X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Flinux%2Fmlx5_os.c;h=d1bf89922ed480c17d43b034f14b407bbc28ad18;hb=c4c3e8afefa8b7e7bc19073f9a159d50c75c8770;hp=aecdc5a68abb5b41885fcaade1c6dc7b77dff8e5;hpb=34776af600df4475799ad8004e76d0eb77c163ff;p=dpdk.git diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index aecdc5a68a..d1bf89922e 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -138,7 +138,7 @@ mlx5_os_set_nonblock_channel_fd(int fd) * Pointer to mlx5 device attributes. * * @return - * 0 on success, non zero error number otherwise + * 0 on success, a negative errno value otherwise and rte_errno is set. */ int mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, @@ -150,8 +150,10 @@ mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, memset(device_attr, 0, sizeof(*device_attr)); err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); - if (err) - return err; + if (err) { + rte_errno = errno; + return -rte_errno; + } device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; device_attr->max_sge = attr_ex.orig_attr.max_sge; @@ -169,9 +171,20 @@ mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; struct mlx5dv_context dv_attr = { .comp_mask = 0 }; +#ifdef HAVE_IBV_MLX5_MOD_SWP + dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; +#endif +#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT + dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; +#endif +#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT + dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; +#endif err = mlx5_glue->dv_query_device(ctx, &dv_attr); - if (err) - return err; + if (err) { + rte_errno = errno; + return -rte_errno; + } device_attr->flags = dv_attr.flags; device_attr->comp_mask = dv_attr.comp_mask; @@ -179,6 +192,7 @@ mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, device_attr->sw_parsing_offloads = dv_attr.sw_parsing_caps.sw_parsing_offloads; #endif +#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT device_attr->min_single_stride_log_num_of_bytes = dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; device_attr->max_single_stride_log_num_of_bytes = @@ -189,13 +203,14 @@ mlx5_os_get_dev_attr(struct mlx5_common_device *cdev, dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; device_attr->stride_supported_qpts = dv_attr.striding_rq_caps.supported_qpts; +#endif #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; #endif strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, sizeof(device_attr->fw_ver)); - return err; + return 0; } /** @@ -671,23 +686,24 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) #ifdef HAVE_IBV_FLOW_DV_SUPPORT struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; bool fallback; #ifndef HAVE_IBV_DEVX_ASYNC fallback = true; #else fallback = false; - if (!sh->devx || !priv->config.dv_flow_en || - !priv->config.hca_attr.flow_counters_dump || - !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || + if (!sh->cdev->config.devx || !priv->config.dv_flow_en || + !hca_attr->flow_counters_dump || + !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) fallback = true; #endif if (fallback) DRV_LOG(INFO, "Use fall-back DV counter management. Flow " "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", - priv->config.hca_attr.flow_counters_dump, - priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); + hca_attr->flow_counters_dump, + hca_attr->flow_counter_bulk_alloc_bitmap); /* Initialize fallback mode only on the port initializes sh. */ if (sh->refcnt == 1) sh->cmng.counter_fallback = fallback; @@ -871,8 +887,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, { const struct mlx5_switch_info *switch_info = &spawn->info; struct mlx5_dev_ctx_shared *sh = NULL; + struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr; struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; - struct mlx5dv_context dv_attr = { .comp_mask = 0 }; struct rte_eth_dev *eth_dev = NULL; struct mlx5_priv *priv = NULL; int err = 0; @@ -964,45 +980,54 @@ err_secondary: mlx5_dev_close(eth_dev); return NULL; } - /* - * Some parameters ("tx_db_nc" in particularly) are needed in - * advance to create dv/verbs device context. We proceed the - * devargs here to get ones, and later proceed devargs again - * to override some hardware settings. - */ + /* Process parameters. */ err = mlx5_args(config, dpdk_dev->devargs); if (err) { - err = rte_errno; DRV_LOG(ERR, "failed to process device arguments: %s", strerror(rte_errno)); - goto error; + return NULL; } + sh = mlx5_alloc_shared_dev_ctx(spawn, config); + if (!sh) + return NULL; + /* Update final values for devargs before check sibling config. */ if (config->dv_miss_info) { if (switch_info->master || switch_info->representor) config->dv_xmeta_en = MLX5_XMETA_MODE_META16; } - sh = mlx5_alloc_shared_dev_ctx(spawn, config); - if (!sh) - return NULL; +#if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) + if (config->dv_flow_en) { + DRV_LOG(WARNING, "DV flow is not supported."); + config->dv_flow_en = 0; + } +#endif +#ifdef HAVE_MLX5DV_DR_ESWITCH + if (!(hca_attr->eswitch_manager && config->dv_flow_en && + (switch_info->representor || switch_info->master))) + config->dv_esw_en = 0; +#else + config->dv_esw_en = 0; +#endif + if (!config->dv_esw_en && + config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { + DRV_LOG(WARNING, + "Metadata mode %u is not supported (no E-Switch).", + config->dv_xmeta_en); + config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; + } + /* Check sibling device configurations. */ + err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev); + if (err) + goto error; #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR config->dest_tir = 1; -#endif -#ifdef HAVE_IBV_MLX5_MOD_SWP - dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; #endif /* * Multi-packet send is supported by ConnectX-4 Lx PF as well * as all ConnectX-5 devices. */ -#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT - dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; -#endif -#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT - dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; -#endif - mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr); - if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { - if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { + if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { + if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { DRV_LOG(DEBUG, "enhanced MPW is supported"); mps = MLX5_MPW_ENHANCED; } else { @@ -1014,46 +1039,41 @@ err_secondary: mps = MLX5_MPW_DISABLED; } #ifdef HAVE_IBV_MLX5_MOD_SWP - if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) - swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; + if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) + swp = sh->device_attr.sw_parsing_offloads; DRV_LOG(DEBUG, "SWP support: %u", swp); #endif config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | MLX5_SW_PARSING_TSO_CAP); #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT - if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { - struct mlx5dv_striding_rq_caps mprq_caps = - dv_attr.striding_rq_caps; - + if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", - mprq_caps.min_single_stride_log_num_of_bytes); + sh->device_attr.min_single_stride_log_num_of_bytes); DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", - mprq_caps.max_single_stride_log_num_of_bytes); + sh->device_attr.max_single_stride_log_num_of_bytes); DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", - mprq_caps.min_single_wqe_log_num_of_strides); + sh->device_attr.min_single_wqe_log_num_of_strides); DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", - mprq_caps.max_single_wqe_log_num_of_strides); + sh->device_attr.max_single_wqe_log_num_of_strides); DRV_LOG(DEBUG, "\tsupported_qpts: %d", - mprq_caps.supported_qpts); + sh->device_attr.stride_supported_qpts); DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d", config->mprq.log_min_stride_wqe_size); DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); mprq = 1; config->mprq.log_min_stride_size = - mprq_caps.min_single_stride_log_num_of_bytes; + sh->device_attr.min_single_stride_log_num_of_bytes; config->mprq.log_max_stride_size = - mprq_caps.max_single_stride_log_num_of_bytes; + sh->device_attr.max_single_stride_log_num_of_bytes; config->mprq.log_min_stride_num = - mprq_caps.min_single_wqe_log_num_of_strides; + sh->device_attr.min_single_wqe_log_num_of_strides; config->mprq.log_max_stride_num = - mprq_caps.max_single_wqe_log_num_of_strides; + sh->device_attr.max_single_wqe_log_num_of_strides; } #endif - /* Rx CQE compression is enabled by default. */ - config->cqe_comp = 1; #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT - if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { - config->tunnel_en = dv_attr.tunnel_offloads_caps & + if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { + config->tunnel_en = sh->device_attr.tunnel_offloads_caps & (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); @@ -1075,9 +1095,9 @@ err_secondary: "tunnel offloading disabled due to old OFED/rdma-core version"); #endif #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT - mpls_en = ((dv_attr.tunnel_offloads_caps & + mpls_en = ((sh->device_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && - (dv_attr.tunnel_offloads_caps & + (sh->device_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", mpls_en ? "" : "not "); @@ -1239,11 +1259,6 @@ err_secondary: DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", priv->dev_port, priv->domain_id); } - /* Override some values set by hardware configuration. */ - mlx5_args(config, dpdk_dev->devargs); - err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev); - if (err) - goto error; config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); DRV_LOG(DEBUG, "checksum offloading is %ssupported", @@ -1251,12 +1266,6 @@ err_secondary: #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) DRV_LOG(DEBUG, "counters are not supported"); -#endif -#if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) - if (config->dv_flow_en) { - DRV_LOG(WARNING, "DV flow is not supported"); - config->dv_flow_en = 0; - } #endif config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; @@ -1304,15 +1313,13 @@ err_secondary: config->mps == MLX5_MPW_ENHANCED ? "enhanced " : config->mps == MLX5_MPW ? "legacy " : "", config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); - if (sh->devx) { - config->hca_attr = sh->cdev->config.hca_attr; - sh->steering_format_version = - config->hca_attr.steering_format_version; + if (sh->cdev->config.devx) { + sh->steering_format_version = hca_attr->steering_format_version; /* Check for LRO support. */ - if (config->dest_tir && config->hca_attr.lro_cap && + if (config->dest_tir && hca_attr->lro_cap && config->dv_flow_en) { /* TBD check tunnel lro caps. */ - config->lro.supported = config->hca_attr.lro_cap; + config->lro.supported = hca_attr->lro_cap; DRV_LOG(DEBUG, "Device supports LRO"); /* * If LRO timeout is not configured by application, @@ -1320,21 +1327,19 @@ err_secondary: */ if (!config->lro.timeout) config->lro.timeout = - config->hca_attr.lro_timer_supported_periods[0]; + hca_attr->lro_timer_supported_periods[0]; DRV_LOG(DEBUG, "LRO session timeout set to %d usec", config->lro.timeout); DRV_LOG(DEBUG, "LRO minimal size of TCP segment " "required for coalescing is %d bytes", - config->hca_attr.lro_min_mss_size); + hca_attr->lro_min_mss_size); } #if defined(HAVE_MLX5DV_DR) && \ (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) - if (config->hca_attr.qos.sup && - config->hca_attr.qos.flow_meter_old && + if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && config->dv_flow_en) { - uint8_t reg_c_mask = - config->hca_attr.qos.flow_meter_reg_c_ids; + uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; /* * Meter needs two REG_C's for color match and pre-sfx * flow match. Here get the REG_C for color match. @@ -1358,20 +1363,18 @@ err_secondary: priv->mtr_color_reg = ffs(reg_c_mask) - 1 + REG_C_0; priv->mtr_en = 1; - priv->mtr_reg_share = - config->hca_attr.qos.flow_meter; + priv->mtr_reg_share = hca_attr->qos.flow_meter; DRV_LOG(DEBUG, "The REG_C meter uses is %d", priv->mtr_color_reg); } } - if (config->hca_attr.qos.sup && - config->hca_attr.qos.flow_meter_aso_sup) { + if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); if (log_obj_size >= - config->hca_attr.qos.log_meter_aso_granularity && - log_obj_size <= - config->hca_attr.qos.log_meter_aso_max_alloc) + hca_attr->qos.log_meter_aso_granularity && + log_obj_size <= + hca_attr->qos.log_meter_aso_max_alloc) sh->meter_aso_en = 1; } if (priv->mtr_en) { @@ -1381,12 +1384,11 @@ err_secondary: goto error; } } - if (config->hca_attr.flow.tunnel_header_0_1) + if (hca_attr->flow.tunnel_header_0_1) sh->tunnel_header_0_1 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO - if (config->hca_attr.flow_hit_aso && - priv->mtr_color_reg == REG_C_3) { + if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { sh->flow_hit_aso_en = 1; err = mlx5_flow_aso_age_mng_init(sh); if (err) { @@ -1398,8 +1400,7 @@ err_secondary: #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ defined(HAVE_MLX5_DR_ACTION_ASO_CT) - if (config->hca_attr.ct_offload && - priv->mtr_color_reg == REG_C_3) { + if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { err = mlx5_flow_aso_ct_mng_init(sh); if (err) { err = -err; @@ -1410,13 +1411,13 @@ err_secondary: } #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) - if (config->hca_attr.log_max_ft_sampler_num > 0 && + if (hca_attr->log_max_ft_sampler_num > 0 && config->dv_flow_en) { priv->sampler_en = 1; DRV_LOG(DEBUG, "Sampler enabled!"); } else { priv->sampler_en = 0; - if (!config->hca_attr.log_max_ft_sampler_num) + if (!hca_attr->log_max_ft_sampler_num) DRV_LOG(WARNING, "No available register for sampler."); else @@ -1425,18 +1426,18 @@ err_secondary: #endif } if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && - !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { + !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); config->cqe_comp = 0; } if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && - (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { + (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) { DRV_LOG(WARNING, "Flow Tag CQE compression" " format isn't supported."); config->cqe_comp = 0; } if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && - (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { + (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { DRV_LOG(WARNING, "L3/L4 Header CQE compression" " format isn't supported."); config->cqe_comp = 0; @@ -1445,55 +1446,55 @@ err_secondary: config->cqe_comp ? "" : "not "); if (config->tx_pp) { DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", - config->hca_attr.dev_freq_khz); + hca_attr->dev_freq_khz); DRV_LOG(DEBUG, "Packet pacing is %ssupported", - config->hca_attr.qos.packet_pacing ? "" : "not "); + hca_attr->qos.packet_pacing ? "" : "not "); DRV_LOG(DEBUG, "Cross channel ops are %ssupported", - config->hca_attr.cross_channel ? "" : "not "); + hca_attr->cross_channel ? "" : "not "); DRV_LOG(DEBUG, "WQE index ignore is %ssupported", - config->hca_attr.wqe_index_ignore ? "" : "not "); + hca_attr->wqe_index_ignore ? "" : "not "); DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", - config->hca_attr.non_wire_sq ? "" : "not "); + hca_attr->non_wire_sq ? "" : "not "); DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", - config->hca_attr.log_max_static_sq_wq ? "" : "not ", - config->hca_attr.log_max_static_sq_wq); + hca_attr->log_max_static_sq_wq ? "" : "not ", + hca_attr->log_max_static_sq_wq); DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", - config->hca_attr.qos.wqe_rate_pp ? "" : "not "); - if (!sh->devx) { + hca_attr->qos.wqe_rate_pp ? "" : "not "); + if (!sh->cdev->config.devx) { DRV_LOG(ERR, "DevX is required for packet pacing"); err = ENODEV; goto error; } - if (!config->hca_attr.qos.packet_pacing) { + if (!hca_attr->qos.packet_pacing) { DRV_LOG(ERR, "Packet pacing is not supported"); err = ENODEV; goto error; } - if (!config->hca_attr.cross_channel) { + if (!hca_attr->cross_channel) { DRV_LOG(ERR, "Cross channel operations are" " required for packet pacing"); err = ENODEV; goto error; } - if (!config->hca_attr.wqe_index_ignore) { + if (!hca_attr->wqe_index_ignore) { DRV_LOG(ERR, "WQE index ignore feature is" " required for packet pacing"); err = ENODEV; goto error; } - if (!config->hca_attr.non_wire_sq) { + if (!hca_attr->non_wire_sq) { DRV_LOG(ERR, "Non-wire SQ feature is" " required for packet pacing"); err = ENODEV; goto error; } - if (!config->hca_attr.log_max_static_sq_wq) { + if (!hca_attr->log_max_static_sq_wq) { DRV_LOG(ERR, "Static WQE SQ feature is" " required for packet pacing"); err = ENODEV; goto error; } - if (!config->hca_attr.qos.wqe_rate_pp) { + if (!hca_attr->qos.wqe_rate_pp) { DRV_LOG(ERR, "WQE rate mode is required" " for packet pacing"); err = ENODEV; @@ -1507,7 +1508,7 @@ err_secondary: #endif } if (config->std_delay_drop || config->hp_delay_drop) { - if (!config->hca_attr.rq_delay_drop) { + if (!hca_attr->rq_delay_drop) { config->std_delay_drop = 0; config->hp_delay_drop = 0; DRV_LOG(WARNING, @@ -1515,10 +1516,10 @@ err_secondary: priv->dev_port); } } - if (sh->devx) { + if (sh->cdev->config.devx) { uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; - err = config->hca_attr.access_register_user ? + err = hca_attr->access_register_user ? mlx5_devx_cmd_register_read (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0, reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; @@ -1532,8 +1533,7 @@ err_secondary: config->rt_timestamp = 1; } else { /* Kernel does not support register reading. */ - if (config->hca_attr.dev_freq_khz == - (NS_PER_S / MS_PER_S)) + if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) config->rt_timestamp = 1; } } @@ -1542,7 +1542,7 @@ err_secondary: * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. */ - if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) + if (hca_attr->scatter_fcs_w_decap_disable && config->decap_en) config->hw_fcs_strip = 0; DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", (config->hw_fcs_strip ? "" : "not ")); @@ -1623,8 +1623,8 @@ err_secondary: DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, priv->mtu); /* Initialize burst functions to prevent crashes before link-up. */ - eth_dev->rx_pkt_burst = removed_rx_burst; - eth_dev->tx_pkt_burst = removed_tx_burst; + eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; + eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; eth_dev->dev_ops = &mlx5_dev_ops; eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; @@ -1652,13 +1652,6 @@ err_secondary: * Verbs context returned by ibv_open_device(). */ mlx5_link_update(eth_dev, 0); -#ifdef HAVE_MLX5DV_DR_ESWITCH - if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && - (switch_info->representor || switch_info->master))) - config->dv_esw_en = 0; -#else - config->dv_esw_en = 0; -#endif /* Detect minimal data bytes to inline. */ mlx5_set_min_inline(spawn, config); /* Store device configuration on private structure. */ @@ -1680,7 +1673,7 @@ err_secondary: if (mlx5_flex_item_port_init(eth_dev) < 0) goto error; } - if (sh->devx && config->dv_flow_en && config->dest_tir) { + if (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) { priv->obj_ops = devx_obj_ops; mlx5_queue_counter_id_prepare(eth_dev); priv->obj_ops.lb_dummy_queue_create = @@ -1725,12 +1718,6 @@ err_secondary: err = -err; goto error; } - if (!priv->config.dv_esw_en && - priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { - DRV_LOG(WARNING, "metadata mode %u is not supported " - "(no E-Switch)", priv->config.dv_xmeta_en); - priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; - } mlx5_set_metadata_mask(eth_dev); if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && !priv->sh->dv_regc0_mask) { @@ -2042,6 +2029,7 @@ mlx5_os_config_default(struct mlx5_dev_config *config, { memset(config, 0, sizeof(*config)); config->mps = MLX5_ARG_UNSET; + config->cqe_comp = 1; config->rx_vec_en = 1; config->txq_inline_max = MLX5_ARG_UNSET; config->txq_inline_min = MLX5_ARG_UNSET; @@ -2112,7 +2100,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); struct mlx5_dev_spawn_data *list = NULL; struct mlx5_dev_config dev_config; - unsigned int dev_config_vf; struct rte_eth_devargs eth_da = *req_eth_da; struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ struct mlx5_bond_info bond_info; @@ -2433,21 +2420,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, * (i.e. master first, then representors from lowest to highest ID). */ qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); - /* Device specific configuration. */ - switch (pci_dev->id.device_id) { - case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: - case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: - dev_config_vf = 1; - break; - default: - dev_config_vf = 0; - break; - } if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { /* Set devargs default values. */ if (eth_da.nb_mh_controllers == 0) { @@ -2471,7 +2443,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, /* Default configuration. */ mlx5_os_config_default(&dev_config, &cdev->config); - dev_config.vf = dev_config_vf; + dev_config.vf = mlx5_dev_is_vf_pci(pci_dev); list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], &dev_config, ð_da); if (!list[i].eth_dev) { @@ -2744,7 +2716,7 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) rte_intr_fd_set(sh->intr_handle, -1); } } - if (sh->devx) { + if (sh->cdev->config.devx) { #ifdef HAVE_IBV_DEVX_ASYNC sh->intr_handle_devx = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);