X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Flinux%2Fmlx5_verbs.c;h=67a7bec22beaae086969eeebf2b8180cbb1ef787;hb=1485d961e2c9d77dfa4900a16b5ba70cbaa4c7ce;hp=58556d2bf0264ba3b989eb4a59388cbef2728e15;hpb=5dfa003db53f6e901dce02dab594e230555c8f33;p=dpdk.git diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c index 58556d2bf0..67a7bec22b 100644 --- a/drivers/net/mlx5/linux/mlx5_verbs.c +++ b/drivers/net/mlx5/linux/mlx5_verbs.c @@ -94,7 +94,6 @@ mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, .qp_state = IBV_QPS_RESET, .port_num = dev_port, }; - int attr_mask = (IBV_QP_STATE | IBV_QP_PORT); int ret; if (type != MLX5_TXQ_MOD_RST2RDY) { @@ -108,10 +107,8 @@ mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, if (type == MLX5_TXQ_MOD_RDY2RST) return 0; } - if (type == MLX5_TXQ_MOD_ERR2RDY) - attr_mask = IBV_QP_STATE; mod.qp_state = IBV_QPS_INIT; - ret = mlx5_glue->modify_qp(obj->qp, &mod, attr_mask); + ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE | IBV_QP_PORT); if (ret) { DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s", strerror(errno)); @@ -272,8 +269,8 @@ mlx5_rxq_ibv_wq_create(struct mlx5_rxq_priv *rxq) wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ; *mprq_attr = (struct mlx5dv_striding_rq_init_attr){ - .single_stride_log_num_of_bytes = rxq_data->strd_sz_n, - .single_wqe_log_num_of_strides = rxq_data->strd_num_n, + .single_stride_log_num_of_bytes = rxq_data->log_strd_sz, + .single_wqe_log_num_of_strides = rxq_data->log_strd_num, .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT, }; } @@ -872,13 +869,12 @@ mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx) /* CQ to be associated with the receive queue. */ qp_attr.recv_cq = txq_ctrl->obj->cq; /* Max number of outstanding WRs. */ - qp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ? - priv->sh->device_attr.max_qp_wr : desc); + qp_attr.cap.max_send_wr = RTE_MIN(priv->sh->dev_cap.max_qp_wr, desc); /* * Max number of scatter/gather elements in a WR, must be 1 to prevent * libmlx5 from trying to affect must be 1 to prevent libmlx5 from * trying to affect too much memory. TX gather is not impacted by the - * device_attr.max_sge limit and will still work properly. + * dev_cap.max_sge limit and will still work properly. */ qp_attr.cap.max_send_sge = 1; qp_attr.qp_type = IBV_QPT_RAW_PACKET, @@ -927,7 +923,7 @@ mlx5_txq_ibv_uar_init(struct mlx5_txq_ctrl *txq_ctrl, void *bf_reg) DRV_LOG(ERR, "Failed to get mem page size"); rte_errno = ENOMEM; } - txq->db_heu = priv->sh->cdev->config.dbnc == MLX5_TXDB_HEURISTIC; + txq->db_heu = priv->sh->cdev->config.dbnc == MLX5_SQ_DB_HEURISTIC; txq->db_nc = mlx5_db_map_type_get(uar_mmap_offset, page_size); ppriv->uar_table[txq->idx].db = bf_reg; #ifndef RTE_ARCH_64 @@ -998,7 +994,7 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET; #ifdef HAVE_IBV_FLOW_DV_SUPPORT /* If using DevX, need additional mask to read tisn value. */ - if (priv->sh->devx && !priv->sh->tdn) + if (priv->sh->cdev->config.devx && !priv->sh->tdn) qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES; #endif obj.cq.in = txq_obj->cq; @@ -1036,13 +1032,17 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) txq_data->wqe_pi = 0; txq_data->wqe_comp = 0; txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV; + txq_data->wait_on_time = !!(!priv->sh->config.tx_pp && + priv->sh->cdev->config.hca_attr.wait_on_time && + txq_data->offloads & + RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP); #ifdef HAVE_IBV_FLOW_DV_SUPPORT /* * If using DevX need to query and store TIS transport domain value. * This is done once per port. * Will use this value on Rx, when creating matching TIR. */ - if (priv->sh->devx && !priv->sh->tdn) { + if (priv->sh->cdev->config.devx && !priv->sh->tdn) { ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn, &priv->sh->tdn); if (ret) {