X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.c;h=0528ed35e206827b01122519f25c073241813abe;hb=62e3ccc2b94c625d4b3ce55044b135c4ab0793db;hp=2b7a6d121fd451175d8b01d0fe5c886204019b52;hpb=2aac5b5d119f425964868a7e530e95d18af9e31c;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 2b7a6d121f..0528ed35e2 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -32,11 +32,11 @@ #include #include #include -#include #include #include #include #include +#include #include "mlx5.h" #include "mlx5_utils.h" @@ -68,9 +68,18 @@ /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" -/* Device parameter to configure inline send. */ +/* Device parameter to configure inline send. Deprecated, ignored.*/ #define MLX5_TXQ_INLINE "txq_inline" +/* Device parameter to limit packet size to inline with ordinary SEND. */ +#define MLX5_TXQ_INLINE_MAX "txq_inline_max" + +/* Device parameter to configure minimal data size to inline. */ +#define MLX5_TXQ_INLINE_MIN "txq_inline_min" + +/* Device parameter to limit packet size to inline with Enhanced MPW. */ +#define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" + /* * Device parameter to configure the number of TX queues threshold for * enabling inline send. @@ -79,20 +88,29 @@ /* * Device parameter to configure the number of TX queues threshold for - * enabling vectorized Tx. + * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). */ #define MLX5_TXQS_MAX_VEC "txqs_max_vec" /* Device parameter to enable multi-packet send WQEs. */ #define MLX5_TXQ_MPW_EN "txq_mpw_en" -/* Device parameter to include 2 dsegs in the title WQEBB. */ +/* + * Device parameter to include 2 dsegs in the title WQEBB. + * Deprecated, ignored. + */ #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" -/* Device parameter to limit the size of inlining packet. */ +/* + * Device parameter to limit the size of inlining packet. + * Deprecated, ignored. + */ #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" -/* Device parameter to enable hardware Tx vector. */ +/* + * Device parameter to enable hardware Tx vector. + * Deprecated, ignored (no vectorized Tx routines anymore). + */ #define MLX5_TX_VEC_EN "tx_vec_en" /* Device parameter to enable hardware Rx vector. */ @@ -101,15 +119,27 @@ /* Allow L3 VXLAN flow creation. */ #define MLX5_L3_VXLAN_EN "l3_vxlan_en" +/* Activate DV E-Switch flow steering. */ +#define MLX5_DV_ESW_EN "dv_esw_en" + /* Activate DV flow steering. */ #define MLX5_DV_FLOW_EN "dv_flow_en" /* Activate Netlink support in VF mode. */ #define MLX5_VF_NL_EN "vf_nl_en" +/* Enable extending memsegs when creating a MR. */ +#define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" + /* Select port representors to instantiate. */ #define MLX5_REPRESENTOR "representor" +/* Device parameter to configure the maximum number of dump files per queue. */ +#define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" + +/* Configure timeout of LRO session (in microseconds). */ +#define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" + #ifndef HAVE_IBV_MLX5_MOD_MPW #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) @@ -141,18 +171,141 @@ struct mlx5_dev_spawn_data { struct mlx5_switch_info info; /**< Switch information. */ struct ibv_device *ibv_dev; /**< Associated IB device. */ struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ + struct rte_pci_device *pci_dev; /**< Backend PCI device. */ }; static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; +/** + * Initialize the counters management structure. + * + * @param[in] sh + * Pointer to mlx5_ibv_shared object to free + */ +static void +mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh) +{ + uint8_t i; + + TAILQ_INIT(&sh->cmng.flow_counters); + for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) + TAILQ_INIT(&sh->cmng.ccont[i].pool_list); +} + +/** + * Destroy all the resources allocated for a counter memory management. + * + * @param[in] mng + * Pointer to the memory management structure. + */ +static void +mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) +{ + uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; + + LIST_REMOVE(mng, next); + claim_zero(mlx5_devx_cmd_destroy(mng->dm)); + claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); + rte_free(mem); +} + +/** + * Close and release all the resources of the counters management. + * + * @param[in] sh + * Pointer to mlx5_ibv_shared object to free. + */ +static void +mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh) +{ + struct mlx5_counter_stats_mem_mng *mng; + uint8_t i; + int j; + int retries = 1024; + + rte_errno = 0; + while (--retries) { + rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); + if (rte_errno != EINPROGRESS) + break; + rte_pause(); + } + for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) { + struct mlx5_flow_counter_pool *pool; + uint32_t batch = !!(i % 2); + + if (!sh->cmng.ccont[i].pools) + continue; + pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); + while (pool) { + if (batch) { + if (pool->min_dcs) + claim_zero + (mlx5_devx_cmd_destroy(pool->min_dcs)); + } + for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { + if (pool->counters_raw[j].action) + claim_zero + (mlx5_glue->destroy_flow_action + (pool->counters_raw[j].action)); + if (!batch && pool->counters_raw[j].dcs) + claim_zero(mlx5_devx_cmd_destroy + (pool->counters_raw[j].dcs)); + } + TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, + next); + rte_free(pool); + pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); + } + rte_free(sh->cmng.ccont[i].pools); + } + mng = LIST_FIRST(&sh->cmng.mem_mngs); + while (mng) { + mlx5_flow_destroy_counter_stat_mem_mng(mng); + mng = LIST_FIRST(&sh->cmng.mem_mngs); + } + memset(&sh->cmng, 0, sizeof(sh->cmng)); +} + +/** + * Extract pdn of PD object using DV API. + * + * @param[in] pd + * Pointer to the verbs PD object. + * @param[out] pdn + * Pointer to the PD object number variable. + * + * @return + * 0 on success, error value otherwise. + */ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT +static int +mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused) +{ + struct mlx5dv_obj obj; + struct mlx5dv_pd pd_info; + int ret = 0; + + obj.pd.in = pd; + obj.pd.out = &pd_info; + ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); + if (ret) { + DRV_LOG(DEBUG, "Fail to get PD object info"); + return ret; + } + *pdn = pd_info.pdn; + return 0; +} +#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ + /** * Allocate shared IB device context. If there is multiport device the * master and representors will share this context, if there is single * port dedicated IB device, the context will be used by only given * port due to unification. * - * Routine first searches the context for the spesified IB device name, + * Routine first searches the context for the specified IB device name, * if found the shared context assumed and reference counter is incremented. * If no context found the new one is created and initialized with specified * IB device context and parameters. @@ -182,7 +335,7 @@ mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) goto exit; } } - /* No device found, we have to create new sharted context. */ + /* No device found, we have to create new shared context. */ assert(spawn->max_port); sh = rte_zmalloc("ethdev shared ib context", sizeof(struct mlx5_ibv_shared) + @@ -219,6 +372,7 @@ mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) sizeof(sh->ibdev_name)); strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, sizeof(sh->ibdev_path)); + sh->pci_dev = spawn->pci_dev; pthread_mutex_init(&sh->intr_mutex, NULL); /* * Setting port_id to max unallowed value means @@ -233,6 +387,36 @@ mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) err = ENOMEM; goto error; } +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + err = mlx5_get_pdn(sh->pd, &sh->pdn); + if (err) { + DRV_LOG(ERR, "Fail to extract pdn from PD"); + goto error; + } +#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ + /* + * Once the device is added to the list of memory event + * callback, its global MR cache table cannot be expanded + * on the fly because of deadlock. If it overflows, lookup + * should be done by searching MR list linearly, which is slow. + * + * At this point the device is not added to the memory + * event list yet, context is just being created. + */ + err = mlx5_mr_btree_init(&sh->mr.cache, + MLX5_MR_BTREE_CACHE_N * 2, + sh->pci_dev->device.numa_node); + if (err) { + err = rte_errno; + goto error; + } + mlx5_flow_counters_mng_init(sh); + /* Add device to memory callback list. */ + rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); + LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, + sh, mem_event_cb); + rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); + /* Add context to the global device list. */ LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); exit: pthread_mutex_unlock(&mlx5_ibv_list_mutex); @@ -280,14 +464,22 @@ mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) assert(rte_eal_process_type() == RTE_PROC_PRIMARY); if (--sh->refcnt) goto exit; + /* Release created Memory Regions. */ + mlx5_mr_release(sh); + /* Remove from memory callback device list. */ + rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); + LIST_REMOVE(sh, mem_event_cb); + rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); + /* Remove context from the global device list. */ LIST_REMOVE(sh, next); /* * Ensure there is no async event handler installed. * Only primary process handles async device events. **/ + mlx5_flow_counters_mng_close(sh); assert(!sh->intr_cnt); if (sh->intr_cnt) - rte_intr_callback_unregister + mlx5_intr_callback_unregister (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); pthread_mutex_destroy(&sh->intr_mutex); if (sh->pd) @@ -299,6 +491,145 @@ exit: pthread_mutex_unlock(&mlx5_ibv_list_mutex); } +/** + * Initialize DR related data within private structure. + * Routine checks the reference counter and does actual + * resources creation/initialization only if counter is zero. + * + * @param[in] priv + * Pointer to the private device data structure. + * + * @return + * Zero on success, positive error code otherwise. + */ +static int +mlx5_alloc_shared_dr(struct mlx5_priv *priv) +{ +#ifdef HAVE_MLX5DV_DR + struct mlx5_ibv_shared *sh = priv->sh; + int err = 0; + void *domain; + + assert(sh); + if (sh->dv_refcnt) { + /* Shared DV/DR structures is already initialized. */ + sh->dv_refcnt++; + priv->dr_shared = 1; + return 0; + } + /* Reference counter is zero, we should initialize structures. */ + domain = mlx5_glue->dr_create_domain(sh->ctx, + MLX5DV_DR_DOMAIN_TYPE_NIC_RX); + if (!domain) { + DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); + err = errno; + goto error; + } + sh->rx_domain = domain; + domain = mlx5_glue->dr_create_domain(sh->ctx, + MLX5DV_DR_DOMAIN_TYPE_NIC_TX); + if (!domain) { + DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); + err = errno; + goto error; + } + pthread_mutex_init(&sh->dv_mutex, NULL); + sh->tx_domain = domain; +#ifdef HAVE_MLX5DV_DR_ESWITCH + if (priv->config.dv_esw_en) { + domain = mlx5_glue->dr_create_domain + (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); + if (!domain) { + DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); + err = errno; + goto error; + } + sh->fdb_domain = domain; + sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); + } +#endif + sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); + sh->dv_refcnt++; + priv->dr_shared = 1; + return 0; + +error: + /* Rollback the created objects. */ + if (sh->rx_domain) { + mlx5_glue->dr_destroy_domain(sh->rx_domain); + sh->rx_domain = NULL; + } + if (sh->tx_domain) { + mlx5_glue->dr_destroy_domain(sh->tx_domain); + sh->tx_domain = NULL; + } + if (sh->fdb_domain) { + mlx5_glue->dr_destroy_domain(sh->fdb_domain); + sh->fdb_domain = NULL; + } + if (sh->esw_drop_action) { + mlx5_glue->destroy_flow_action(sh->esw_drop_action); + sh->esw_drop_action = NULL; + } + if (sh->pop_vlan_action) { + mlx5_glue->destroy_flow_action(sh->pop_vlan_action); + sh->pop_vlan_action = NULL; + } + return err; +#else + (void)priv; + return 0; +#endif +} + +/** + * Destroy DR related data within private structure. + * + * @param[in] priv + * Pointer to the private device data structure. + */ +static void +mlx5_free_shared_dr(struct mlx5_priv *priv) +{ +#ifdef HAVE_MLX5DV_DR + struct mlx5_ibv_shared *sh; + + if (!priv->dr_shared) + return; + priv->dr_shared = 0; + sh = priv->sh; + assert(sh); + assert(sh->dv_refcnt); + if (sh->dv_refcnt && --sh->dv_refcnt) + return; + if (sh->rx_domain) { + mlx5_glue->dr_destroy_domain(sh->rx_domain); + sh->rx_domain = NULL; + } + if (sh->tx_domain) { + mlx5_glue->dr_destroy_domain(sh->tx_domain); + sh->tx_domain = NULL; + } +#ifdef HAVE_MLX5DV_DR_ESWITCH + if (sh->fdb_domain) { + mlx5_glue->dr_destroy_domain(sh->fdb_domain); + sh->fdb_domain = NULL; + } + if (sh->esw_drop_action) { + mlx5_glue->destroy_flow_action(sh->esw_drop_action); + sh->esw_drop_action = NULL; + } +#endif + if (sh->pop_vlan_action) { + mlx5_glue->destroy_flow_action(sh->pop_vlan_action); + sh->pop_vlan_action = NULL; + } + pthread_mutex_destroy(&sh->dv_mutex); +#else + (void)priv; +#endif +} + /** * Initialize shared data between primary and secondary process. * @@ -348,30 +679,6 @@ error: return ret; } -/** - * Uninitialize shared data between primary and secondary process. - * - * The pointer of secondary process is dereferenced and primary process frees - * the memzone. - */ -static void -mlx5_uninit_shared_data(void) -{ - const struct rte_memzone *mz; - - rte_spinlock_lock(&mlx5_shared_data_lock); - if (mlx5_shared_data) { - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); - rte_memzone_free(mz); - } else { - memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); - } - mlx5_shared_data = NULL; - } - rte_spinlock_unlock(&mlx5_shared_data_lock); -} - /** * Retrieve integer value from environment variable. * @@ -445,6 +752,79 @@ mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) rte_free(ptr); } +/** + * DPDK callback to add udp tunnel port + * + * @param[in] dev + * A pointer to eth_dev + * @param[in] udp_tunnel + * A pointer to udp tunnel + * + * @return + * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. + */ +int +mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_udp_tunnel *udp_tunnel) +{ + assert(udp_tunnel != NULL); + if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN && + udp_tunnel->udp_port == 4789) + return 0; + if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE && + udp_tunnel->udp_port == 4790) + return 0; + return -ENOTSUP; +} + +/** + * Initialize process private data structure. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_proc_priv_init(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_proc_priv *ppriv; + size_t ppriv_size; + + /* + * UAR register table follows the process private structure. BlueFlame + * registers for Tx queues are stored in the table. + */ + ppriv_size = + sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); + ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, + RTE_CACHE_LINE_SIZE, dev->device->numa_node); + if (!ppriv) { + rte_errno = ENOMEM; + return -rte_errno; + } + ppriv->uar_table_sz = ppriv_size; + dev->process_private = ppriv; + return 0; +} + +/** + * Un-initialize process private data structure. + * + * @param dev + * Pointer to Ethernet device structure. + */ +static void +mlx5_proc_priv_uninit(struct rte_eth_dev *dev) +{ + if (!dev->process_private) + return; + rte_free(dev->process_private); + dev->process_private = NULL; +} + /** * DPDK callback to close the device. * @@ -489,12 +869,9 @@ mlx5_dev_close(struct rte_eth_dev *dev) priv->txqs_n = 0; priv->txqs = NULL; } + mlx5_proc_priv_uninit(dev); mlx5_mprq_free_mp(dev); - mlx5_mr_release(dev); - assert(priv->sh); - if (priv->sh) - mlx5_free_shared_ibctx(priv->sh); - priv->sh = NULL; + mlx5_free_shared_dr(priv); if (priv->rss_conf.rss_key != NULL) rte_free(priv->rss_conf.rss_key); if (priv->reta_idx != NULL) @@ -505,19 +882,29 @@ mlx5_dev_close(struct rte_eth_dev *dev) close(priv->nl_socket_route); if (priv->nl_socket_rdma >= 0) close(priv->nl_socket_rdma); - if (priv->tcf_context) - mlx5_flow_tcf_context_destroy(priv->tcf_context); - ret = mlx5_hrxq_ibv_verify(dev); + if (priv->vmwa_context) + mlx5_vlan_vmwa_exit(priv->vmwa_context); + if (priv->sh) { + /* + * Free the shared context in last turn, because the cleanup + * routines above may use some shared fields, like + * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing + * ifindex if Netlink fails. + */ + mlx5_free_shared_ibctx(priv->sh); + priv->sh = NULL; + } + ret = mlx5_hrxq_verify(dev); if (ret) DRV_LOG(WARNING, "port %u some hash Rx queue still remain", dev->data->port_id); - ret = mlx5_ind_table_ibv_verify(dev); + ret = mlx5_ind_table_obj_verify(dev); if (ret) DRV_LOG(WARNING, "port %u some indirection table still remain", dev->data->port_id); - ret = mlx5_rxq_ibv_verify(dev); + ret = mlx5_rxq_obj_verify(dev); if (ret) - DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", + DRV_LOG(WARNING, "port %u some Rx queue objects still remain", dev->data->port_id); ret = mlx5_rxq_verify(dev); if (ret) @@ -537,17 +924,15 @@ mlx5_dev_close(struct rte_eth_dev *dev) dev->data->port_id); if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { unsigned int c = 0; - unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); - uint16_t port_id[i]; + uint16_t port_id; - i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); - while (i--) { + RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) { struct mlx5_priv *opriv = - rte_eth_devices[port_id[i]].data->dev_private; + rte_eth_devices[port_id].data->dev_private; if (!opriv || opriv->domain_id != priv->domain_id || - &rte_eth_devices[port_id[i]] == dev) + &rte_eth_devices[port_id] == dev) continue; ++c; } @@ -583,6 +968,7 @@ const struct eth_dev_ops mlx5_dev_ops = { .xstats_get_names = mlx5_xstats_get_names, .fw_version_get = mlx5_fw_version_get, .dev_infos_get = mlx5_dev_infos_get, + .read_clock = mlx5_read_clock, .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, .vlan_filter_set = mlx5_vlan_filter_set, .rx_queue_setup = mlx5_rx_queue_setup, @@ -609,6 +995,9 @@ const struct eth_dev_ops mlx5_dev_ops = { .rx_queue_intr_enable = mlx5_rx_intr_enable, .rx_queue_intr_disable = mlx5_rx_intr_disable, .is_removed = mlx5_is_removed, + .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, }; /* Available operations from secondary process. */ @@ -622,6 +1011,8 @@ static const struct eth_dev_ops mlx5_dev_sec_ops = { .dev_infos_get = mlx5_dev_infos_get, .rx_descriptor_status = mlx5_rx_descriptor_status, .tx_descriptor_status = mlx5_tx_descriptor_status, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, }; /* Available operations in flow isolated mode. */ @@ -665,6 +1056,8 @@ const struct eth_dev_ops mlx5_dev_ops_isolate = { .rx_queue_intr_enable = mlx5_rx_intr_enable, .rx_queue_intr_disable = mlx5_rx_intr_disable, .is_removed = mlx5_is_removed, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, }; /** @@ -711,27 +1104,45 @@ mlx5_args_check(const char *key, const char *val, void *opaque) } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { config->mprq.min_rxqs_num = tmp; } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { - config->txq_inline = tmp; + DRV_LOG(WARNING, "%s: deprecated parameter," + " converted to txq_inline_max", key); + config->txq_inline_max = tmp; + } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { + config->txq_inline_max = tmp; + } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { + config->txq_inline_min = tmp; + } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { + config->txq_inline_mpw = tmp; } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { config->txqs_inline = tmp; } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { - config->txqs_vec = tmp; + DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { config->mps = !!tmp; } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { - config->mpw_hdr_dseg = !!tmp; + DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { - config->inline_max_packet_sz = tmp; + DRV_LOG(WARNING, "%s: deprecated parameter," + " converted to txq_inline_mpw", key); + config->txq_inline_mpw = tmp; } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { - config->tx_vec_en = !!tmp; + DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { config->rx_vec_en = !!tmp; } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { config->l3_vxlan_en = !!tmp; } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { config->vf_nl_en = !!tmp; + } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { + config->dv_esw_en = !!tmp; } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { config->dv_flow_en = !!tmp; + } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { + config->mr_ext_memseg_en = !!tmp; + } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { + config->max_dump_files_num = tmp; + } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { + config->lro.timeout = tmp; } else { DRV_LOG(WARNING, "%s: unknown parameter", key); rte_errno = EINVAL; @@ -763,6 +1174,9 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_RX_MPRQ_MAX_MEMCPY_LEN, MLX5_RXQS_MIN_MPRQ, MLX5_TXQ_INLINE, + MLX5_TXQ_INLINE_MIN, + MLX5_TXQ_INLINE_MAX, + MLX5_TXQ_INLINE_MPW, MLX5_TXQS_MIN_INLINE, MLX5_TXQS_MAX_VEC, MLX5_TXQ_MPW_EN, @@ -772,8 +1186,12 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_RX_VEC_EN, MLX5_L3_VXLAN_EN, MLX5_VF_NL_EN, + MLX5_DV_ESW_EN, MLX5_DV_FLOW_EN, + MLX5_MR_EXT_MEMSEG_EN, MLX5_REPRESENTOR, + MLX5_MAX_DUMP_FILES_NUM, + MLX5_LRO_TIMEOUT_USEC, NULL, }; struct rte_kvargs *kvlist; @@ -784,8 +1202,10 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) return 0; /* Following UGLY cast is done to pass checkpatch. */ kvlist = rte_kvargs_parse(devargs->args, params); - if (kvlist == NULL) - return 0; + if (kvlist == NULL) { + rte_errno = EINVAL; + return -rte_errno; + } /* Process parameters. */ for (i = 0; (params[i] != NULL); ++i) { if (rte_kvargs_count(kvlist, params[i])) { @@ -804,132 +1224,6 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) static struct rte_pci_driver mlx5_driver; -static int -find_lower_va_bound(const struct rte_memseg_list *msl, - const struct rte_memseg *ms, void *arg) -{ - void **addr = arg; - - if (msl->external) - return 0; - if (*addr == NULL) - *addr = ms->addr; - else - *addr = RTE_MIN(*addr, ms->addr); - - return 0; -} - -/** - * Reserve UAR address space for primary process. - * - * Process local resource is used by both primary and secondary to avoid - * duplicate reservation. The space has to be available on both primary and - * secondary process, TXQ UAR maps to this area using fixed mmap w/o double - * check. - * - * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. - */ -static int -mlx5_uar_init_primary(void) -{ - struct mlx5_shared_data *sd = mlx5_shared_data; - void *addr = (void *)0; - - if (sd->uar_base) - return 0; - /* find out lower bound of hugepage segments */ - rte_memseg_walk(find_lower_va_bound, &addr); - /* keep distance to hugepages to minimize potential conflicts. */ - addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); - /* anonymous mmap, no real memory consumption. */ - addr = mmap(addr, MLX5_UAR_SIZE, - PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - if (addr == MAP_FAILED) { - DRV_LOG(ERR, - "Failed to reserve UAR address space, please" - " adjust MLX5_UAR_SIZE or try --base-virtaddr"); - rte_errno = ENOMEM; - return -rte_errno; - } - /* Accept either same addr or a new addr returned from mmap if target - * range occupied. - */ - DRV_LOG(INFO, "Reserved UAR address space: %p", addr); - sd->uar_base = addr; /* for primary and secondary UAR re-mmap. */ - return 0; -} - -/** - * Unmap UAR address space reserved for primary process. - */ -static void -mlx5_uar_uninit_primary(void) -{ - struct mlx5_shared_data *sd = mlx5_shared_data; - - if (!sd->uar_base) - return; - munmap(sd->uar_base, MLX5_UAR_SIZE); - sd->uar_base = NULL; -} - -/** - * Reserve UAR address space for secondary process, align with primary process. - * - * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. - */ -static int -mlx5_uar_init_secondary(void) -{ - struct mlx5_shared_data *sd = mlx5_shared_data; - struct mlx5_local_data *ld = &mlx5_local_data; - void *addr; - - if (ld->uar_base) { /* Already reserved. */ - assert(sd->uar_base == ld->uar_base); - return 0; - } - assert(sd->uar_base); - /* anonymous mmap, no real memory consumption. */ - addr = mmap(sd->uar_base, MLX5_UAR_SIZE, - PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - if (addr == MAP_FAILED) { - DRV_LOG(ERR, "UAR mmap failed: %p size: %llu", - sd->uar_base, MLX5_UAR_SIZE); - rte_errno = ENXIO; - return -rte_errno; - } - if (sd->uar_base != addr) { - DRV_LOG(ERR, - "UAR address %p size %llu occupied, please" - " adjust MLX5_UAR_OFFSET or try EAL parameter" - " --base-virtaddr", - sd->uar_base, MLX5_UAR_SIZE); - rte_errno = ENXIO; - return -rte_errno; - } - ld->uar_base = addr; - DRV_LOG(INFO, "Reserved UAR address space: %p", addr); - return 0; -} - -/** - * Unmap UAR address space reserved for secondary process. - */ -static void -mlx5_uar_uninit_secondary(void) -{ - struct mlx5_local_data *ld = &mlx5_local_data; - - if (!ld->uar_base) - return; - munmap(ld->uar_base, MLX5_UAR_SIZE); - ld->uar_base = NULL; -} - /** * PMD global initialization. * @@ -945,7 +1239,7 @@ mlx5_init_once(void) { struct mlx5_shared_data *sd; struct mlx5_local_data *ld = &mlx5_local_data; - int ret; + int ret = 0; if (mlx5_init_shared_data()) return -rte_errno; @@ -960,44 +1254,266 @@ mlx5_init_once(void) rte_rwlock_init(&sd->mem_event_rwlock); rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", mlx5_mr_mem_event_cb, NULL); - mlx5_mp_init_primary(); - ret = mlx5_uar_init_primary(); + ret = mlx5_mp_init_primary(); if (ret) - goto error; + goto out; sd->init_done = true; break; case RTE_PROC_SECONDARY: if (ld->init_done) break; - mlx5_mp_init_secondary(); - ret = mlx5_uar_init_secondary(); + ret = mlx5_mp_init_secondary(); if (ret) - goto error; + goto out; ++sd->secondary_cnt; ld->init_done = true; break; default: break; } +out: rte_spinlock_unlock(&sd->lock); - return 0; -error: - switch (rte_eal_process_type()) { - case RTE_PROC_PRIMARY: - mlx5_uar_uninit_primary(); - mlx5_mp_uninit_primary(); - rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", NULL); + return ret; +} + +/** + * Configures the minimal amount of data to inline into WQE + * while sending packets. + * + * - the txq_inline_min has the maximal priority, if this + * key is specified in devargs + * - if DevX is enabled the inline mode is queried from the + * device (HCA attributes and NIC vport context if needed). + * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX + * and none (0 bytes) for other NICs + * + * @param spawn + * Verbs device parameters (name, port, switch_info) to spawn. + * @param config + * Device configuration parameters. + */ +static void +mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, + struct mlx5_dev_config *config) +{ + if (config->txq_inline_min != MLX5_ARG_UNSET) { + /* Application defines size of inlined data explicitly. */ + switch (spawn->pci_dev->id.device_id) { + case PCI_DEVICE_ID_MELLANOX_CONNECTX4: + case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: + if (config->txq_inline_min < + (int)MLX5_INLINE_HSIZE_L2) { + DRV_LOG(DEBUG, + "txq_inline_mix aligned to minimal" + " ConnectX-4 required value %d", + (int)MLX5_INLINE_HSIZE_L2); + config->txq_inline_min = MLX5_INLINE_HSIZE_L2; + } + break; + } + goto exit; + } + if (config->hca_attr.eth_net_offloads) { + /* We have DevX enabled, inline mode queried successfully. */ + switch (config->hca_attr.wqe_inline_mode) { + case MLX5_CAP_INLINE_MODE_L2: + /* outer L2 header must be inlined. */ + config->txq_inline_min = MLX5_INLINE_HSIZE_L2; + goto exit; + case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: + /* No inline data are required by NIC. */ + config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; + config->hw_vlan_insert = + config->hca_attr.wqe_vlan_insert; + DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); + goto exit; + case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: + /* inline mode is defined by NIC vport context. */ + if (!config->hca_attr.eth_virt) + break; + switch (config->hca_attr.vport_inline_mode) { + case MLX5_INLINE_MODE_NONE: + config->txq_inline_min = + MLX5_INLINE_HSIZE_NONE; + goto exit; + case MLX5_INLINE_MODE_L2: + config->txq_inline_min = + MLX5_INLINE_HSIZE_L2; + goto exit; + case MLX5_INLINE_MODE_IP: + config->txq_inline_min = + MLX5_INLINE_HSIZE_L3; + goto exit; + case MLX5_INLINE_MODE_TCP_UDP: + config->txq_inline_min = + MLX5_INLINE_HSIZE_L4; + goto exit; + case MLX5_INLINE_MODE_INNER_L2: + config->txq_inline_min = + MLX5_INLINE_HSIZE_INNER_L2; + goto exit; + case MLX5_INLINE_MODE_INNER_IP: + config->txq_inline_min = + MLX5_INLINE_HSIZE_INNER_L3; + goto exit; + case MLX5_INLINE_MODE_INNER_TCP_UDP: + config->txq_inline_min = + MLX5_INLINE_HSIZE_INNER_L4; + goto exit; + } + } + } + /* + * We get here if we are unable to deduce + * inline data size with DevX. Try PCI ID + * to determine old NICs. + */ + switch (spawn->pci_dev->id.device_id) { + case PCI_DEVICE_ID_MELLANOX_CONNECTX4: + case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: + case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: + config->txq_inline_min = MLX5_INLINE_HSIZE_L2; + config->hw_vlan_insert = 0; break; - case RTE_PROC_SECONDARY: - mlx5_uar_uninit_secondary(); - mlx5_mp_uninit_secondary(); + case PCI_DEVICE_ID_MELLANOX_CONNECTX5: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: + /* + * These NICs support VLAN insertion from WQE and + * report the wqe_vlan_insert flag. But there is the bug + * and PFC control may be broken, so disable feature. + */ + config->hw_vlan_insert = 0; + config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; break; default: + config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; break; } - rte_spinlock_unlock(&sd->lock); - mlx5_uninit_shared_data(); - return -rte_errno; +exit: + DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); +} + +/** + * Allocate page of door-bells and register it using DevX API. + * + * @param [in] dev + * Pointer to Ethernet device. + * + * @return + * Pointer to new page on success, NULL otherwise. + */ +static struct mlx5_devx_dbr_page * +mlx5_alloc_dbr_page(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_devx_dbr_page *page; + + /* Allocate space for door-bell page and management data. */ + page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page), + RTE_CACHE_LINE_SIZE, dev->device->numa_node); + if (!page) { + DRV_LOG(ERR, "port %u cannot allocate dbr page", + dev->data->port_id); + return NULL; + } + /* Register allocated memory. */ + page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs, + MLX5_DBR_PAGE_SIZE, 0); + if (!page->umem) { + DRV_LOG(ERR, "port %u cannot umem reg dbr page", + dev->data->port_id); + rte_free(page); + return NULL; + } + return page; +} + +/** + * Find the next available door-bell, allocate new page if needed. + * + * @param [in] dev + * Pointer to Ethernet device. + * @param [out] dbr_page + * Door-bell page containing the page data. + * + * @return + * Door-bell address offset on success, a negative error value otherwise. + */ +int64_t +mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_devx_dbr_page *page = NULL; + uint32_t i, j; + + LIST_FOREACH(page, &priv->dbrpgs, next) + if (page->dbr_count < MLX5_DBR_PER_PAGE) + break; + if (!page) { /* No page with free door-bell exists. */ + page = mlx5_alloc_dbr_page(dev); + if (!page) /* Failed to allocate new page. */ + return (-1); + LIST_INSERT_HEAD(&priv->dbrpgs, page, next); + } + /* Loop to find bitmap part with clear bit. */ + for (i = 0; + i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; + i++) + ; /* Empty. */ + /* Find the first clear bit. */ + j = rte_bsf64(~page->dbr_bitmap[i]); + assert(i < (MLX5_DBR_PER_PAGE / 64)); + page->dbr_bitmap[i] |= (1 << j); + page->dbr_count++; + *dbr_page = page; + return (((i * 64) + j) * sizeof(uint64_t)); +} + +/** + * Release a door-bell record. + * + * @param [in] dev + * Pointer to Ethernet device. + * @param [in] umem_id + * UMEM ID of page containing the door-bell record to release. + * @param [in] offset + * Offset of door-bell record in page. + * + * @return + * 0 on success, a negative error value otherwise. + */ +int32_t +mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_devx_dbr_page *page = NULL; + int ret = 0; + + LIST_FOREACH(page, &priv->dbrpgs, next) + /* Find the page this address belongs to. */ + if (page->umem->umem_id == umem_id) + break; + if (!page) + return -EINVAL; + page->dbr_count--; + if (!page->dbr_count) { + /* Page not used, free it and remove from list. */ + LIST_REMOVE(page, next); + if (page->umem) + ret = -mlx5_glue->devx_umem_dereg(page->umem); + rte_free(page); + } else { + /* Mark in bitmap that this door-bell is not in use. */ + offset /= MLX5_DBR_SIZE; + int i = offset / 64; + int j = offset % 64; + + page->dbr_bitmap[i] &= ~(1 << j); + } + return ret; } /** @@ -1041,7 +1557,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, unsigned int mprq_max_stride_size_n = 0; unsigned int mprq_min_stride_num_n = 0; unsigned int mprq_max_stride_num_n = 0; - struct ether_addr mac; + struct rte_ether_addr mac; char name[RTE_ETH_NAME_MAX_LEN]; int own_domain_id = 0; uint16_t port_id; @@ -1088,12 +1604,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } eth_dev->device = dpdk_dev; eth_dev->dev_ops = &mlx5_dev_sec_ops; + err = mlx5_proc_priv_init(eth_dev); + if (err) + return NULL; /* Receive command fd from primary process */ err = mlx5_mp_req_verbs_cmd_fd(eth_dev); if (err < 0) return NULL; /* Remap UAR for Tx queues. */ - err = mlx5_tx_uar_remap(eth_dev, err); + err = mlx5_tx_uar_init_secondary(eth_dev, err); if (err) return NULL; /* @@ -1109,6 +1628,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, if (!sh) return NULL; config.devx = sh->devx; +#ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR + config.dest_tir = 1; +#endif #ifdef HAVE_IBV_MLX5_MOD_SWP dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; #endif @@ -1233,7 +1755,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } priv->sh = sh; priv->ibv_port = spawn->ibv_port; - priv->mtu = ETHER_MTU; + priv->mtu = RTE_ETHER_MTU; #ifndef RTE_ARCH_64 /* Initialize UAR access locks for 32bit implementations. */ rte_spinlock_init(&priv->uar_lock_cq); @@ -1251,7 +1773,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, * Currently we support single E-Switch per PF configurations * only and vport_id field contains the vport index for * associated VF, which is deduced from representor port name. - * For exapmple, let's have the IB device port 10, it has + * For example, let's have the IB device port 10, it has * attached network device eth0, which has port name attribute * pf0vf2, we can deduce the VF number as 2, and set vport index * as 3 (2+1). This assigning schema should be changed if the @@ -1267,22 +1789,16 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, * Look for sibling devices in order to reuse their switch domain * if any, otherwise allocate one. */ - i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); - if (i > 0) { - uint16_t port_id[i]; - - i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); - while (i--) { - const struct mlx5_priv *opriv = - rte_eth_devices[port_id[i]].data->dev_private; + RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) { + const struct mlx5_priv *opriv = + rte_eth_devices[port_id].data->dev_private; - if (!opriv || - opriv->domain_id == - RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) - continue; - priv->domain_id = opriv->domain_id; - break; - } + if (!opriv || + opriv->domain_id == + RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) + continue; + priv->domain_id = opriv->domain_id; + break; } if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { err = rte_eth_switch_domain_alloc(&priv->domain_id); @@ -1372,6 +1888,36 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } else if (config.cqe_pad) { DRV_LOG(INFO, "Rx CQE padding is enabled"); } + if (config.devx) { + priv->counter_fallback = 0; + err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); + if (err) { + err = -err; + goto error; + } + if (!config.hca_attr.flow_counters_dump) + priv->counter_fallback = 1; +#ifndef HAVE_IBV_DEVX_ASYNC + priv->counter_fallback = 1; +#endif + if (priv->counter_fallback) + DRV_LOG(INFO, "Use fall-back DV counter management\n"); + /* Check for LRO support. */ + if (config.dest_tir && config.hca_attr.lro_cap) { + /* TBD check tunnel lro caps. */ + config.lro.supported = config.hca_attr.lro_cap; + DRV_LOG(DEBUG, "Device supports LRO"); + /* + * If LRO timeout is not configured by application, + * use the minimal supported value. + */ + if (!config.lro.timeout) + config.lro.timeout = + config.hca_attr.lro_timer_supported_periods[0]; + DRV_LOG(DEBUG, "LRO session timeout set to %d usec", + config.lro.timeout); + } + } if (config.mprq.enabled && mprq) { if (config.mprq.stride_num_n > mprq_max_stride_num_n || config.mprq.stride_num_n < mprq_min_stride_num_n) { @@ -1390,6 +1936,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); config.mprq.enabled = 0; } + if (config.max_dump_files_num == 0) + config.max_dump_files_num = 128; eth_dev = rte_eth_dev_allocate(name); if (eth_dev == NULL) { DRV_LOG(ERR, "can not allocate rte ethdev"); @@ -1402,6 +1950,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; eth_dev->data->representor_id = priv->representor_id; } + /* + * Store associated network device interface index. This index + * is permanent throughout the lifetime of device. So, we may store + * the ifindex here and use the cached value further. + */ + assert(spawn->ifindex); + priv->if_index = spawn->ifindex; eth_dev->data->dev_private = priv; priv->dev_data = eth_dev->data; eth_dev->data->mac_addrs = priv->mac; @@ -1449,34 +2004,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); if (config.vf && config.vf_nl_en) mlx5_nl_mac_addr_sync(eth_dev); - priv->tcf_context = mlx5_flow_tcf_context_create(); - if (!priv->tcf_context) { - err = -rte_errno; - DRV_LOG(WARNING, - "flow rules relying on switch offloads will not be" - " supported: cannot open libmnl socket: %s", - strerror(rte_errno)); - } else { - struct rte_flow_error error; - unsigned int ifindex = mlx5_ifindex(eth_dev); - - if (!ifindex) { - err = -rte_errno; - error.message = - "cannot retrieve network interface index"; - } else { - err = mlx5_flow_tcf_init(priv->tcf_context, - ifindex, &error); - } - if (err) { - DRV_LOG(WARNING, - "flow rules relying on switch offloads will" - " not be supported: %s: %s", - error.message, strerror(rte_errno)); - mlx5_flow_tcf_context_destroy(priv->tcf_context); - priv->tcf_context = NULL; - } - } TAILQ_INIT(&priv->flows); TAILQ_INIT(&priv->ctrl_flows); /* Hint libmlx5 to use PMD allocator for data plane resources */ @@ -1494,12 +2021,28 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mlx5_set_link_up(eth_dev); /* * Even though the interrupt handler is not installed yet, - * interrupts will still trigger on the asyn_fd from + * interrupts will still trigger on the async_fd from * Verbs context returned by ibv_open_device(). */ mlx5_link_update(eth_dev, 0); +#ifdef HAVE_MLX5DV_DR_ESWITCH + if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && + (switch_info->representor || switch_info->master))) + config.dv_esw_en = 0; +#else + config.dv_esw_en = 0; +#endif + /* Detect minimal data bytes to inline. */ + mlx5_set_min_inline(spawn, &config); /* Store device configuration on private structure. */ priv->config = config; + /* Create context for virtual machine VLAN workaround. */ + priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); + if (config.dv_flow_en) { + err = mlx5_alloc_shared_dr(priv); + if (err) + goto error; + } /* Supported Verbs flow priority number detection. */ err = mlx5_flow_discover_priorities(eth_dev); if (err < 0) { @@ -1507,33 +2050,17 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, goto error; } priv->config.flow_prio = err; - /* - * Once the device is added to the list of memory event - * callback, its global MR cache table cannot be expanded - * on the fly because of deadlock. If it overflows, lookup - * should be done by searching MR list linearly, which is slow. - */ - err = mlx5_mr_btree_init(&priv->mr.cache, - MLX5_MR_BTREE_CACHE_N * 2, - eth_dev->device->numa_node); - if (err) { - err = rte_errno; - goto error; - } - /* Add device to memory callback list. */ - rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); - LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, - priv, mem_event_cb); - rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); return eth_dev; error: if (priv) { + if (priv->sh) + mlx5_free_shared_dr(priv); if (priv->nl_socket_route >= 0) close(priv->nl_socket_route); if (priv->nl_socket_rdma >= 0) close(priv->nl_socket_rdma); - if (priv->tcf_context) - mlx5_flow_tcf_context_destroy(priv->tcf_context); + if (priv->vmwa_context) + mlx5_vlan_vmwa_exit(priv->vmwa_context); if (own_domain_id) claim_zero(rte_eth_switch_domain_free(priv->domain_id)); rte_free(priv); @@ -1669,7 +2196,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, } ibv_match[nd] = NULL; if (!nd) { - /* No device macthes, just complain and bail out. */ + /* No device matches, just complain and bail out. */ mlx5_glue->free_device_list(ibv_list); DRV_LOG(WARNING, "no Verbs device matches PCI device " PCI_PRI_FMT "," @@ -1702,7 +2229,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, if (np > 1) { /* - * Signle IB device with multiple ports found, + * Single IB device with multiple ports found, * it may be E-Switch master device and representors. * We have to perform identification trough the ports. */ @@ -1714,6 +2241,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, list[ns].ibv_port = i; list[ns].ibv_dev = ibv_match[0]; list[ns].eth_dev = NULL; + list[ns].pci_dev = pci_dev; list[ns].ifindex = mlx5_nl_ifindex (nl_rdma, list[ns].ibv_dev->name, i); if (!list[ns].ifindex) { @@ -1780,17 +2308,46 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, list[ns].ibv_port = 1; list[ns].ibv_dev = ibv_match[i]; list[ns].eth_dev = NULL; + list[ns].pci_dev = pci_dev; list[ns].ifindex = 0; if (nl_rdma >= 0) list[ns].ifindex = mlx5_nl_ifindex (nl_rdma, list[ns].ibv_dev->name, 1); if (!list[ns].ifindex) { + char ifname[IF_NAMESIZE]; + /* - * No network interface index found for the - * specified device, it means there it is not - * a representor/master. + * Netlink failed, it may happen with old + * ib_core kernel driver (before 4.16). + * We can assume there is old driver because + * here we are processing single ports IB + * devices. Let's try sysfs to retrieve + * the ifindex. The method works for + * master device only. */ - continue; + if (nd > 1) { + /* + * Multiple devices found, assume + * representors, can not distinguish + * master/representor and retrieve + * ifindex via sysfs. + */ + continue; + } + ret = mlx5_get_master_ifname + (ibv_match[i]->ibdev_path, &ifname); + if (!ret) + list[ns].ifindex = + if_nametoindex(ifname); + if (!list[ns].ifindex) { + /* + * No network interface index found + * for the specified device, it means + * there it is neither representor + * nor master. + */ + continue; + } } ret = -1; if (nl_route >= 0) @@ -1846,25 +2403,23 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev_config = (struct mlx5_dev_config){ .hw_padding = 0, .mps = MLX5_ARG_UNSET, - .tx_vec_en = 1, .rx_vec_en = 1, - .txq_inline = MLX5_ARG_UNSET, + .txq_inline_max = MLX5_ARG_UNSET, + .txq_inline_min = MLX5_ARG_UNSET, + .txq_inline_mpw = MLX5_ARG_UNSET, .txqs_inline = MLX5_ARG_UNSET, - .txqs_vec = MLX5_ARG_UNSET, - .inline_max_packet_sz = MLX5_ARG_UNSET, .vf_nl_en = 1, + .mr_ext_memseg_en = 1, .mprq = { .enabled = 0, /* Disabled by default. */ .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, }, + .dv_esw_en = 1, }; /* Device specific configuration. */ switch (pci_dev->id.device_id) { - case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: - dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD; - break; case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: @@ -1874,9 +2429,6 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, default: break; } - /* Set architecture-dependent default value if unset. */ - if (dev_config.txqs_vec == MLX5_ARG_UNSET) - dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS; for (i = 0; i != ns; ++i) { uint32_t restore; @@ -1947,14 +2499,9 @@ static int mlx5_pci_remove(struct rte_pci_device *pci_dev) { uint16_t port_id; - struct rte_eth_dev *port; - for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { - port = &rte_eth_devices[port_id]; - if (port->state != RTE_ETH_DEV_UNUSED && - port->device == &pci_dev->device) - rte_eth_dev_close(port_id); - } + RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) + rte_eth_dev_close(port_id); return 0; } @@ -2021,8 +2568,8 @@ static struct rte_pci_driver mlx5_driver = { .remove = mlx5_pci_remove, .dma_map = mlx5_dma_map, .dma_unmap = mlx5_dma_unmap, - .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | - RTE_PCI_DRV_PROBE_AGAIN), + .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | + RTE_PCI_DRV_PROBE_AGAIN, }; #ifdef RTE_IBVERBS_LINK_DLOPEN