X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.c;h=72b1e356737a1eb33142a176a510fbb9f3e07c6e;hb=72d836b300b9e92201a924c4b540a68ae0570388;hp=f827318fd0049e0432b914648f867b01fff308dd;hpb=ea823b2c511d6e4a4e51fa5e4aabc30e5a30cdb7;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index f827318fd0..72b1e35673 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -42,9 +43,6 @@ #define MLX5_ETH_DRIVER_NAME mlx5_eth -/* Driver type key for new device global syntax. */ -#define MLX5_DRIVER_KEY "driver" - /* Device parameter to enable RX completion queue compression. */ #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" @@ -93,12 +91,6 @@ /* Device parameter to enable multi-packet send WQEs. */ #define MLX5_TXQ_MPW_EN "txq_mpw_en" -/* - * Device parameter to force doorbell register mapping - * to non-cahed region eliminating the extra write memory barrier. - */ -#define MLX5_TX_DB_NC "tx_db_nc" - /* * Device parameter to include 2 dsegs in the title WQEBB. * Deprecated, ignored. @@ -151,9 +143,6 @@ /* Activate Netlink support in VF mode. */ #define MLX5_VF_NL_EN "vf_nl_en" -/* Enable extending memsegs when creating a MR. */ -#define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" - /* Select port representors to instantiate. */ #define MLX5_REPRESENTOR "representor" @@ -172,16 +161,14 @@ /* Flow memory reclaim mode. */ #define MLX5_RECLAIM_MEM "reclaim_mem_mode" -/* The default memory allocator used in PMD. */ -#define MLX5_SYS_MEM_EN "sys_mem_en" /* Decap will be used or not. */ #define MLX5_DECAP_EN "decap_en" /* Device parameter to configure allow or prevent duplicate rules pattern. */ #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" -/* Device parameter to configure implicit registration of mempool memory. */ -#define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en" +/* Device parameter to configure the delay drop when creating Rxqs. */ +#define MLX5_DELAY_DROP "delay_drop" /* Shared memory between primary and secondary processes. */ struct mlx5_shared_data *mlx5_shared_data; @@ -378,7 +365,6 @@ static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { }, }; - #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 @@ -450,7 +436,7 @@ mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) mlx5_free(sh->aso_age_mng); return -1; } - rte_spinlock_init(&sh->aso_age_mng->resize_sl); + rte_rwlock_init(&sh->aso_age_mng->resize_rwl); rte_spinlock_init(&sh->aso_age_mng->free_sl); LIST_INIT(&sh->aso_age_mng->free); return 0; @@ -510,6 +496,46 @@ mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) } } +/** + * DV flow counter mode detect and config. + * + * @param dev + * Pointer to rte_eth_dev structure. + * + */ +void +mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; + bool fallback; + +#ifndef HAVE_IBV_DEVX_ASYNC + fallback = true; +#else + fallback = false; + if (!sh->cdev->config.devx || !sh->config.dv_flow_en || + !hca_attr->flow_counters_dump || + !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || + (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) + fallback = true; +#endif + if (fallback) + DRV_LOG(INFO, "Use fall-back DV counter management. Flow " + "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", + hca_attr->flow_counters_dump, + hca_attr->flow_counter_bulk_alloc_bitmap); + /* Initialize fallback mode only on the port initializes sh. */ + if (sh->refcnt == 1) + sh->cmng.counter_fallback = fallback; + else if (fallback != sh->cmng.counter_fallback) + DRV_LOG(WARNING, "Port %d in sh has different fallback mode " + "with others:%d.", PORT_ID(priv), fallback); +#endif +} + /** * Initialize the counters management structure. * @@ -519,7 +545,6 @@ mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) static void mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) { - struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; int i; memset(&sh->cmng, 0, sizeof(sh->cmng)); @@ -532,10 +557,6 @@ mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) TAILQ_INIT(&sh->cmng.counters[i]); rte_spinlock_init(&sh->cmng.csl[i]); } - if (sh->devx && !haswell_broadwell_cpu) { - sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write; - sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read; - } } /** @@ -550,8 +571,7 @@ mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; LIST_REMOVE(mng, next); - claim_zero(mlx5_devx_cmd_destroy(mng->dm)); - claim_zero(mlx5_os_umem_dereg(mng->umem)); + mlx5_os_wrapped_mkey_destroy(&mng->wm); mlx5_free(mem); } @@ -632,6 +652,7 @@ mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) } if (sh->meter_aso_en) { rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); + rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); LIST_INIT(&sh->mtrmng->pools_mng.meters); } sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; @@ -798,12 +819,9 @@ mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) * * @param[in] sh * Pointer to mlx5_dev_ctx_shared object. - * @param[in] config - * Pointer to user dev config. */ static void -mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh, - const struct mlx5_dev_config *config) +mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) { uint8_t i; struct mlx5_indexed_pool_config cfg; @@ -818,12 +836,12 @@ mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh, * according to PCI function flow configuration. */ case MLX5_IPOOL_MLX5_FLOW: - cfg.size = config->dv_flow_en ? + cfg.size = sh->config.dv_flow_en ? sizeof(struct mlx5_flow_handle) : MLX5_FLOW_HANDLE_VERBS_SIZE; break; } - if (config->reclaim_mode) { + if (sh->config.reclaim_mode) { cfg.release_mem_en = 1; cfg.per_core_cache = 0; } else { @@ -865,8 +883,7 @@ bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_flex_parser_profiles *prf = - &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0]; + struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; return !!prf->obj; } @@ -885,15 +902,14 @@ int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_flex_parser_profiles *prf = - &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0]; + struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; uint32_t ids[8]; int ret; - if (!priv->config.hca_attr.parse_graph_flex_node) { + if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { DRV_LOG(ERR, "Dynamic flex parser is not supported " "for device %s.", priv->dev_data->name); return -ENOTSUP; @@ -949,8 +965,7 @@ static void mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_flex_parser_profiles *prf = - &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0]; + struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; if (prf->obj) mlx5_devx_cmd_destroy(prf->obj); @@ -987,143 +1002,35 @@ mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) return tn_offloads; } -/* - * Allocate Rx and Tx UARs in robust fashion. - * This routine handles the following UAR allocation issues: - * - * - tries to allocate the UAR with the most appropriate memory - * mapping type from the ones supported by the host - * - * - tries to allocate the UAR with non-NULL base address - * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as - * UAR base address if UAR was not the first object in the UAR page. - * It caused the PMD failure and we should try to get another UAR - * till we get the first one with non-NULL base address returned. - */ +/* Fill all fields of UAR structure. */ static int -mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, - const struct mlx5_common_dev_config *config) +mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) { - uint32_t uar_mapping, retry; - int err = 0; - void *base_addr; - - for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) { -#ifdef MLX5DV_UAR_ALLOC_TYPE_NC - /* Control the mapping type according to the settings. */ - uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ? - MLX5DV_UAR_ALLOC_TYPE_NC : - MLX5DV_UAR_ALLOC_TYPE_BF; -#else - RTE_SET_USED(config); - /* - * It seems we have no way to control the memory mapping type - * for the UAR, the default "Write-Combining" type is supposed. - * The UAR initialization on queue creation queries the - * actual mapping type done by Verbs/kernel and setups the - * PMD datapath accordingly. - */ - uar_mapping = 0; -#endif - sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx, - uar_mapping); -#ifdef MLX5DV_UAR_ALLOC_TYPE_NC - if (!sh->tx_uar && - uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) { - if (config->dbnc == MLX5_TXDB_CACHED || - config->dbnc == MLX5_TXDB_HEURISTIC) - DRV_LOG(WARNING, "Devarg tx_db_nc setting " - "is not supported by DevX"); - /* - * In some environments like virtual machine - * the Write Combining mapped might be not supported - * and UAR allocation fails. We try "Non-Cached" - * mapping for the case. The tx_burst routines take - * the UAR mapping type into account on UAR setup - * on queue creation. - */ - DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)"); - uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; - sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx, - uar_mapping); - } else if (!sh->tx_uar && - uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) { - if (config->dbnc == MLX5_TXDB_NCACHED) - DRV_LOG(WARNING, "Devarg tx_db_nc settings " - "is not supported by DevX"); - /* - * If Verbs/kernel does not support "Non-Cached" - * try the "Write-Combining". - */ - DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)"); - uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF; - sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx, - uar_mapping); - } -#endif - if (!sh->tx_uar) { - DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)"); - err = ENOMEM; - goto exit; - } - base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar); - if (base_addr) - break; - /* - * The UARs are allocated by rdma_core within the - * IB device context, on context closure all UARs - * will be freed, should be no memory/object leakage. - */ - DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR"); - sh->tx_uar = NULL; - } - /* Check whether we finally succeeded with valid UAR allocation. */ - if (!sh->tx_uar) { - DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)"); - err = ENOMEM; - goto exit; - } - for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) { - uar_mapping = 0; - sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx, - uar_mapping); -#ifdef MLX5DV_UAR_ALLOC_TYPE_NC - if (!sh->devx_rx_uar && - uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) { - /* - * Rx UAR is used to control interrupts only, - * should be no datapath noticeable impact, - * can try "Non-Cached" mapping safely. - */ - DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)"); - uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; - sh->devx_rx_uar = mlx5_glue->devx_alloc_uar - (sh->cdev->ctx, uar_mapping); - } -#endif - if (!sh->devx_rx_uar) { - DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)"); - err = ENOMEM; - goto exit; - } - base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar); - if (base_addr) - break; - /* - * The UARs are allocated by rdma_core within the - * IB device context, on context closure all UARs - * will be freed, should be no memory/object leakage. - */ - DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR"); - sh->devx_rx_uar = NULL; + int ret; + + ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); + if (ret) { + DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); + return -rte_errno; } - /* Check whether we finally succeeded with valid UAR allocation. */ - if (!sh->devx_rx_uar) { - DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)"); - err = ENOMEM; + MLX5_ASSERT(sh->tx_uar.obj); + MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); + ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); + if (ret) { + DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); + mlx5_devx_uar_release(&sh->tx_uar); + return -rte_errno; } -exit: - return err; + MLX5_ASSERT(sh->rx_uar.obj); + MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); + return 0; +} + +static void +mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) +{ + mlx5_devx_uar_release(&sh->rx_uar); + mlx5_devx_uar_release(&sh->tx_uar); } /** @@ -1180,6 +1087,301 @@ mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) return mlx5_dev_mempool_subscribe(sh->cdev); } +/** + * Set up multiple TISs with different affinities according to + * number of bonding ports + * + * @param priv + * Pointer of shared context. + * + * @return + * Zero on success, -1 otherwise. + */ +static int +mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) +{ + int i; + struct mlx5_devx_lag_context lag_ctx = { 0 }; + struct mlx5_devx_tis_attr tis_attr = { 0 }; + + tis_attr.transport_domain = sh->td->id; + if (sh->bond.n_port) { + if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { + sh->lag.tx_remap_affinity[0] = + lag_ctx.tx_remap_affinity_1; + sh->lag.tx_remap_affinity[1] = + lag_ctx.tx_remap_affinity_2; + sh->lag.affinity_mode = lag_ctx.port_select_mode; + } else { + DRV_LOG(ERR, "Failed to query lag affinity."); + return -1; + } + if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) { + for (i = 0; i < sh->bond.n_port; i++) { + tis_attr.lag_tx_port_affinity = + MLX5_IFC_LAG_MAP_TIS_AFFINITY(i, + sh->bond.n_port); + sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, + &tis_attr); + if (!sh->tis[i]) { + DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device" + " %s.", i, sh->bond.n_port, + sh->ibdev_name); + return -1; + } + } + DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", + sh->bond.n_port, lag_ctx.tx_remap_affinity_1, + lag_ctx.tx_remap_affinity_2); + return 0; + } + if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) + DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", + sh->ibdev_name); + } + tis_attr.lag_tx_port_affinity = 0; + sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); + if (!sh->tis[0]) { + DRV_LOG(ERR, "Failed to TIS 0 for bonding device" + " %s.", sh->ibdev_name); + return -1; + } + return 0; +} + +/** + * Verify and store value for share device argument. + * + * @param[in] key + * Key argument to verify. + * @param[in] val + * Value associated with key. + * @param opaque + * User data. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) +{ + struct mlx5_sh_config *config = opaque; + signed long tmp; + + errno = 0; + tmp = strtol(val, NULL, 0); + if (errno) { + rte_errno = errno; + DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); + return -rte_errno; + } + if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { + /* Negative values are acceptable for some keys only. */ + rte_errno = EINVAL; + DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); + return -rte_errno; + } + if (strcmp(MLX5_TX_PP, key) == 0) { + unsigned long mod = tmp >= 0 ? tmp : -tmp; + + if (!mod) { + DRV_LOG(ERR, "Zero Tx packet pacing parameter."); + rte_errno = EINVAL; + return -rte_errno; + } + config->tx_pp = tmp; + } else if (strcmp(MLX5_TX_SKEW, key) == 0) { + config->tx_skew = tmp; + } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { + config->l3_vxlan_en = !!tmp; + } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { + config->vf_nl_en = !!tmp; + } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { + config->dv_esw_en = !!tmp; + } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { + if (tmp > 2) { + DRV_LOG(ERR, "Invalid %s parameter.", key); + rte_errno = EINVAL; + return -rte_errno; + } + config->dv_flow_en = tmp; + } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { + if (tmp != MLX5_XMETA_MODE_LEGACY && + tmp != MLX5_XMETA_MODE_META16 && + tmp != MLX5_XMETA_MODE_META32 && + tmp != MLX5_XMETA_MODE_MISS_INFO) { + DRV_LOG(ERR, "Invalid extensive metadata parameter."); + rte_errno = EINVAL; + return -rte_errno; + } + if (tmp != MLX5_XMETA_MODE_MISS_INFO) + config->dv_xmeta_en = tmp; + else + config->dv_miss_info = 1; + } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { + config->lacp_by_user = !!tmp; + } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { + if (tmp != MLX5_RCM_NONE && + tmp != MLX5_RCM_LIGHT && + tmp != MLX5_RCM_AGGR) { + DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); + rte_errno = EINVAL; + return -rte_errno; + } + config->reclaim_mode = tmp; + } else if (strcmp(MLX5_DECAP_EN, key) == 0) { + config->decap_en = !!tmp; + } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { + config->allow_duplicate_pattern = !!tmp; + } + return 0; +} + +/** + * Parse user device parameters and adjust them according to device + * capabilities. + * + * @param sh + * Pointer to shared device context. + * @param mkvlist + * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. + * @param config + * Pointer to shared device configuration structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, + struct mlx5_kvargs_ctrl *mkvlist, + struct mlx5_sh_config *config) +{ + const char **params = (const char *[]){ + MLX5_TX_PP, + MLX5_TX_SKEW, + MLX5_L3_VXLAN_EN, + MLX5_VF_NL_EN, + MLX5_DV_ESW_EN, + MLX5_DV_FLOW_EN, + MLX5_DV_XMETA_EN, + MLX5_LACP_BY_USER, + MLX5_RECLAIM_MEM, + MLX5_DECAP_EN, + MLX5_ALLOW_DUPLICATE_PATTERN, + NULL, + }; + int ret = 0; + + /* Default configuration. */ + memset(config, 0, sizeof(*config)); + config->vf_nl_en = 1; + config->dv_esw_en = 1; + config->dv_flow_en = 1; + config->decap_en = 1; + config->allow_duplicate_pattern = 1; + if (mkvlist != NULL) { + /* Process parameters. */ + ret = mlx5_kvargs_process(mkvlist, params, + mlx5_dev_args_check_handler, config); + if (ret) { + DRV_LOG(ERR, "Failed to process device arguments: %s", + strerror(rte_errno)); + return -rte_errno; + } + } + /* Adjust parameters according to device capabilities. */ + if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { + DRV_LOG(WARNING, "DV flow is not supported."); + config->dv_flow_en = 0; + } + if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { + DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); + config->dv_esw_en = 0; + } + if (config->dv_esw_en && !config->dv_flow_en) { + DRV_LOG(DEBUG, + "E-Switch DV flow is supported only when DV flow is enabled."); + config->dv_esw_en = 0; + } + if (config->dv_miss_info && config->dv_esw_en) + config->dv_xmeta_en = MLX5_XMETA_MODE_META16; + if (!config->dv_esw_en && + config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { + DRV_LOG(WARNING, + "Metadata mode %u is not supported (no E-Switch).", + config->dv_xmeta_en); + config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; + } + if (config->tx_pp && !sh->dev_cap.txpp_en) { + DRV_LOG(ERR, "Packet pacing is not supported."); + rte_errno = ENODEV; + return -rte_errno; + } + if (!config->tx_pp && config->tx_skew) { + DRV_LOG(WARNING, + "\"tx_skew\" doesn't affect without \"tx_pp\"."); + } + /* + * If HW has bug working with tunnel packet decapsulation and scatter + * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. + * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. + */ + if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) + config->hw_fcs_strip = 0; + else + config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; + DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", + (config->hw_fcs_strip ? "" : "not ")); + DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); + DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); + DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); + DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); + DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); + DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); + DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); + DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); + DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); + DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); + DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); + DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", + config->allow_duplicate_pattern); + return 0; +} + +/** + * Configure realtime timestamp format. + * + * @param sh + * Pointer to mlx5_dev_ctx_shared object. + * @param hca_attr + * Pointer to DevX HCA capabilities structure. + */ +void +mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, + struct mlx5_hca_attr *hca_attr) +{ + uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); + uint32_t reg[dw_cnt]; + int ret = ENOTSUP; + + if (hca_attr->access_register_user) + ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, + MLX5_REGISTER_ID_MTUTC, 0, + reg, dw_cnt); + if (!ret) { + uint32_t ts_mode; + + /* MTUTC register is read successfully. */ + ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); + if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) + sh->dev_cap.rt_timestamp = 1; + } else { + /* Kernel does not support register reading. */ + if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) + sh->dev_cap.rt_timestamp = 1; + } +} + /** * Allocate shared device context. If there is multiport device the * master and representors will share this context, if there is single @@ -1193,8 +1395,8 @@ mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) * * @param[in] spawn * Pointer to the device attributes (name, port, etc). - * @param[in] config - * Pointer to device configuration structure. + * @param mkvlist + * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. * * @return * Pointer to mlx5_dev_ctx_shared object on success, @@ -1202,12 +1404,11 @@ mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) */ struct mlx5_dev_ctx_shared * mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, - const struct mlx5_dev_config *config) + struct mlx5_kvargs_ctrl *mkvlist) { struct mlx5_dev_ctx_shared *sh; int err = 0; uint32_t i; - struct mlx5_devx_tis_attr tis_attr = { 0 }; MLX5_ASSERT(spawn); /* Secondary process should not create the shared context. */ @@ -1224,70 +1425,68 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, MLX5_ASSERT(spawn->max_port); sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, sizeof(struct mlx5_dev_ctx_shared) + - spawn->max_port * - sizeof(struct mlx5_dev_shared_port), + spawn->max_port * sizeof(struct mlx5_dev_shared_port), RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); if (!sh) { - DRV_LOG(ERR, "shared context allocation failure"); - rte_errno = ENOMEM; + DRV_LOG(ERR, "Shared context allocation failure."); + rte_errno = ENOMEM; goto exit; } pthread_mutex_init(&sh->txpp.mutex, NULL); sh->numa_node = spawn->cdev->dev->numa_node; sh->cdev = spawn->cdev; - sh->devx = sh->cdev->config.devx; + sh->esw_mode = !!(spawn->info.master || spawn->info.representor); if (spawn->bond_info) sh->bond = *spawn->bond_info; - err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr); + err = mlx5_os_capabilities_prepare(sh); + if (err) { + DRV_LOG(ERR, "Fail to configure device capabilities."); + goto error; + } + err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); if (err) { - DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed"); + DRV_LOG(ERR, "Failed to process device configure: %s", + strerror(rte_errno)); goto error; } sh->refcnt = 1; sh->max_port = spawn->max_port; - sh->reclaim_mode = config->reclaim_mode; strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), sizeof(sh->ibdev_name) - 1); strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), sizeof(sh->ibdev_path) - 1); /* - * Setting port_id to max unallowed value means - * there is no interrupt subhandler installed for - * the given port index i. + * Setting port_id to max unallowed value means there is no interrupt + * subhandler installed for the given port index i. */ for (i = 0; i < sh->max_port; i++) { sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; + sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; } - if (sh->devx) { + if (sh->cdev->config.devx) { sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); if (!sh->td) { DRV_LOG(ERR, "TD allocation failure"); - err = ENOMEM; + rte_errno = ENOMEM; goto error; } - tis_attr.transport_domain = sh->td->id; - sh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); - if (!sh->tis) { + if (mlx5_setup_tis(sh)) { DRV_LOG(ERR, "TIS allocation failure"); - err = ENOMEM; + rte_errno = ENOMEM; goto error; } - err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config); + err = mlx5_rxtx_uars_prepare(sh); if (err) goto error; - MLX5_ASSERT(sh->tx_uar); - MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar)); - - MLX5_ASSERT(sh->devx_rx_uar); - MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar)); - } #ifndef RTE_ARCH_64 - /* Initialize UAR access locks for 32bit implementations. */ - rte_spinlock_init(&sh->uar_lock_cq); - for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) - rte_spinlock_init(&sh->uar_lock[i]); + } else { + /* Initialize UAR access locks for 32bit implementations. */ + rte_spinlock_init(&sh->uar_lock_cq); + for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) + rte_spinlock_init(&sh->uar_lock[i]); #endif + } mlx5_os_dev_shared_handler_install(sh); if (LIST_EMPTY(&mlx5_dev_ctx_list)) { err = mlx5_flow_os_init_workspace_once(); @@ -1296,7 +1495,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, } mlx5_flow_aging_init(sh); mlx5_flow_counters_mng_init(sh); - mlx5_flow_ipool_create(sh, config); + mlx5_flow_ipool_create(sh); /* Add context to the global device list. */ LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); rte_spinlock_init(&sh->geneve_tlv_opt_sl); @@ -1304,19 +1503,19 @@ exit: pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); return sh; error: + err = rte_errno; pthread_mutex_destroy(&sh->txpp.mutex); pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); MLX5_ASSERT(sh); - if (sh->tis) - claim_zero(mlx5_devx_cmd_destroy(sh->tis)); + mlx5_rxtx_uars_release(sh); + i = 0; + do { + if (sh->tis[i]) + claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); + } while (++i < (uint32_t)sh->bond.n_port); if (sh->td) claim_zero(mlx5_devx_cmd_destroy(sh->td)); - if (sh->devx_rx_uar) - mlx5_glue->devx_free_uar(sh->devx_rx_uar); - if (sh->tx_uar) - mlx5_glue->devx_free_uar(sh->tx_uar); mlx5_free(sh); - MLX5_ASSERT(err > 0); rte_errno = err; return NULL; } @@ -1332,6 +1531,7 @@ void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) { int ret; + int i = 0; pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); #ifdef RTE_LIBRTE_MLX5_DEBUG @@ -1369,11 +1569,17 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) mlx5_flow_os_release_workspace(); } pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); + if (sh->flex_parsers_dv) { + mlx5_list_destroy(sh->flex_parsers_dv); + sh->flex_parsers_dv = NULL; + } /* * Ensure there is no async event handler installed. * Only primary process handles async device events. **/ mlx5_flow_counters_mng_close(sh); + if (sh->ct_mng) + mlx5_flow_aso_ct_mng_close(sh); if (sh->aso_age_mng) { mlx5_flow_aso_age_mng_close(sh); sh->aso_age_mng = NULL; @@ -1382,16 +1588,13 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) mlx5_aso_flow_mtrs_mng_close(sh); mlx5_flow_ipool_destroy(sh); mlx5_os_dev_shared_handler_uninstall(sh); - if (sh->tx_uar) { - mlx5_glue->devx_free_uar(sh->tx_uar); - sh->tx_uar = NULL; - } - if (sh->tis) - claim_zero(mlx5_devx_cmd_destroy(sh->tis)); + mlx5_rxtx_uars_release(sh); + do { + if (sh->tis[i]) + claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); + } while (++i < sh->bond.n_port); if (sh->td) claim_zero(mlx5_devx_cmd_destroy(sh->td)); - if (sh->devx_rx_uar) - mlx5_glue->devx_free_uar(sh->devx_rx_uar); MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); pthread_mutex_destroy(&sh->txpp.mutex); mlx5_free(sh); @@ -1410,13 +1613,47 @@ void mlx5_free_table_hash_list(struct mlx5_priv *priv) { struct mlx5_dev_ctx_shared *sh = priv->sh; - - if (!sh->flow_tbls) + struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? + &sh->groups : &sh->flow_tbls; + if (*tbls == NULL) return; - mlx5_hlist_destroy(sh->flow_tbls); - sh->flow_tbls = NULL; + mlx5_hlist_destroy(*tbls); + *tbls = NULL; } +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) +/** + * Allocate HW steering group hash list. + * + * @param[in] priv + * Pointer to the private device data structure. + */ +static int +mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) +{ + int err = 0; + struct mlx5_dev_ctx_shared *sh = priv->sh; + char s[MLX5_NAME_SIZE]; + + MLX5_ASSERT(sh); + snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); + sh->groups = mlx5_hlist_create + (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, + false, true, sh, + flow_hw_grp_create_cb, + flow_hw_grp_match_cb, + flow_hw_grp_remove_cb, + flow_hw_grp_clone_cb, + flow_hw_grp_clone_free_cb); + if (!sh->groups) { + DRV_LOG(ERR, "flow groups with hash creation failed."); + err = ENOMEM; + } + return err; +} +#endif + + /** * Initialize flow table hash list and create the root tables entry * for each domain. @@ -1431,11 +1668,14 @@ int mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) { int err = 0; + /* Tables are only used in DV and DR modes. */ #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_dev_ctx_shared *sh = priv->sh; char s[MLX5_NAME_SIZE]; + if (priv->sh->config.dv_flow_en == 2) + return mlx5_alloc_hw_group_hash_list(priv); MLX5_ASSERT(sh); snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, @@ -1511,10 +1751,10 @@ mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, struct rte_eth_udp_tunnel *udp_tunnel) { MLX5_ASSERT(udp_tunnel != NULL); - if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN && + if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && udp_tunnel->udp_port == 4789) return 0; - if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE && + if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && udp_tunnel->udp_port == 4790) return 0; return -ENOTSUP; @@ -1541,8 +1781,8 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev) * UAR register table follows the process private structure. BlueFlame * registers for Tx queues are stored in the table. */ - ppriv_size = - sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); + ppriv_size = sizeof(struct mlx5_proc_priv) + + priv->txqs_n * sizeof(struct mlx5_uar_data); ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, RTE_CACHE_LINE_SIZE, dev->device->numa_node); if (!ppriv) { @@ -1551,6 +1791,8 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev) } ppriv->uar_table_sz = priv->txqs_n; dev->process_private = ppriv; + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + priv->sh->pppriv = ppriv; return 0; } @@ -1613,25 +1855,25 @@ mlx5_dev_close(struct rte_eth_dev *dev) mlx5_action_handle_flush(dev); mlx5_flow_meter_flush(dev, NULL); /* Prevent crashes when queues are still in use. */ - dev->rx_pkt_burst = removed_rx_burst; - dev->tx_pkt_burst = removed_tx_burst; + dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; + dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; rte_wmb(); /* Disable datapath on secondary process. */ mlx5_mp_os_req_stop_rxtx(dev); /* Free the eCPRI flex parser resource. */ mlx5_flex_parser_ecpri_release(dev); - if (priv->rxqs != NULL) { + mlx5_flex_item_port_cleanup(dev); +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) + flow_hw_resource_release(dev); +#endif + if (priv->rxq_privs != NULL) { /* XXX race condition if mlx5_rx_burst() is still running. */ rte_delay_us_sleep(1000); for (i = 0; (i != priv->rxqs_n); ++i) mlx5_rxq_release(dev, i); priv->rxqs_n = 0; - priv->rxqs = NULL; - } - if (priv->representor) { - /* Each representor has a dedicated interrupts handler */ - mlx5_free(dev->intr_handle); - dev->intr_handle = NULL; + mlx5_free(priv->rxq_privs); + priv->rxq_privs = NULL; } if (priv->txqs != NULL) { /* XXX race condition if mlx5_tx_burst() is still running. */ @@ -1651,14 +1893,12 @@ mlx5_dev_close(struct rte_eth_dev *dev) if (priv->mreg_cp_tbl) mlx5_hlist_destroy(priv->mreg_cp_tbl); mlx5_mprq_free_mp(dev); - if (priv->sh->ct_mng) - mlx5_flow_aso_ct_mng_close(priv->sh); mlx5_os_free_shared_dr(priv); if (priv->rss_conf.rss_key != NULL) mlx5_free(priv->rss_conf.rss_key); if (priv->reta_idx != NULL) mlx5_free(priv->reta_idx); - if (priv->config.vf) + if (priv->sh->dev_cap.vf) mlx5_os_mac_addr_flush(dev); if (priv->nl_socket_route >= 0) close(priv->nl_socket_route); @@ -1678,6 +1918,10 @@ mlx5_dev_close(struct rte_eth_dev *dev) if (ret) DRV_LOG(WARNING, "port %u some Rx queue objects still remain", dev->data->port_id); + ret = mlx5_ext_rxq_verify(dev); + if (ret) + DRV_LOG(WARNING, "Port %u some external RxQ still remain.", + dev->data->port_id); ret = mlx5_rxq_verify(dev); if (ret) DRV_LOG(WARNING, "port %u some Rx queues still remain", @@ -1696,10 +1940,11 @@ mlx5_dev_close(struct rte_eth_dev *dev) dev->data->port_id); if (priv->hrxqs) mlx5_list_destroy(priv->hrxqs); + mlx5_free(priv->ext_rxqs); /* * Free the shared context in last turn, because the cleanup * routines above may use some shared fields, like - * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing + * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving * ifindex if Netlink fails. */ mlx5_free_shared_dev_ctx(priv->sh); @@ -1901,17 +2146,13 @@ const struct eth_dev_ops mlx5_dev_ops_isolate = { * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_args_check(const char *key, const char *val, void *opaque) +mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) { - struct mlx5_dev_config *config = opaque; - unsigned long mod; + struct mlx5_port_config *config = opaque; signed long tmp; /* No-op, port representors are processed in mlx5_dev_spawn(). */ - if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) || - !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) || - !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) || - !strcmp(MLX5_MR_EXT_MEMSEG_EN, key)) + if (!strcmp(MLX5_REPRESENTOR, key)) return 0; errno = 0; tmp = strtol(val, NULL, 0); @@ -1920,13 +2161,12 @@ mlx5_args_check(const char *key, const char *val, void *opaque) DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); return -rte_errno; } - if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { + if (tmp < 0) { /* Negative values are acceptable for some keys only. */ rte_errno = EINVAL; DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); return -rte_errno; } - mod = tmp >= 0 ? tmp : -tmp; if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { DRV_LOG(ERR, "invalid CQE compression " @@ -1941,9 +2181,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque) } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { config->mprq.enabled = !!tmp; } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { - config->mprq.stride_num_n = tmp; + config->mprq.log_stride_num = tmp; } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { - config->mprq.stride_size_n = tmp; + config->mprq.log_stride_size = tmp; } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { config->mprq.max_memcpy_len = tmp; } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { @@ -1972,86 +2212,42 @@ mlx5_args_check(const char *key, const char *val, void *opaque) config->txq_inline_mpw = tmp; } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); - } else if (strcmp(MLX5_TX_PP, key) == 0) { - if (!mod) { - DRV_LOG(ERR, "Zero Tx packet pacing parameter"); - rte_errno = EINVAL; - return -rte_errno; - } - config->tx_pp = tmp; - } else if (strcmp(MLX5_TX_SKEW, key) == 0) { - config->tx_skew = tmp; } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { config->rx_vec_en = !!tmp; - } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { - config->l3_vxlan_en = !!tmp; - } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { - config->vf_nl_en = !!tmp; - } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { - config->dv_esw_en = !!tmp; - } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { - config->dv_flow_en = !!tmp; - } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { - if (tmp != MLX5_XMETA_MODE_LEGACY && - tmp != MLX5_XMETA_MODE_META16 && - tmp != MLX5_XMETA_MODE_META32 && - tmp != MLX5_XMETA_MODE_MISS_INFO) { - DRV_LOG(ERR, "invalid extensive " - "metadata parameter"); - rte_errno = EINVAL; - return -rte_errno; - } - if (tmp != MLX5_XMETA_MODE_MISS_INFO) - config->dv_xmeta_en = tmp; - else - config->dv_miss_info = 1; - } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { - config->lacp_by_user = !!tmp; } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { config->max_dump_files_num = tmp; } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { - config->lro.timeout = tmp; - } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) { - DRV_LOG(DEBUG, "class argument is %s.", val); + config->lro_timeout = tmp; } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { config->log_hp_size = tmp; - } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { - if (tmp != MLX5_RCM_NONE && - tmp != MLX5_RCM_LIGHT && - tmp != MLX5_RCM_AGGR) { - DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); - rte_errno = EINVAL; - return -rte_errno; - } - config->reclaim_mode = tmp; - } else if (strcmp(MLX5_DECAP_EN, key) == 0) { - config->decap_en = !!tmp; - } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { - config->allow_duplicate_pattern = !!tmp; - } else { - DRV_LOG(WARNING, "%s: unknown parameter", key); - rte_errno = EINVAL; - return -rte_errno; + } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { + config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); + config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); } return 0; } /** - * Parse device parameters. + * Parse user port parameters and adjust them according to device capabilities. * + * @param priv + * Pointer to shared device context. + * @param mkvlist + * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. * @param config - * Pointer to device configuration structure. - * @param devargs - * Device arguments structure. + * Pointer to port configuration structure. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) +mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, + struct mlx5_port_config *config) { + struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; + struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; + bool devx = priv->sh->cdev->config.devx; const char **params = (const char *[]){ - MLX5_DRIVER_KEY, MLX5_RXQ_CQE_COMP_EN, MLX5_RXQ_PKT_PAD_EN, MLX5_RX_MPRQ_EN, @@ -2068,56 +2264,341 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_TXQ_MPW_EN, MLX5_TXQ_MPW_HDR_DSEG_EN, MLX5_TXQ_MAX_INLINE_LEN, - MLX5_TX_DB_NC, - MLX5_TX_PP, - MLX5_TX_SKEW, MLX5_TX_VEC_EN, MLX5_RX_VEC_EN, - MLX5_L3_VXLAN_EN, - MLX5_VF_NL_EN, - MLX5_DV_ESW_EN, - MLX5_DV_FLOW_EN, - MLX5_DV_XMETA_EN, - MLX5_LACP_BY_USER, - MLX5_MR_EXT_MEMSEG_EN, MLX5_REPRESENTOR, MLX5_MAX_DUMP_FILES_NUM, MLX5_LRO_TIMEOUT_USEC, - RTE_DEVARGS_KEY_CLASS, MLX5_HP_BUF_SIZE, - MLX5_RECLAIM_MEM, - MLX5_SYS_MEM_EN, - MLX5_DECAP_EN, - MLX5_ALLOW_DUPLICATE_PATTERN, - MLX5_MR_MEMPOOL_REG_EN, + MLX5_DELAY_DROP, NULL, }; - struct rte_kvargs *kvlist; int ret = 0; - int i; - if (devargs == NULL) + /* Default configuration. */ + memset(config, 0, sizeof(*config)); + config->mps = MLX5_ARG_UNSET; + config->cqe_comp = 1; + config->rx_vec_en = 1; + config->txq_inline_max = MLX5_ARG_UNSET; + config->txq_inline_min = MLX5_ARG_UNSET; + config->txq_inline_mpw = MLX5_ARG_UNSET; + config->txqs_inline = MLX5_ARG_UNSET; + config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; + config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; + config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; + config->log_hp_size = MLX5_ARG_UNSET; + config->std_delay_drop = 0; + config->hp_delay_drop = 0; + if (mkvlist != NULL) { + /* Process parameters. */ + ret = mlx5_kvargs_process(mkvlist, params, + mlx5_port_args_check_handler, config); + if (ret) { + DRV_LOG(ERR, "Failed to process port arguments: %s", + strerror(rte_errno)); + return -rte_errno; + } + } + /* Adjust parameters according to device capabilities. */ + if (config->hw_padding && !dev_cap->hw_padding) { + DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); + config->hw_padding = 0; + } else if (config->hw_padding) { + DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); + } + /* + * MPW is disabled by default, while the Enhanced MPW is enabled + * by default. + */ + if (config->mps == MLX5_ARG_UNSET) + config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? + MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; + else + config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; + DRV_LOG(INFO, "%sMPS is %s", + config->mps == MLX5_MPW_ENHANCED ? "enhanced " : + config->mps == MLX5_MPW ? "legacy " : "", + config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); + /* LRO is supported only when DV flow enabled. */ + if (dev_cap->lro_supported && !priv->sh->config.dv_flow_en) + dev_cap->lro_supported = 0; + if (dev_cap->lro_supported) { + /* + * If LRO timeout is not configured by application, + * use the minimal supported value. + */ + if (!config->lro_timeout) + config->lro_timeout = + hca_attr->lro_timer_supported_periods[0]; + DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", + config->lro_timeout); + } + if (config->cqe_comp && !dev_cap->cqe_comp) { + DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); + config->cqe_comp = 0; + } + if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && + (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { + DRV_LOG(WARNING, + "Flow Tag CQE compression format isn't supported."); + config->cqe_comp = 0; + } + if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && + (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { + DRV_LOG(WARNING, + "L3/L4 Header CQE compression format isn't supported."); + config->cqe_comp = 0; + } + DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.", + config->cqe_comp ? "" : "not "); + if ((config->std_delay_drop || config->hp_delay_drop) && + !dev_cap->rq_delay_drop_en) { + config->std_delay_drop = 0; + config->hp_delay_drop = 0; + DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", + priv->dev_port); + } + if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { + DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); + config->mprq.enabled = 0; + } + if (config->max_dump_files_num == 0) + config->max_dump_files_num = 128; + /* Detect minimal data bytes to inline. */ + mlx5_set_min_inline(priv); + DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", + config->hw_vlan_insert ? "" : "not "); + DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); + DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); + DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); + DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); + DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", + config->std_delay_drop); + DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); + DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", + config->max_dump_files_num); + DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); + DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); + DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", + config->mprq.log_stride_num); + DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", + config->mprq.log_stride_size); + DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", + config->mprq.max_memcpy_len); + DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); + DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); + DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); + DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); + DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); + DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); + DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); + return 0; +} + +/** + * Print the key for device argument. + * + * It is "dummy" handler whose whole purpose is to enable using + * mlx5_kvargs_process() function which set devargs as used. + * + * @param key + * Key argument. + * @param val + * Value associated with key, unused. + * @param opaque + * Unused, can be NULL. + * + * @return + * 0 on success, function cannot fail. + */ +static int +mlx5_dummy_handler(const char *key, const char *val, void *opaque) +{ + DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); + RTE_SET_USED(opaque); + RTE_SET_USED(val); + return 0; +} + +/** + * Set requested devargs as used when device is already spawned. + * + * It is necessary since it is valid to ask probe again for existing device, + * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. + * + * @param name + * Name of the existing device. + * @param port_id + * Port identifier of the device. + * @param mkvlist + * Pointer to mlx5 kvargs control to sign as used. + */ +void +mlx5_port_args_set_used(const char *name, uint16_t port_id, + struct mlx5_kvargs_ctrl *mkvlist) +{ + const char **params = (const char *[]){ + MLX5_RXQ_CQE_COMP_EN, + MLX5_RXQ_PKT_PAD_EN, + MLX5_RX_MPRQ_EN, + MLX5_RX_MPRQ_LOG_STRIDE_NUM, + MLX5_RX_MPRQ_LOG_STRIDE_SIZE, + MLX5_RX_MPRQ_MAX_MEMCPY_LEN, + MLX5_RXQS_MIN_MPRQ, + MLX5_TXQ_INLINE, + MLX5_TXQ_INLINE_MIN, + MLX5_TXQ_INLINE_MAX, + MLX5_TXQ_INLINE_MPW, + MLX5_TXQS_MIN_INLINE, + MLX5_TXQS_MAX_VEC, + MLX5_TXQ_MPW_EN, + MLX5_TXQ_MPW_HDR_DSEG_EN, + MLX5_TXQ_MAX_INLINE_LEN, + MLX5_TX_VEC_EN, + MLX5_RX_VEC_EN, + MLX5_REPRESENTOR, + MLX5_MAX_DUMP_FILES_NUM, + MLX5_LRO_TIMEOUT_USEC, + MLX5_HP_BUF_SIZE, + MLX5_DELAY_DROP, + NULL, + }; + + /* Secondary process should not handle devargs. */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return; + MLX5_ASSERT(mkvlist != NULL); + DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " + "already exists, set devargs as used:", name, port_id); + /* This function cannot fail with this handler. */ + mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); +} + +/** + * Check sibling device configurations when probing again. + * + * Sibling devices sharing infiniband device context should have compatible + * configurations. This regards representors and bonding device. + * + * @param cdev + * Pointer to mlx5 device structure. + * @param mkvlist + * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, + struct mlx5_kvargs_ctrl *mkvlist) +{ + struct mlx5_dev_ctx_shared *sh = NULL; + struct mlx5_sh_config *config; + int ret; + + /* Secondary process should not handle devargs. */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; - /* Following UGLY cast is done to pass checkpatch. */ - kvlist = rte_kvargs_parse(devargs->args, params); - if (kvlist == NULL) { - rte_errno = EINVAL; + pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); + /* Search for IB context by common device pointer. */ + LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) + if (sh->cdev == cdev) + break; + pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); + /* There is sh for this device -> it isn't probe again. */ + if (sh == NULL) + return 0; + config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, + sizeof(struct mlx5_sh_config), + RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); + if (config == NULL) { + rte_errno = -ENOMEM; return -rte_errno; } - /* Process parameters. */ - for (i = 0; (params[i] != NULL); ++i) { - if (rte_kvargs_count(kvlist, params[i])) { - ret = rte_kvargs_process(kvlist, params[i], - mlx5_args_check, config); - if (ret) { - rte_errno = EINVAL; - rte_kvargs_free(kvlist); - return -rte_errno; - } - } + /* + * Creates a temporary IB context configure structure according to new + * devargs attached in probing again. + */ + ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); + if (ret) { + DRV_LOG(ERR, "Failed to process device configure: %s", + strerror(rte_errno)); + mlx5_free(config); + return ret; + } + /* + * Checks the match between the temporary structure and the existing + * IB context structure. + */ + if (sh->config.dv_flow_en ^ config->dv_flow_en) { + DRV_LOG(ERR, "\"dv_flow_en\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || + (sh->config.dv_miss_info ^ config->dv_miss_info)) { + DRV_LOG(ERR, "\"dv_xmeta_en\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.dv_esw_en ^ config->dv_esw_en) { + DRV_LOG(ERR, "\"dv_esw_en\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.reclaim_mode ^ config->reclaim_mode) { + DRV_LOG(ERR, "\"reclaim_mode\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; } - rte_kvargs_free(kvlist); + if (sh->config.allow_duplicate_pattern ^ + config->allow_duplicate_pattern) { + DRV_LOG(ERR, "\"allow_duplicate_pattern\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { + DRV_LOG(ERR, "\"l3_vxlan_en\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.decap_en ^ config->decap_en) { + DRV_LOG(ERR, "\"decap_en\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.lacp_by_user ^ config->lacp_by_user) { + DRV_LOG(ERR, "\"lacp_by_user\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.tx_pp ^ config->tx_pp) { + DRV_LOG(ERR, "\"tx_pp\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + if (sh->config.tx_skew ^ config->tx_skew) { + DRV_LOG(ERR, "\"tx_skew\" " + "configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } + mlx5_free(config); return 0; +error: + mlx5_free(config); + rte_errno = EINVAL; + return -rte_errno; } /** @@ -2131,19 +2612,19 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx * and none (0 bytes) for other NICs * - * @param spawn - * Verbs device parameters (name, port, switch_info) to spawn. - * @param config - * Device configuration parameters. + * @param priv + * Pointer to the private device data structure. */ void -mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, - struct mlx5_dev_config *config) +mlx5_set_min_inline(struct mlx5_priv *priv) { + struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; + struct mlx5_port_config *config = &priv->config; + if (config->txq_inline_min != MLX5_ARG_UNSET) { /* Application defines size of inlined data explicitly. */ - if (spawn->pci_dev != NULL) { - switch (spawn->pci_dev->id.device_id) { + if (priv->pci_dev != NULL) { + switch (priv->pci_dev->id.device_id) { case PCI_DEVICE_ID_MELLANOX_CONNECTX4: case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: if (config->txq_inline_min < @@ -2159,9 +2640,9 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, } goto exit; } - if (config->hca_attr.eth_net_offloads) { + if (hca_attr->eth_net_offloads) { /* We have DevX enabled, inline mode queried successfully. */ - switch (config->hca_attr.wqe_inline_mode) { + switch (hca_attr->wqe_inline_mode) { case MLX5_CAP_INLINE_MODE_L2: /* outer L2 header must be inlined. */ config->txq_inline_min = MLX5_INLINE_HSIZE_L2; @@ -2170,14 +2651,14 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, /* No inline data are required by NIC. */ config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; config->hw_vlan_insert = - config->hca_attr.wqe_vlan_insert; + hca_attr->wqe_vlan_insert; DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); goto exit; case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: /* inline mode is defined by NIC vport context. */ - if (!config->hca_attr.eth_virt) + if (!hca_attr->eth_virt) break; - switch (config->hca_attr.vport_inline_mode) { + switch (hca_attr->vport_inline_mode) { case MLX5_INLINE_MODE_NONE: config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; @@ -2209,7 +2690,7 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, } } } - if (spawn->pci_dev == NULL) { + if (priv->pci_dev == NULL) { config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; goto exit; } @@ -2218,7 +2699,7 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, * inline data size with DevX. Try PCI ID * to determine old NICs. */ - switch (spawn->pci_dev->id.device_id) { + switch (priv->pci_dev->id.device_id) { case PCI_DEVICE_ID_MELLANOX_CONNECTX4: case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: @@ -2260,7 +2741,7 @@ mlx5_set_metadata_mask(struct rte_eth_dev *dev) uint32_t meta, mark, reg_c0; reg_c0 = ~priv->vport_meta_mask; - switch (priv->config.dv_xmeta_en) { + switch (sh->config.dv_xmeta_en) { case MLX5_XMETA_MODE_LEGACY: meta = UINT32_MAX; mark = MLX5_FLOW_MARK_MASK; @@ -2280,21 +2761,21 @@ mlx5_set_metadata_mask(struct rte_eth_dev *dev) break; } if (sh->dv_mark_mask && sh->dv_mark_mask != mark) - DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X", + DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", sh->dv_mark_mask, mark); else sh->dv_mark_mask = mark; if (sh->dv_meta_mask && sh->dv_meta_mask != meta) - DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X", + DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", sh->dv_meta_mask, meta); else sh->dv_meta_mask = meta; if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) - DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X", + DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", sh->dv_meta_mask, reg_c0); else sh->dv_regc0_mask = reg_c0; - DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en); + DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); @@ -2320,60 +2801,6 @@ rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) return RTE_DIM(dynf_names); } -/** - * Comparison callback to sort device data. - * - * This is meant to be used with qsort(). - * - * @param a[in] - * Pointer to pointer to first data object. - * @param b[in] - * Pointer to pointer to second data object. - * - * @return - * 0 if both objects are equal, less than 0 if the first argument is less - * than the second, greater than 0 otherwise. - */ -int -mlx5_dev_check_sibling_config(struct mlx5_priv *priv, - struct mlx5_dev_config *config, - struct rte_device *dpdk_dev) -{ - struct mlx5_dev_ctx_shared *sh = priv->sh; - struct mlx5_dev_config *sh_conf = NULL; - uint16_t port_id; - - MLX5_ASSERT(sh); - /* Nothing to compare for the single/first device. */ - if (sh->refcnt == 1) - return 0; - /* Find the device with shared context. */ - MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { - struct mlx5_priv *opriv = - rte_eth_devices[port_id].data->dev_private; - - if (opriv && opriv != priv && opriv->sh == sh) { - sh_conf = &opriv->config; - break; - } - } - if (!sh_conf) - return 0; - if (sh_conf->dv_flow_en ^ config->dv_flow_en) { - DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch" - " for shared %s context", sh->ibdev_name); - rte_errno = EINVAL; - return rte_errno; - } - if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) { - DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch" - " for shared %s context", sh->ibdev_name); - rte_errno = EINVAL; - return rte_errno; - } - return 0; -} - /** * Look for the ethernet device belonging to mlx5 driver. *