X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=0c4ebb275b1e7d080030214e0eb9e81b04674a23;hb=50cc92dde839ba7904b7ffa3aa0bb7b1a8e0e8c5;hp=eadb797bda9f497988abb5891c784ccf528d73c4;hpb=1872635570becc389b0a069a540a12454d796c97;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index eadb797bda..0c4ebb275b 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -10,22 +10,23 @@ #include #include #include -#include #include #include #include -#include +#include #include #include #include #include +#include #include #include #include #include #include +#include #include "mlx5_defs.h" #include "mlx5_utils.h" @@ -36,7 +37,7 @@ #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) enum mlx5_ipool_index { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ MLX5_IPOOL_TAG, /* Pool for tag resource. */ @@ -44,6 +45,8 @@ enum mlx5_ipool_index { MLX5_IPOOL_JUMP, /* Pool for jump resource. */ MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ + MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ + MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ #endif MLX5_IPOOL_MTR, /* Pool for meter resource. */ MLX5_IPOOL_MCP, /* Pool for metadata resource. */ @@ -51,8 +54,8 @@ enum mlx5_ipool_index { MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ - MLX5_IPOOL_TUNNEL_ID, /* Pool for flow tunnel ID. */ - MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ + MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ + MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ MLX5_IPOOL_MAX, }; @@ -82,6 +85,11 @@ struct mlx5_dev_attr { int max_sge; int max_cq; int max_qp; + int max_cqe; + uint32_t max_pd; + uint32_t max_mr; + uint32_t max_srq; + uint32_t max_srq_wr; uint32_t raw_packet_caps; uint32_t max_rwq_indirection_table_size; uint32_t max_tso; @@ -108,6 +116,17 @@ struct mlx5_dev_spawn_data { void *phys_dev; /**< Associated physical device. */ struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ struct rte_pci_device *pci_dev; /**< Backend PCI device. */ + struct mlx5_bond_info *bond_info; +}; + +/** Data associated with socket messages. */ +struct mlx5_flow_dump_req { + uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ + uint64_t flow_id; +} __rte_packed; + +struct mlx5_flow_dump_ack { + int rc; /**< Return code. */ }; /** Key string for IPC. */ @@ -134,9 +153,9 @@ struct mlx5_local_data { extern struct mlx5_shared_data *mlx5_shared_data; /* Dev ops structs */ -extern const struct eth_dev_ops mlx5_os_dev_ops; -extern const struct eth_dev_ops mlx5_os_dev_sec_ops; -extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; +extern const struct eth_dev_ops mlx5_dev_ops; +extern const struct eth_dev_ops mlx5_dev_sec_ops; +extern const struct eth_dev_ops mlx5_dev_ops_isolate; struct mlx5_counter_ctrl { /* Name of the counter. */ @@ -205,7 +224,7 @@ struct mlx5_dev_config { /* Whether tunnel stateless offloads are supported. */ unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ unsigned int cqe_comp:1; /* CQE compression is enabled. */ - unsigned int cqe_pad:1; /* CQE padding is enabled. */ + unsigned int cqe_comp_fmt:3; /* CQE compression format. */ unsigned int tso:1; /* Whether TSO is supported. */ unsigned int rx_vec_en:1; /* Rx vector is enabled. */ unsigned int mr_ext_memseg_en:1; @@ -256,41 +275,30 @@ struct mlx5_dev_config { }; -/** - * Type of object being allocated. - */ -enum mlx5_verbs_alloc_type { - MLX5_VERBS_ALLOC_TYPE_NONE, - MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, - MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, -}; - /* Structure for VF VLAN workaround. */ struct mlx5_vf_vlan { uint32_t tag:12; uint32_t created:1; }; -/** - * Verbs allocator needs a context to know in the callback which kind of - * resources it is allocating. - */ -struct mlx5_verbs_alloc_ctx { - enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ - const void *obj; /* Pointer to the DPDK object. */ -}; - /* Flow drop context necessary due to Verbs API. */ struct mlx5_drop { struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ struct mlx5_rxq_obj *rxq; /* Rx queue object. */ }; +/* Loopback dummy queue resources required due to Verbs API. */ +struct mlx5_lb_ctx { + struct ibv_qp *qp; /* QP object. */ + void *ibv_cq; /* Completion queue. */ + uint16_t refcnt; /* Reference count for representors. */ +}; + #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 #define MLX5_CNT_CONTAINER_RESIZE 64 #define MLX5_CNT_SHARED_OFFSET 0x80000000 -#define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) +#define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ MLX5_CNT_BATCH_OFFSET) #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) @@ -352,7 +360,10 @@ struct flow_counter_stats { /* Shared counters information for counters. */ struct mlx5_flow_counter_shared { - uint32_t id; /**< User counter ID. */ + union { + uint32_t refcnt; /* Only for shared action management. */ + uint32_t id; /* User counter ID for legacy sharing. */ + }; }; /* Shared counter configuration. */ @@ -465,16 +476,98 @@ struct mlx5_flow_counter_mng { uint8_t pending_queries; uint16_t pool_index; uint8_t query_thread_on; - bool relaxed_ordering; + bool relaxed_ordering_read; + bool relaxed_ordering_write; bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; +/* ASO structures. */ +#define MLX5_ASO_QUEUE_LOG_DESC 10 + +struct mlx5_aso_cq { + uint16_t log_desc_n; + uint32_t cq_ci:24; + struct mlx5_devx_cq cq_obj; + uint64_t errors; +}; + +struct mlx5_aso_sq_elem { + union { + struct { + struct mlx5_aso_age_pool *pool; + uint16_t burst_size; + }; + struct mlx5_aso_mtr *mtr; + struct { + struct mlx5_aso_ct_action *ct; + char *query_data; + }; + }; +}; + +struct mlx5_aso_sq { + uint16_t log_desc_n; + rte_spinlock_t sqsl; + struct mlx5_aso_cq cq; + struct mlx5_devx_sq sq_obj; + volatile uint64_t *uar_addr; + struct mlx5_pmd_mr mr; + uint16_t pi; + uint32_t head; + uint32_t tail; + uint32_t sqn; + struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; + uint16_t next; /* Pool index of the next pool to query. */ +}; + +struct mlx5_aso_age_action { + LIST_ENTRY(mlx5_aso_age_action) next; + void *dr_action; + uint32_t refcnt; + /* Following fields relevant only when action is active. */ + uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ + struct mlx5_age_param age_params; +}; + +#define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 + +struct mlx5_aso_age_pool { + struct mlx5_devx_obj *flow_hit_aso_obj; + uint16_t index; /* Pool index in pools array. */ + uint64_t time_of_last_age_check; /* In seconds. */ + struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; +}; + +LIST_HEAD(aso_age_list, mlx5_aso_age_action); + +struct mlx5_aso_age_mng { + struct mlx5_aso_age_pool **pools; + uint16_t n; /* Total number of pools. */ + uint16_t next; /* Number of pools in use, index of next free pool. */ + rte_spinlock_t resize_sl; /* Lock for resize objects. */ + rte_spinlock_t free_sl; /* Lock for free list access. */ + struct aso_age_list free; /* Free age actions list - ready to use. */ + struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ +}; + +/* Management structure for geneve tlv option */ +struct mlx5_geneve_tlv_option_resource { + struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ + rte_be16_t option_class; /* geneve tlv opt class.*/ + uint8_t option_type; /* geneve tlv opt type.*/ + uint8_t length; /* geneve tlv opt length. */ + uint32_t refcnt; /* geneve tlv object reference counter */ +}; + + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ ((age_info)->flags |= (1 << (BIT))) +#define MLX5_AGE_UNSET(age_info, BIT) \ + ((age_info)->flags &= ~(1 << (BIT))) #define MLX5_AGE_GET(age_info, BIT) \ ((age_info)->flags & (1 << (BIT))) #define GET_PORT_AGE_INFO(priv) \ @@ -485,8 +578,9 @@ struct mlx5_flow_counter_mng { /* Aging information for per port. */ struct mlx5_age_info { uint8_t flags; /* Indicate if is new event or need to be triggered. */ - struct mlx5_counters aged_counters; /* Aged flow counter list. */ - rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ + struct mlx5_counters aged_counters; /* Aged counter list. */ + struct aso_age_list aged_aso; /* Aged ASO actions list. */ + rte_spinlock_t aged_sl; /* Aged flow list lock. */ }; /* Per port data of shared IB device. */ @@ -504,14 +598,314 @@ struct mlx5_dev_shared_port { /* Aging information for per port. */ }; +/* + * Max number of actions per DV flow. + * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED + * in rdma-core file providers/mlx5/verbs.c. + */ +#define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 + +/*ASO flow meter structures*/ +/* Modify this value if enum rte_mtr_color changes. */ +#define RTE_MTR_DROPPED RTE_COLORS +/* Yellow is not supported. */ +#define MLX5_MTR_RTE_COLORS (RTE_COLOR_GREEN + 1) +/* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ +#define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF +#define MLX5_INVALID_POLICY_ID UINT32_MAX +/* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ +#define MLX5_MTR_TABLE_ID_SUFFIX 1 +/* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ +#define MLX5_MTR_TABLE_ID_DROP 2 + +enum mlx5_meter_domain { + MLX5_MTR_DOMAIN_INGRESS, + MLX5_MTR_DOMAIN_EGRESS, + MLX5_MTR_DOMAIN_TRANSFER, + MLX5_MTR_DOMAIN_MAX, +}; +#define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) +#define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) +#define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) +#define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ + MLX5_MTR_DOMAIN_EGRESS_BIT | \ + MLX5_MTR_DOMAIN_TRANSFER_BIT) + +/* + * Meter sub-policy structure. + * Each RSS TIR in meter policy need its own sub-policy resource. + */ +struct mlx5_flow_meter_sub_policy { + uint32_t main_policy_id:1; + /* Main policy id is same as this sub_policy id. */ + uint32_t idx:31; + /* Index to sub_policy ipool entity. */ + void *main_policy; + /* Point to struct mlx5_flow_meter_policy. */ + struct mlx5_flow_tbl_resource *tbl_rsc; + /* The sub-policy table resource. */ + uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; + /* Index to TIR resource. */ + struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; + /* Meter jump/drop table. */ + struct mlx5_flow_dv_matcher *color_matcher[RTE_COLORS]; + /* Matcher for Color. */ + void *color_rule[RTE_COLORS]; + /* Meter green/yellow/drop rule. */ +}; + +struct mlx5_meter_policy_acts { + uint8_t actions_n; + /* Number of actions. */ + void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; + /* Action list. */ +}; + +struct mlx5_meter_policy_action_container { + uint32_t rix_mark; + /* Index to the mark action. */ + struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; + /* Pointer to modify header resource in cache. */ + uint8_t fate_action; + /* Fate action type. */ + union { + struct rte_flow_action *rss; + /* Rss action configuration. */ + uint32_t rix_port_id_action; + /* Index to port ID action resource. */ + void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; + /* Jump/drop action per color. */ + uint16_t queue; + /* Queue action configuration. */ + struct { + uint32_t next_mtr_id; + /* The next meter id. */ + void *next_sub_policy; + /* Next meter's sub-policy. */ + }; + }; +}; + +/* Flow meter policy parameter structure. */ +struct mlx5_flow_meter_policy { + struct rte_eth_dev *dev; + /* The port dev on which policy is created. */ + uint32_t is_rss:1; + /* Is RSS policy table. */ + uint32_t ingress:1; + /* Rule applies to ingress domain. */ + uint32_t egress:1; + /* Rule applies to egress domain. */ + uint32_t transfer:1; + /* Rule applies to transfer domain. */ + uint32_t is_queue:1; + /* Is queue action in policy table. */ + uint32_t is_hierarchy:1; + /* Is meter action in policy table. */ + rte_spinlock_t sl; + uint32_t ref_cnt; + /* Use count. */ + struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; + /* Policy actions container. */ + void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; + /* drop action for red color. */ + uint16_t sub_policy_num; + /* Count sub policy tables, 3 bits per domain. */ + struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; + /* Sub policy table array must be the end of struct. */ +}; + +/* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ +#define MLX5_MTR_RSS_MAX_SUB_POLICY 7 +#define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 +#define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 +#define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF +#define MLX5_MTR_CHAIN_MAX_NUM 8 + +/* Flow meter default policy parameter structure. + * Policy index 0 is reserved by default policy table. + * Action per color as below: + * green - do nothing, yellow - do nothing, red - drop + */ +struct mlx5_flow_meter_def_policy { + struct mlx5_flow_meter_sub_policy sub_policy; + /* Policy rules jump to other tables. */ + void *dr_jump_action[RTE_COLORS]; + /* Jump action per color. */ +}; + +/* Meter parameter structure. */ +struct mlx5_flow_meter_info { + uint32_t meter_id; + /**< Meter id. */ + uint32_t policy_id; + /* Policy id, the first sub_policy idx. */ + struct mlx5_flow_meter_profile *profile; + /**< Meter profile parameters. */ + rte_spinlock_t sl; /**< Meter action spinlock. */ + /** Set of stats counters to be enabled. + * @see enum rte_mtr_stats_type + */ + uint32_t bytes_dropped:1; + /** Set bytes dropped stats to be enabled. */ + uint32_t pkts_dropped:1; + /** Set packets dropped stats to be enabled. */ + uint32_t active_state:1; + /**< Meter hw active state. */ + uint32_t shared:1; + /**< Meter shared or not. */ + uint32_t is_enable:1; + /**< Meter disable/enable state. */ + uint32_t ingress:1; + /**< Rule applies to egress traffic. */ + uint32_t egress:1; + /** + * Instead of simply matching the properties of traffic as it would + * appear on a given DPDK port ID, enabling this attribute transfers + * a flow rule to the lowest possible level of any device endpoints + * found in the pattern. + * + * When supported, this effectively enables an application to + * re-route traffic not necessarily intended for it (e.g. coming + * from or addressed to different physical ports, VFs or + * applications) at the device level. + * + * It complements the behavior of some pattern items such as + * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. + * + * When transferring flow rules, ingress and egress attributes keep + * their original meaning, as if processing traffic emitted or + * received by the application. + */ + uint32_t transfer:1; + uint32_t def_policy:1; + /* Meter points to default policy. */ + void *drop_rule[MLX5_MTR_DOMAIN_MAX]; + /* Meter drop rule in drop table. */ + uint32_t drop_cnt; + /**< Color counter for drop. */ + uint32_t ref_cnt; + /**< Use count. */ + struct mlx5_indexed_pool *flow_ipool; + /**< Index pool for flow id. */ + void *meter_action; + /**< Flow meter action. */ +}; + +/* PPS(packets per second) map to BPS(Bytes per second). + * HW treat packet as 128bytes in PPS mode + */ +#define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 + +/* RFC2697 parameter structure. */ +struct mlx5_flow_meter_srtcm_rfc2697_prm { + rte_be32_t cbs_cir; + /* + * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, + * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. + */ + rte_be32_t ebs_eir; + /* + * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, + * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. + */ +}; + +/* Flow meter profile structure. */ +struct mlx5_flow_meter_profile { + TAILQ_ENTRY(mlx5_flow_meter_profile) next; + /**< Pointer to the next flow meter structure. */ + uint32_t id; /**< Profile id. */ + struct rte_mtr_meter_profile profile; /**< Profile detail. */ + union { + struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; + /**< srtcm_rfc2697 struct. */ + }; + uint32_t ref_cnt; /**< Use count. */ +}; + +/* 2 meters in each ASO cache line */ +#define MLX5_MTRS_CONTAINER_RESIZE 64 +/* + * The pool index and offset of meter in the pool array makes up the + * meter index. In case the meter is from pool 0 and offset 0, it + * should plus 1 to avoid index 0, since 0 means invalid meter index + * currently. + */ +#define MLX5_MAKE_MTR_IDX(pi, offset) \ + ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) + +/*aso flow meter state*/ +enum mlx5_aso_mtr_state { + ASO_METER_FREE, /* In free list. */ + ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ + ASO_METER_READY, /* CQE received. */ +}; + +/* Generic aso_flow_meter information. */ +struct mlx5_aso_mtr { + LIST_ENTRY(mlx5_aso_mtr) next; + struct mlx5_flow_meter_info fm; + /**< Pointer to the next aso flow meter structure. */ + uint8_t state; /**< ASO flow meter state. */ + uint8_t offset; +}; + +/* Generic aso_flow_meter pool structure. */ +struct mlx5_aso_mtr_pool { + struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; + /*Must be the first in pool*/ + struct mlx5_devx_obj *devx_obj; + /* The devx object of the minimum aso flow meter ID. */ + uint32_t index; /* Pool index in management structure. */ +}; + +LIST_HEAD(aso_meter_list, mlx5_aso_mtr); +/* Pools management structure for ASO flow meter pools. */ +struct mlx5_aso_mtr_pools_mng { + volatile uint16_t n_valid; /* Number of valid pools. */ + uint16_t n; /* Number of pools. */ + rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ + struct aso_meter_list meters; /* Free ASO flow meter list. */ + struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ + struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ +}; + +/* Meter management structure for global flow meter resource. */ +struct mlx5_flow_mtr_mng { + struct mlx5_aso_mtr_pools_mng pools_mng; + /* Pools management structure for ASO flow meter pools. */ + struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; + /* Default policy table. */ + uint32_t def_policy_id; + /* Default policy id. */ + uint32_t def_policy_ref_cnt; + /** def_policy meter use count. */ + struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; + /* Meter drop table. */ + struct mlx5_flow_dv_matcher * + drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; + /* Matcher meter in drop table. */ + struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; + /* Default matcher in drop table. */ + void *def_rule[MLX5_MTR_DOMAIN_MAX]; + /* Default rule in drop table. */ + uint8_t max_mtr_bits; + /* Indicate how many bits are used by meter id at the most. */ + uint8_t max_mtr_flow_bits; + /* Indicate how many bits are used by meter flow id at the most. */ +}; + /* Table key of the hash organization. */ union mlx5_flow_tbl_key { struct { /* Table ID should be at the lowest address. */ - uint32_t table_id; /**< ID of the table. */ - uint16_t dummy; /**< Dummy table for DV API. */ - uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ - uint8_t direction; /**< 1 - egress, 0 - ingress. */ + uint32_t level; /**< Level of the table. */ + uint32_t id:22; /**< ID of the table. */ + uint32_t dummy:1; /**< Dummy table for DV API. */ + uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ + uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ + uint32_t reserved:7; /**< must be zero for comparison. */ }; uint64_t v64; /**< full 64bits value of key */ }; @@ -528,9 +922,9 @@ struct mlx5_flow_tbl_resource { #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) /* Tables for metering splits should be added here. */ -#define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) -#define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) -#define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) +#define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) +#define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) +#define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY #define MLX5_MAX_TABLES_FDB UINT16_MAX #define MLX5_FLOW_TABLE_FACTOR 10 @@ -547,31 +941,19 @@ struct mlx5_flow_id_pool { /* Tx pacing queue structure - for Clock and Rearm queues. */ struct mlx5_txpp_wq { /* Completion Queue related data.*/ - struct mlx5_devx_obj *cq; - void *cq_umem; - union { - volatile void *cq_buf; - volatile struct mlx5_cqe *cqes; - }; - volatile uint32_t *cq_dbrec; + struct mlx5_devx_cq cq_obj; uint32_t cq_ci:24; uint32_t arm_sn:2; /* Send Queue related data.*/ - struct mlx5_devx_obj *sq; - void *sq_umem; - union { - volatile void *sq_buf; - volatile struct mlx5_wqe *wqes; - }; + struct mlx5_devx_sq sq_obj; uint16_t sq_size; /* Number of WQEs in the queue. */ uint16_t sq_ci; /* Next WQE to execute. */ - volatile uint32_t *sq_dbrec; }; /* Tx packet pacing internal timestamp. */ struct mlx5_txpp_ts { - rte_atomic64_t ci_ts; - rte_atomic64_t ts; + uint64_t ci_ts; + uint64_t ts; }; /* Tx packet pacing structure. */ @@ -594,11 +976,11 @@ struct mlx5_dev_txpp { struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ /* Statistics counters. */ - rte_atomic32_t err_miss_int; /* Missed service interrupt. */ - rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */ - rte_atomic32_t err_clock_queue; /* Clock Queue errors. */ - rte_atomic32_t err_ts_past; /* Timestamp in the past. */ - rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */ + uint64_t err_miss_int; /* Missed service interrupt. */ + uint64_t err_rearm_queue; /* Rearm Queue errors. */ + uint64_t err_clock_queue; /* Clock Queue errors. */ + uint64_t err_ts_past; /* Timestamp in the past. */ + uint64_t err_ts_future; /* Timestamp in the distant future. */ }; /* Supported flex parser profile ID. */ @@ -615,6 +997,75 @@ struct mlx5_flex_parser_profiles { void *obj; /* Flex parser node object. */ }; +/* Max member ports per bonding device. */ +#define MLX5_BOND_MAX_PORTS 2 + +/* Bonding device information. */ +struct mlx5_bond_info { + int n_port; /* Number of bond member ports. */ + uint32_t ifindex; + char ifname[MLX5_NAMESIZE + 1]; + struct { + char ifname[MLX5_NAMESIZE + 1]; + uint32_t ifindex; + struct rte_pci_addr pci_addr; + } ports[MLX5_BOND_MAX_PORTS]; +}; + +/* Number of connection tracking objects per pool: must be a power of 2. */ +#define MLX5_ASO_CT_ACTIONS_PER_POOL 64 + +/* Generate incremental and unique CT index from pool and offset. */ +#define MLX5_MAKE_CT_IDX(pool, offset) \ + ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) + +/* ASO Conntrack state. */ +enum mlx5_aso_ct_state { + ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ + ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ + ASO_CONNTRACK_READY, /* CQE received w/o error. */ + ASO_CONNTRACK_QUERY, /* WQE for query sent. */ + ASO_CONNTRACK_MAX, /* Guard. */ +}; + +/* Generic ASO connection tracking structure. */ +struct mlx5_aso_ct_action { + LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */ + void *dr_action_orig; /* General action object for original dir. */ + void *dr_action_rply; /* General action object for reply dir. */ + uint32_t refcnt; /* Action used count in device flows. */ + uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ + uint16_t peer; /* The only peer port index could also use this CT. */ + enum mlx5_aso_ct_state state; /* ASO CT state. */ + bool is_original; /* The direction of the DR action to be used. */ +}; + +/* CT action object state update. */ +#define MLX5_ASO_CT_UPDATE_STATE(c, s) \ + __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) + +/* ASO connection tracking software pool definition. */ +struct mlx5_aso_ct_pool { + uint16_t index; /* Pool index in pools array. */ + struct mlx5_devx_obj *devx_obj; + /* The first devx object in the bulk, used for freeing (not yet). */ + struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL]; + /* CT action structures bulk. */ +}; + +LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); + +/* Pools management structure for ASO connection tracking pools. */ +struct mlx5_aso_ct_pools_mng { + struct mlx5_aso_ct_pool **pools; + uint16_t n; /* Total number of pools. */ + uint16_t next; /* Number of pools in use, index of next free pool. */ + rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ + rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ + struct aso_ct_list free_cts; /* Free ASO CT objects list. */ + struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ +}; + /* * Shared Infiniband device context for Master/Representors * which belong to same IB device with multiple IB ports. @@ -623,14 +1074,20 @@ struct mlx5_dev_ctx_shared { LIST_ENTRY(mlx5_dev_ctx_shared) next; uint32_t refcnt; uint32_t devx:1; /* Opened with DV. */ - uint32_t eqn; /* Event Queue number. */ + uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ + uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */ + uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */ + uint32_t qp_ts_format:2; /* QP timestamp formats supported. */ + uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ + uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ uint32_t max_port; /* Maximal IB device port index. */ + struct mlx5_bond_info bond; /* Bonding information. */ void *ctx; /* Verbs/DV/DevX context. */ void *pd; /* Protection Domain. */ uint32_t pdn; /* Protection Domain number. */ uint32_t tdn; /* Transport Domain number. */ - char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ - char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ + char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ + char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ struct mlx5_dev_attr device_attr; /* Device properties. */ int numa_node; /* Numa node of backing physical device. */ LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; @@ -639,7 +1096,6 @@ struct mlx5_dev_ctx_shared { /* Packet pacing related structure. */ struct mlx5_dev_txpp txpp; /* Shared DV/DR flow data section. */ - pthread_mutex_t dv_mutex; /* DV context mutex. */ uint32_t dv_meta_mask; /* flow META metadata supported mask. */ uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ @@ -654,15 +1110,16 @@ struct mlx5_dev_ctx_shared { struct mlx5_hlist *flow_tbls; struct mlx5_flow_tunnel_hub *tunnel_hub; /* Direct Rules tables for FDB, NIC TX+RX */ - void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ + void *dr_drop_action; /* Pointer to DR drop action, any domain. */ void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ struct mlx5_hlist *modify_cmds; struct mlx5_hlist *tag_table; - uint32_t port_id_action_list; /* List of port ID actions. */ - uint32_t push_vlan_action_list; /* List of push VLAN actions. */ - uint32_t sample_action_list; /* List of sample actions. */ - uint32_t dest_array_list; /* List of destination array actions. */ + struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ + struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ + struct mlx5_cache_list sample_action_list; /* List of sample actions. */ + struct mlx5_cache_list dest_array_list; + /* List of destination array actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ void *default_miss_action; /* Default miss action. */ struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; @@ -678,10 +1135,23 @@ struct mlx5_dev_ctx_shared { struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; /* Flex parser profiles information. */ void *devx_rx_uar; /* DevX UAR for Rx. */ + struct mlx5_aso_age_mng *aso_age_mng; + /* Management data for aging mechanism using ASO Flow Hit. */ + struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; + /* Management structure for geneve tlv option */ + rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ + struct mlx5_flow_mtr_mng *mtrmng; + /* Meter management structure. */ + struct mlx5_aso_ct_pools_mng *ct_mng; + /* Management data for ASO connection tracking. */ + struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; -/* Per-process private structure. */ +/* + * Per-process private structure. + * Caution, secondary process may rebuild the struct during port start. + */ struct mlx5_proc_priv { size_t uar_table_sz; /* Size of UAR register table. */ @@ -692,7 +1162,7 @@ struct mlx5_proc_priv { /* MTR profile list. */ TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); /* MTR list. */ -TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); +TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); /* RSS description. */ struct mlx5_flow_rss_desc { @@ -703,11 +1173,13 @@ struct mlx5_flow_rss_desc { uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ uint32_t key_len; /**< RSS hash key len. */ uint32_t tunnel; /**< Queue in tunnel. */ + uint32_t shared_rss; /**< Shared RSS index. */ + struct mlx5_ind_table_obj *ind_tbl; + /**< Indirection table for shared RSS hash RX queues. */ union { uint16_t *queue; /**< Destination queues. */ const uint16_t *const_q; /**< Const pointer convert. */ }; - bool standalone; /**< Queue is standalone or not. */ }; #define MLX5_PROC_PRIV(port_id) \ @@ -725,9 +1197,10 @@ struct mlx5_rxq_obj { void *ibv_cq; /* Completion Queue. */ void *ibv_channel; }; + struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ struct { - struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ - struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ + struct mlx5_devx_rq rq_obj; /* DevX RQ object. */ + struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ void *devx_channel; }; }; @@ -743,14 +1216,13 @@ struct mlx5_ind_table_obj { struct mlx5_devx_obj *rqt; /* DevX RQT object. */ }; uint32_t queues_n; /**< Number of queues in the list. */ - uint16_t queues[]; /**< Queue list. */ + uint16_t *queues; /**< Queue list. */ }; /* Hash Rx queue. */ __extension__ struct mlx5_hrxq { struct mlx5_cache_entry entry; /* Cache entry. */ - uint32_t refcnt; /* Reference counter. */ uint32_t standalone:1; /* This object used in shared action. */ struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ RTE_STD_C11 @@ -758,7 +1230,7 @@ struct mlx5_hrxq { void *qp; /* Verbs queue pair. */ struct mlx5_devx_obj *tir; /* DevX TIR object. */ }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) void *action; /* DV QP action pointer. */ #endif uint64_t hash_fields; /* Verbs Hash fields. */ @@ -784,16 +1256,10 @@ struct mlx5_txq_obj { }; struct { struct rte_eth_dev *dev; - struct mlx5_devx_obj *cq_devx; - void *cq_umem; - void *cq_buf; - int64_t cq_dbrec_offset; - struct mlx5_devx_dbr_page *cq_dbrec_page; - struct mlx5_devx_obj *sq_devx; - void *sq_umem; - void *sq_buf; - int64_t sq_dbrec_offset; - struct mlx5_devx_dbr_page *sq_dbrec_page; + struct mlx5_devx_cq cq_obj; + /* DevX CQ object and its resources. */ + struct mlx5_devx_sq sq_obj; + /* DevX SQ object and its resources. */ }; }; }; @@ -820,6 +1286,10 @@ struct mlx5_obj_ops { void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, struct mlx5_ind_table_obj *ind_tbl); + int (*ind_table_modify)(struct rte_eth_dev *dev, + const unsigned int log_n, + const uint16_t *queues, const uint32_t queues_n, + struct mlx5_ind_table_obj *ind_tbl); void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, int tunnel __rte_unused); @@ -834,6 +1304,16 @@ struct mlx5_obj_ops { int (*txq_obj_modify)(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); + int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); + void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); +}; + +#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) + +/* MR operations structure. */ +struct mlx5_mr_ops { + mlx5_reg_mr_t reg_mr; + mlx5_dereg_mr_t dereg_mr; }; struct mlx5_priv { @@ -852,18 +1332,17 @@ struct mlx5_priv { unsigned int representor:1; /* Device is a port representor. */ unsigned int master:1; /* Device is a E-Switch master. */ unsigned int txpp_en:1; /* Tx packet pacing enabled. */ + unsigned int sampler_en:1; /* Whether support sampler. */ unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ - unsigned int sampler_en:1; /* Whether support sampler. */ + unsigned int lb_used:1; /* Loopback queue is referred to. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ uint32_t vport_meta_mask; /* Used for vport index field match mask. */ - int32_t representor_id; /* Port representor identifier. */ - int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ + uint16_t representor_id; /* UINT16_MAX if not a representor. */ + int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ unsigned int if_index; /* Associated kernel network device index. */ - uint32_t bond_ifindex; /**< Bond interface index. */ - char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ /* RX/TX queues. */ unsigned int rxqs_n; /* RX queues array size. */ unsigned int txqs_n; /* TX queues array size. */ @@ -895,24 +1374,26 @@ struct mlx5_priv { struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ struct mlx5_dev_config config; /* Device configuration. */ - struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_hlist *mreg_cp_tbl; /* Hash table of Rx metadata register copy table. */ uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ uint8_t mtr_color_reg; /* Meter color match REG_C. */ - struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ - struct mlx5_flow_meters flow_meters; /* MTR list. */ + struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ + struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ + struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ + struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ struct mlx5_mp_id mp_id; /* ID of a multi-process process */ LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ - LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions; - /* shared actions */ + rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ + uint32_t rss_shared_actions; /* RSS shared actions. */ + struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ + uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id) @@ -926,14 +1407,24 @@ struct rte_hairpin_peer_info { uint16_t manual_bind; }; +#define BUF_SIZE 1024 +enum dr_dump_rec_type { + DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, + DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, + DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, +}; + /* mlx5.c */ int mlx5_getenv_int(const char *); int mlx5_proc_priv_init(struct rte_eth_dev *dev); +void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); int mlx5_dev_close(struct rte_eth_dev *dev); +bool mlx5_is_hpf(struct rte_eth_dev *dev); +void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); /* Macro to iterate over all valid ports for mlx5 driver. */ #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ @@ -960,10 +1451,23 @@ int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap); bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); +int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); +int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); +int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); /* mlx5_ethdev.c */ int mlx5_dev_configure(struct rte_eth_dev *dev); +int mlx5_representor_info_get(struct rte_eth_dev *dev, + struct rte_eth_representor_info *info); +#define MLX5_REPRESENTOR_ID(pf, type, repr) \ + (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) +#define MLX5_REPRESENTOR_REPR(repr_id) \ + ((repr_id) & 0xfff) +#define MLX5_REPRESENTOR_TYPE(repr_id) \ + (((repr_id) >> 12) & 3) +uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, + enum rte_eth_representor_type hpf_type); int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); int mlx5_dev_infos_get(struct rte_eth_dev *dev, @@ -979,6 +1483,8 @@ int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); /* mlx5_ethdev_os.c */ +int mlx5_get_ifname(const struct rte_eth_dev *dev, + char (*ifname)[MLX5_NAMESIZE]); unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); @@ -1114,10 +1620,7 @@ int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, struct rte_flow_error *error); int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, struct rte_flow_error *error); -int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, - void *arg); +int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); int mlx5_flow_start_default(struct rte_eth_dev *dev); void mlx5_flow_stop_default(struct rte_eth_dev *dev); int mlx5_flow_verify(struct rte_eth_dev *dev); @@ -1132,8 +1635,6 @@ int mlx5_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow_item_eth *eth_mask); int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); -int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); -void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, uint64_t async_id, int status); void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); @@ -1142,11 +1643,23 @@ uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, bool clear, uint64_t *pkts, uint64_t *bytes); -int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, - struct rte_flow_error *error); +int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, + FILE *file, struct rte_flow_error *error); +int save_dump_file(const unsigned char *data, uint32_t size, + uint32_t type, uint32_t id, void *arg, FILE *file); +int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, + struct rte_flow_query_count *count, struct rte_flow_error *error); +#ifdef HAVE_IBV_FLOW_DV_SUPPORT +int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, + FILE *file, struct rte_flow_error *error); +#endif void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, uint32_t nb_contexts, struct rte_flow_error *error); +int mlx5_validate_action_ct(struct rte_eth_dev *dev, + const struct rte_flow_action_conntrack *conntrack, + struct rte_flow_error *error); + /* mlx5_mp_os.c */ @@ -1166,14 +1679,26 @@ int mlx5_pmd_socket_init(void); /* mlx5_flow_meter.c */ int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); -struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, - uint32_t meter_id); -struct mlx5_flow_meter *mlx5_flow_meter_attach - (struct mlx5_priv *priv, - uint32_t meter_id, - const struct rte_flow_attr *attr, - struct rte_flow_error *error); -void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); +struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, + uint32_t meter_id, uint32_t *mtr_idx); +struct mlx5_flow_meter_info * +flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); +int mlx5_flow_meter_attach(struct mlx5_priv *priv, + struct mlx5_flow_meter_info *fm, + const struct rte_flow_attr *attr, + struct rte_flow_error *error); +void mlx5_flow_meter_detach(struct mlx5_priv *priv, + struct mlx5_flow_meter_info *fm); +struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find + (struct rte_eth_dev *dev, + uint32_t policy_id, + uint32_t *policy_idx); +struct mlx5_flow_meter_policy * +mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, + struct mlx5_flow_meter_policy *policy); +int mlx5_flow_meter_flush(struct rte_eth_dev *dev, + struct rte_mtr_error *error); +void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); /* mlx5_os.c */ struct rte_pci_driver; @@ -1218,4 +1743,27 @@ void mlx5_txpp_interrupt_handler(void *cb_arg); eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); +/* mlx5_flow_aso.c */ + +int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, + enum mlx5_access_aso_opc_mod aso_opc_mod); +int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); +int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); +void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, + enum mlx5_access_aso_opc_mod aso_opc_mod); +int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_mtr *mtr); +int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_mtr *mtr); +int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_ct_action *ct, + const struct rte_flow_action_conntrack *profile); +int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_ct_action *ct); +int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_ct_action *ct, + struct rte_flow_action_conntrack *profile); +int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, + struct mlx5_aso_ct_action *ct); + #endif /* RTE_PMD_MLX5_H_ */