X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=2004479e016c0c08ddaa476bb72c78fdb6c461c1;hb=f3faf9ea1185;hp=8f2c541a6e6dfcd37495a01ca1da81c3685a89d4;hpb=46a5e6bc6a85d7e5103e59509096964cbf637d83;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8f2c541a6e..2004479e01 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -32,86 +32,29 @@ #include #include +#include +#include +#include +#include +#include +#include + +#include "mlx5_defs.h" #include "mlx5_utils.h" -#include "mlx5_mr.h" #include "mlx5_autoconf.h" -#include "mlx5_defs.h" -#include "mlx5_glue.h" -#include "mlx5_prm.h" -enum { - PCI_VENDOR_ID_MELLANOX = 0x15b3, -}; - -enum { - PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, - PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, - PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, - PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, - PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, - PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, - PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, - PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, - PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, - PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, - PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, - PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, - PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, - PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, -}; -/* Request types for IPC. */ -enum mlx5_mp_req_type { - MLX5_MP_REQ_VERBS_CMD_FD = 1, - MLX5_MP_REQ_CREATE_MR, - MLX5_MP_REQ_START_RXTX, - MLX5_MP_REQ_STOP_RXTX, - MLX5_MP_REQ_QUEUE_STATE_MODIFY, -}; - -struct mlx5_mp_arg_queue_state_modify { - uint8_t is_wq; /* Set if WQ. */ - uint16_t queue_id; /* DPDK queue ID. */ - enum ibv_wq_state state; /* WQ requested state. */ -}; - -/* Pameters for IPC. */ -struct mlx5_mp_param { - enum mlx5_mp_req_type type; - int port_id; - int result; - RTE_STD_C11 - union { - uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */ - struct mlx5_mp_arg_queue_state_modify state_modify; - /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */ - } args; +enum mlx5_ipool_index { + MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ + MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ + MLX5_IPOOL_TAG, /* Pool for tag resource. */ + MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ + MLX5_IPOOL_MAX, }; -/** Request timeout for IPC. */ -#define MLX5_MP_REQ_TIMEOUT_SEC 5 - /** Key string for IPC. */ #define MLX5_MP_NAME "net_mlx5_mp" -/* Recognized Infiniband device physical port name types. */ -enum mlx5_phys_port_name_type { - MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ - MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ -}; - -/** Switch information returned by mlx5_nl_switch_info(). */ -struct mlx5_switch_info { - uint32_t master:1; /**< Master device. */ - uint32_t representor:1; /**< Representor device. */ - enum mlx5_phys_port_name_type name_type; /** < Port name type. */ - int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ - int32_t port_name; /**< Representor port name. */ - uint64_t switch_id; /**< Switch identifier. */ -}; LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); @@ -148,65 +91,15 @@ struct mlx5_xstats_ctrl { /* Index in the device counters table. */ uint16_t dev_table_idx[MLX5_MAX_XSTATS]; uint64_t base[MLX5_MAX_XSTATS]; + uint64_t xstats[MLX5_MAX_XSTATS]; + uint64_t hw_stats[MLX5_MAX_XSTATS]; struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; }; struct mlx5_stats_ctrl { /* Base for imissed counter. */ uint64_t imissed_base; -}; - -/* devX creation object */ -struct mlx5_devx_obj { - struct mlx5dv_devx_obj *obj; /* The DV object. */ - int id; /* The object ID. */ -}; - -struct mlx5_devx_mkey_attr { - uint64_t addr; - uint64_t size; - uint32_t umem_id; - uint32_t pd; -}; - -/* HCA qos attributes. */ -struct mlx5_hca_qos_attr { - uint32_t sup:1; /* Whether QOS is supported. */ - uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ - uint8_t log_max_flow_meter; - /* Power of the maximum supported meters. */ - uint8_t flow_meter_reg_c_ids; - /* Bitmap of the reg_Cs available for flow meter to use. */ - -}; - -/* HCA supports this number of time periods for LRO. */ -#define MLX5_LRO_NUM_SUPP_PERIODS 4 - -/* HCA attributes. */ -struct mlx5_hca_attr { - uint32_t eswitch_manager:1; - uint32_t flow_counters_dump:1; - uint8_t flow_counter_bulk_alloc_bitmap; - uint32_t eth_net_offloads:1; - uint32_t eth_virt:1; - uint32_t wqe_vlan_insert:1; - uint32_t wqe_inline_mode:2; - uint32_t vport_inline_mode:3; - uint32_t tunnel_stateless_geneve_rx:1; - uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ - uint32_t lro_cap:1; - uint32_t tunnel_lro_gre:1; - uint32_t tunnel_lro_vxlan:1; - uint32_t lro_max_msg_sz_mode:2; - uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; - uint32_t flex_parser_protocols; - uint32_t hairpin:1; - uint32_t log_max_hairpin_queues:5; - uint32_t log_max_hairpin_wq_data_sz:5; - uint32_t log_max_hairpin_num_packets:5; - uint32_t vhca_id:16; - struct mlx5_hca_qos_attr qos; + uint64_t imissed; }; /* Flow list . */ @@ -218,6 +111,12 @@ TAILQ_HEAD(mlx5_flows, rte_flow); #define MLX5_LRO_SUPPORTED(dev) \ (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) +/* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ +#define MLX5_LRO_SEG_CHUNK_SIZE 256u + +/* Maximal size of aggregated LRO packet. */ +#define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) + /* LRO configurations structure. */ struct mlx5_lro_config { uint32_t supported:1; /* Whether LRO is supported. */ @@ -259,6 +158,7 @@ struct mlx5_dev_config { struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ + unsigned int stride_size_n; /* Size of a stride. */ unsigned int min_stride_size_n; /* Min size of a stride. */ unsigned int max_stride_size_n; /* Max size of a stride. */ unsigned int max_memcpy_len; @@ -267,12 +167,14 @@ struct mlx5_dev_config { /* Rx queue count threshold to enable MPRQ. */ } mprq; /* Configurations for Multi-Packet RQ. */ int mps; /* Multi-packet send supported mode. */ + int dbnc; /* Skip doorbell register write barrier. */ unsigned int flow_prio; /* Number of flow priorities. */ enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; /* Availibility of mreg_c's. */ unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ unsigned int ind_table_max_size; /* Maximum indirection table size. */ unsigned int max_dump_files_num; /* Maximum dump files per queue. */ + unsigned int log_hp_size; /* Single hairpin queue data size in total. */ int txqs_inline; /* Queue number threshold for inlining. */ int txq_inline_min; /* Minimal amount of data bytes to inline. */ int txq_inline_max; /* Max packet size for inlining with SEND. */ @@ -281,133 +183,6 @@ struct mlx5_dev_config { struct mlx5_lro_config lro; /* LRO configuration. */ }; -struct mlx5_devx_wq_attr { - uint32_t wq_type:4; - uint32_t wq_signature:1; - uint32_t end_padding_mode:2; - uint32_t cd_slave:1; - uint32_t hds_skip_first_sge:1; - uint32_t log2_hds_buf_size:3; - uint32_t page_offset:5; - uint32_t lwm:16; - uint32_t pd:24; - uint32_t uar_page:24; - uint64_t dbr_addr; - uint32_t hw_counter; - uint32_t sw_counter; - uint32_t log_wq_stride:4; - uint32_t log_wq_pg_sz:5; - uint32_t log_wq_sz:5; - uint32_t dbr_umem_valid:1; - uint32_t wq_umem_valid:1; - uint32_t log_hairpin_num_packets:5; - uint32_t log_hairpin_data_sz:5; - uint32_t single_wqe_log_num_of_strides:4; - uint32_t two_byte_shift_en:1; - uint32_t single_stride_log_num_of_bytes:3; - uint32_t dbr_umem_id; - uint32_t wq_umem_id; - uint64_t wq_umem_offset; -}; - -/* Create RQ attributes structure, used by create RQ operation. */ -struct mlx5_devx_create_rq_attr { - uint32_t rlky:1; - uint32_t delay_drop_en:1; - uint32_t scatter_fcs:1; - uint32_t vsd:1; - uint32_t mem_rq_type:4; - uint32_t state:4; - uint32_t flush_in_error_en:1; - uint32_t hairpin:1; - uint32_t user_index:24; - uint32_t cqn:24; - uint32_t counter_set_id:8; - uint32_t rmpn:24; - struct mlx5_devx_wq_attr wq_attr; -}; - -/* Modify RQ attributes structure, used by modify RQ operation. */ -struct mlx5_devx_modify_rq_attr { - uint32_t rqn:24; - uint32_t rq_state:4; /* Current RQ state. */ - uint32_t state:4; /* Required RQ state. */ - uint32_t scatter_fcs:1; - uint32_t vsd:1; - uint32_t counter_set_id:8; - uint32_t hairpin_peer_sq:24; - uint32_t hairpin_peer_vhca:16; - uint64_t modify_bitmask; - uint32_t lwm:16; /* Contained WQ lwm. */ -}; - -struct mlx5_rx_hash_field_select { - uint32_t l3_prot_type:1; - uint32_t l4_prot_type:1; - uint32_t selected_fields:30; -}; - -/* TIR attributes structure, used by TIR operations. */ -struct mlx5_devx_tir_attr { - uint32_t disp_type:4; - uint32_t lro_timeout_period_usecs:16; - uint32_t lro_enable_mask:4; - uint32_t lro_max_msg_sz:8; - uint32_t inline_rqn:24; - uint32_t rx_hash_symmetric:1; - uint32_t tunneled_offload_en:1; - uint32_t indirect_table:24; - uint32_t rx_hash_fn:4; - uint32_t self_lb_block:2; - uint32_t transport_domain:24; - uint32_t rx_hash_toeplitz_key[10]; - struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; - struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; -}; - -/* RQT attributes structure, used by RQT operations. */ -struct mlx5_devx_rqt_attr { - uint32_t rqt_max_size:16; - uint32_t rqt_actual_size:16; - uint32_t rq_list[]; -}; - -/* TIS attributes structure. */ -struct mlx5_devx_tis_attr { - uint32_t strict_lag_tx_port_affinity:1; - uint32_t tls_en:1; - uint32_t lag_tx_port_affinity:4; - uint32_t prio:4; - uint32_t transport_domain:24; -}; - -/* SQ attributes structure, used by SQ create operation. */ -struct mlx5_devx_create_sq_attr { - uint32_t rlky:1; - uint32_t cd_master:1; - uint32_t fre:1; - uint32_t flush_in_error_en:1; - uint32_t allow_multi_pkt_send_wqe:1; - uint32_t min_wqe_inline_mode:3; - uint32_t state:4; - uint32_t reg_umr:1; - uint32_t allow_swp:1; - uint32_t hairpin:1; - uint32_t user_index:24; - uint32_t cqn:24; - uint32_t packet_pacing_rate_limit_index:16; - uint32_t tis_lst_sz:16; - uint32_t tis_num:24; - struct mlx5_devx_wq_attr wq_attr; -}; - -/* SQ attributes structure, used by SQ modify operation. */ -struct mlx5_devx_modify_sq_attr { - uint32_t sq_state:4; - uint32_t state:4; - uint32_t hairpin_peer_rq:24; - uint32_t hairpin_peer_vhca:16; -}; /** * Type of object being allocated. @@ -418,30 +193,12 @@ enum mlx5_verbs_alloc_type { MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, }; -/* VLAN netdev for VLAN workaround. */ -struct mlx5_vlan_dev { - uint32_t refcnt; - uint32_t ifindex; /**< Own interface index. */ -}; - /* Structure for VF VLAN workaround. */ struct mlx5_vf_vlan { uint32_t tag:12; uint32_t created:1; }; -/* - * Array of VLAN devices created on the base of VF - * used for workaround in virtual environments. - */ -struct mlx5_vlan_vmwa_context { - int nl_socket; - uint32_t nl_sn; - uint32_t vf_ifindex; - struct rte_eth_dev *dev; - struct mlx5_vlan_dev vlan_dev[4096]; -}; - /** * Verbs allocator needs a context to know in the callback which kind of * resources it is allocating. @@ -451,8 +208,6 @@ struct mlx5_verbs_alloc_ctx { const void *obj; /* Pointer to the DPDK object. */ }; -LIST_HEAD(mlx5_mr_list, mlx5_mr); - /* Flow drop context necessary due to Verbs API. */ struct mlx5_drop { struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ @@ -461,6 +216,20 @@ struct mlx5_drop { #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 +#define MLX5_CNT_CONTAINER_RESIZE 64 +/* + * The pool index and offset of counter in the pool array makes up the + * counter index. In case the counter is from pool 0 and offset 0, it + * should plus 1 to avoid index 0, since 0 means invalid counter index + * currently. + */ +#define MLX5_MAKE_CNT_IDX(pi, offset) \ + ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) +#define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \ + ((pool) + 1))[((cnt) - (pool)->counters_raw)]) +#define MLX5_GET_POOL_CNT_EXT(pool, offset) \ + (&((struct mlx5_flow_counter_ext *) \ + ((pool) + 1))[offset]) struct mlx5_flow_counter_pool; @@ -469,15 +238,25 @@ struct flow_counter_stats { uint64_t bytes; }; -/* Counters information. */ +/* Generic counters information. */ struct mlx5_flow_counter { TAILQ_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next flow counter structure. */ + union { + uint64_t hits; /**< Reset value of hits packets. */ + int64_t query_gen; /**< Generation of the last release. */ + }; + uint64_t bytes; /**< Reset value of bytes. */ + void *action; /**< Pointer to the dv action. */ +}; + +/* Extend counters information for none batch counters. */ +struct mlx5_flow_counter_ext { uint32_t shared:1; /**< Share counter ID with other flow rules. */ uint32_t batch: 1; /**< Whether the counter was allocated by batch command. */ uint32_t ref_cnt:30; /**< Reference counter. */ - uint32_t id; /**< Counter ID. */ + uint32_t id; /**< User counter ID. */ union { /**< Holds the counters for the rule. */ #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) struct ibv_counter_set *cs; @@ -485,19 +264,13 @@ struct mlx5_flow_counter { struct ibv_counters *cs; #endif struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ - struct mlx5_flow_counter_pool *pool; /**< The counter pool. */ }; - union { - uint64_t hits; /**< Reset value of hits packets. */ - int64_t query_gen; /**< Generation of the last release. */ - }; - uint64_t bytes; /**< Reset value of bytes. */ - void *action; /**< Pointer to the dv action. */ }; + TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); -/* Counter pool structure - query is in pool resolution. */ +/* Generic counter pool structure - query is in pool resolution. */ struct mlx5_flow_counter_pool { TAILQ_ENTRY(mlx5_flow_counter_pool) next; struct mlx5_counters counters; /* Free counter list. */ @@ -506,12 +279,14 @@ struct mlx5_flow_counter_pool { rte_atomic64_t a64_dcs; }; /* The devx object of the minimum counter ID. */ - rte_atomic64_t query_gen; - uint32_t n_counters: 16; /* Number of devx allocated counters. */ + rte_atomic64_t start_query_gen; /* Query start round. */ + rte_atomic64_t end_query_gen; /* Query end round. */ + uint32_t index; /* Pool index in container. */ rte_spinlock_t sl; /* The pool lock. */ struct mlx5_counter_stats_raw *raw; struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ - struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */ + struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL]; + /* The pool counters memory. */ }; struct mlx5_counter_stats_raw; @@ -571,6 +346,18 @@ struct mlx5_ibv_shared_port { */ }; +/* Table key of the hash organization. */ +union mlx5_flow_tbl_key { + struct { + /* Table ID should be at the lowest address. */ + uint32_t table_id; /**< ID of the table. */ + uint16_t reserved; /**< must be zero for comparison. */ + uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ + uint8_t direction; /**< 1 - egress, 0 - ingress. */ + }; + uint64_t v64; /**< full 64bits value of key */ +}; + /* Table structure. */ struct mlx5_flow_tbl_resource { void *obj; /**< Pointer to DR table object. */ @@ -610,6 +397,7 @@ struct mlx5_flow_id_pool { /**< The next index that can be used without any free elements. */ uint32_t *curr; /**< Pointer to the index to pop. */ uint32_t *last; /**< Pointer to the last element in the empty arrray. */ + uint32_t max_id; /**< Maximum id can be allocated from the pool. */ }; /* @@ -630,13 +418,7 @@ struct mlx5_ibv_shared { struct ibv_device_attr_ex device_attr; /* Device properties. */ LIST_ENTRY(mlx5_ibv_shared) mem_event_cb; /**< Called by memory event callback. */ - struct { - uint32_t dev_gen; /* Generation number to flush local caches. */ - rte_rwlock_t rwlock; /* MR Lock. */ - struct mlx5_mr_btree cache; /* Global MR cache table. */ - struct mlx5_mr_list mr_list; /* Registered MR list. */ - struct mlx5_mr_list mr_free_list; /* Freed MR list. */ - } mr; + struct mlx5_mr_share_cache share_cache; /* Shared DV/DR flow data section. */ pthread_mutex_t dv_mutex; /* DV context mutex. */ uint32_t dv_meta_mask; /* flow META metadata supported mask. */ @@ -644,33 +426,20 @@ struct mlx5_ibv_shared { uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ uint32_t dv_refcnt; /* DV/DR data reference counter. */ void *fdb_domain; /* FDB Direct Rules name space handle. */ - struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB]; - /* FDB Direct Rules tables. */ - struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl; - /* FDB meter suffix rules table. */ void *rx_domain; /* RX Direct Rules name space handle. */ - struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES]; - /* RX Direct Rules tables. */ - struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl; - /* RX meter suffix rules table. */ void *tx_domain; /* TX Direct Rules name space handle. */ - struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES]; - /* TX Direct Rules tables. */ - struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl; - /* TX meter suffix rules table. */ + struct mlx5_hlist *flow_tbls; + /* Direct Rules tables for FDB, NIC TX+RX */ void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ - /* TX Direct Rules tables/ */ - LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; - LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; + uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */ LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; - LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags; - LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl; - LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource) - port_id_action_list; /* List of port ID actions. */ - LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource) - push_vlan_action_list; /* List of push VLAN actions. */ + struct mlx5_hlist *tag_table; + uint32_t port_id_action_list; /* List of port ID actions. */ + uint32_t push_vlan_action_list; /* List of push VLAN actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ + struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; + /* Memory Pool for mlx5 flow resources. */ /* Shared interrupt handler section. */ pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ uint32_t intr_cnt; /* Interrupt handler reference counter. */ @@ -694,6 +463,8 @@ struct mlx5_proc_priv { /* MTR profile list. */ TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); +/* MTR list. */ +TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); #define MLX5_PROC_PRIV(port_id) \ ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) @@ -716,6 +487,7 @@ struct mlx5_priv { unsigned int dr_shared:1; /* DV/DR data is shared. */ unsigned int counter_fallback:1; /* Use counter fallback management. */ unsigned int mtr_en:1; /* Whether support meter. */ + unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ @@ -735,6 +507,9 @@ struct mlx5_priv { struct mlx5_drop drop_queue; /* Flow drop queues. */ struct mlx5_flows flows; /* RTE Flow rules. */ struct mlx5_flows ctrl_flows; /* Control flow rules. */ + void *inter_flows; /* Intermediate resources for flow creation. */ + int flow_idx; /* Intermediate device flow index. */ + int flow_nested_idx; /* Intermediate device flow index, nested. */ LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ @@ -757,21 +532,23 @@ struct mlx5_priv { /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - uint32_t nl_sn; /* Netlink message sequence number. */ LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ - struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ + struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_flow_id_pool *qrss_id_pool; struct mlx5_hlist *mreg_cp_tbl; /* Hash table of Rx metadata register copy table. */ uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ uint8_t mtr_color_reg; /* Meter color match REG_C. */ struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ + struct mlx5_flow_meters flow_meters; /* MTR list. */ #ifndef RTE_ARCH_64 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; /* UAR same-page access control required in 32bit implementations. */ #endif uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ + uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ + struct mlx5_mp_id mp_id; /* ID of a multi-process process */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id) @@ -816,8 +593,6 @@ int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); -int mlx5_dev_to_pci_addr(const char *dev_path, - struct rte_pci_addr *pci_addr); void mlx5_dev_link_status_handler(void *arg); void mlx5_dev_interrupt_handler(void *arg); void mlx5_dev_interrupt_handler_devx(void *arg); @@ -836,8 +611,6 @@ int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); void mlx5_sysfs_check_switch_info(bool device_dir, struct mlx5_switch_info *switch_info); -void mlx5_nl_check_switch_info(bool nun_vf_set, - struct mlx5_switch_info *switch_info); void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, @@ -856,6 +629,8 @@ int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, uint32_t index, uint32_t vmdq); +struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init + (struct rte_eth_dev *dev, uint32_t ifindex); int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *mc_addr_set, @@ -899,6 +674,11 @@ int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); +void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); +void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vf_vlan); +void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vf_vlan); /* mlx5_trigger.c */ @@ -926,7 +706,8 @@ struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, struct rte_flow_error *error); -void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); +void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list, + bool active); int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, const struct rte_flow_action *action, void *data, @@ -939,6 +720,10 @@ int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, void *arg); int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); +int mlx5_flow_start_default(struct rte_eth_dev *dev); +void mlx5_flow_stop_default(struct rte_eth_dev *dev); +void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev); +void mlx5_flow_free_intermediate(struct rte_eth_dev *dev); int mlx5_flow_verify(struct rte_eth_dev *dev); int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, @@ -956,80 +741,33 @@ void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, uint64_t async_id, int status); void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh); void mlx5_flow_query_alarm(void *arg); +uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); +void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); +int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, + bool clear, uint64_t *pkts, uint64_t *bytes); +int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, + struct rte_flow_error *error); /* mlx5_mp.c */ +int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer); +int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer); void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); -int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr); -int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev); -int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev, - struct mlx5_mp_arg_queue_state_modify *sm); -int mlx5_mp_init_primary(void); -void mlx5_mp_uninit_primary(void); -int mlx5_mp_init_secondary(void); -void mlx5_mp_uninit_secondary(void); - -/* mlx5_nl.c */ - -int mlx5_nl_init(int protocol); -int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, - uint32_t index); -int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac, - uint32_t index); -void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); -void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); -int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); -int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); -unsigned int mlx5_nl_portnum(int nl, const char *name); -unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); -int mlx5_nl_switch_info(int nl, unsigned int ifindex, - struct mlx5_switch_info *info); - -struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, - uint32_t ifindex); -void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx); -void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, - struct mlx5_vf_vlan *vf_vlan); -void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, - struct mlx5_vf_vlan *vf_vlan); -/* mlx5_devx_cmds.c */ - -struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, - uint32_t bulk_sz); -int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); -int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, - int clear, uint32_t n_counters, - uint64_t *pkts, uint64_t *bytes, - uint32_t mkey, void *addr, - struct mlx5dv_devx_cmd_comp *cmd_comp, - uint64_t async_id); -int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, - struct mlx5_hca_attr *attr); -struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx, - struct mlx5_devx_mkey_attr *attr); -int mlx5_devx_get_out_command_status(void *out); -int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num, - uint32_t *tis_td); -struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx, - struct mlx5_devx_create_rq_attr *rq_attr, - int socket); -int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, - struct mlx5_devx_modify_rq_attr *rq_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx, - struct mlx5_devx_tir_attr *tir_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx, - struct mlx5_devx_rqt_attr *rqt_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_sq - (struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr); -int mlx5_devx_cmd_modify_sq - (struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_tis - (struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx); +/* mlx5_socket.c */ + +int mlx5_pmd_socket_init(void); /* mlx5_flow_meter.c */ int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); +struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, + uint32_t meter_id); +struct mlx5_flow_meter *mlx5_flow_meter_attach + (struct mlx5_priv *priv, + uint32_t meter_id, + const struct rte_flow_attr *attr, + struct rte_flow_error *error); +void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); #endif /* RTE_PMD_MLX5_H_ */