X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=21866778106e73f01a925c03574e141033f932c1;hb=9b9890e20dc4541fd06bc5666e5fb8a507dfb3e9;hp=9f96bd05111c8d4e49d2e5eee7eae220d43b7c07;hpb=84d33890484c68ddf5edcb6ca0840aae0072f97d;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 9f96bd0511..2186677810 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -32,6 +32,9 @@ #include "mlx5_os.h" #include "mlx5_autoconf.h" + +#define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) + enum mlx5_ipool_index { #ifdef HAVE_IBV_FLOW_DV_SUPPORT MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ @@ -41,6 +44,8 @@ enum mlx5_ipool_index { MLX5_IPOOL_JUMP, /* Pool for jump resource. */ MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ + MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ + MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ #endif MLX5_IPOOL_MTR, /* Pool for meter resource. */ MLX5_IPOOL_MCP, /* Pool for metadata resource. */ @@ -48,8 +53,7 @@ enum mlx5_ipool_index { MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ - MLX5_IPOOL_TUNNEL_ID, /* Pool for flow tunnel ID. */ - MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ + MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ MLX5_IPOOL_MAX, }; @@ -65,6 +69,13 @@ enum mlx5_reclaim_mem_mode { MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ }; +/* Hash and cache list callback context. */ +struct mlx5_flow_cb_ctx { + struct rte_eth_dev *dev; + struct rte_flow_error *error; + void *data; +}; + /* Device attributes used in mlx5 PMD */ struct mlx5_dev_attr { uint64_t device_cap_flags_ex; @@ -72,6 +83,11 @@ struct mlx5_dev_attr { int max_sge; int max_cq; int max_qp; + int max_cqe; + uint32_t max_pd; + uint32_t max_mr; + uint32_t max_srq; + uint32_t max_srq_wr; uint32_t raw_packet_caps; uint32_t max_rwq_indirection_table_size; uint32_t max_tso; @@ -195,6 +211,7 @@ struct mlx5_dev_config { /* Whether tunnel stateless offloads are supported. */ unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ unsigned int cqe_comp:1; /* CQE compression is enabled. */ + unsigned int cqe_comp_fmt:3; /* CQE compression format. */ unsigned int cqe_pad:1; /* CQE padding is enabled. */ unsigned int tso:1; /* Whether TSO is supported. */ unsigned int rx_vec_en:1; /* Rx vector is enabled. */ @@ -246,30 +263,12 @@ struct mlx5_dev_config { }; -/** - * Type of object being allocated. - */ -enum mlx5_verbs_alloc_type { - MLX5_VERBS_ALLOC_TYPE_NONE, - MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, - MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, -}; - /* Structure for VF VLAN workaround. */ struct mlx5_vf_vlan { uint32_t tag:12; uint32_t created:1; }; -/** - * Verbs allocator needs a context to know in the callback which kind of - * resources it is allocating. - */ -struct mlx5_verbs_alloc_ctx { - enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ - const void *obj; /* Pointer to the DPDK object. */ -}; - /* Flow drop context necessary due to Verbs API. */ struct mlx5_drop { struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ @@ -455,12 +454,92 @@ struct mlx5_flow_counter_mng { uint8_t pending_queries; uint16_t pool_index; uint8_t query_thread_on; - bool relaxed_ordering; + bool relaxed_ordering_read; + bool relaxed_ordering_write; bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; +/* ASO structures. */ +#define MLX5_ASO_QUEUE_LOG_DESC 10 + +struct mlx5_aso_cq { + uint16_t log_desc_n; + uint32_t cq_ci:24; + struct mlx5_devx_obj *cq; + struct mlx5dv_devx_umem *umem_obj; + union { + volatile void *umem_buf; + volatile struct mlx5_cqe *cqes; + }; + volatile uint32_t *db_rec; + uint64_t errors; +}; + +struct mlx5_aso_devx_mr { + void *buf; + uint64_t length; + struct mlx5dv_devx_umem *umem; + struct mlx5_devx_obj *mkey; + bool is_indirect; +}; + +struct mlx5_aso_sq_elem { + struct mlx5_aso_age_pool *pool; + uint16_t burst_size; +}; + +struct mlx5_aso_sq { + uint16_t log_desc_n; + struct mlx5_aso_cq cq; + struct mlx5_devx_obj *sq; + struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */ + union { + volatile void *umem_buf; + volatile struct mlx5_aso_wqe *wqes; + }; + volatile uint32_t *db_rec; + volatile uint64_t *uar_addr; + struct mlx5_aso_devx_mr mr; + uint16_t pi; + uint32_t head; + uint32_t tail; + uint32_t sqn; + struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; + uint16_t next; /* Pool index of the next pool to query. */ +}; + +struct mlx5_aso_age_action { + LIST_ENTRY(mlx5_aso_age_action) next; + void *dr_action; + uint32_t refcnt; + /* Following fields relevant only when action is active. */ + uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ + struct mlx5_age_param age_params; +}; + +#define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 + +struct mlx5_aso_age_pool { + struct mlx5_devx_obj *flow_hit_aso_obj; + uint16_t index; /* Pool index in pools array. */ + uint64_t time_of_last_age_check; /* In seconds. */ + struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; +}; + +LIST_HEAD(aso_age_list, mlx5_aso_age_action); + +struct mlx5_aso_age_mng { + struct mlx5_aso_age_pool **pools; + uint16_t n; /* Total number of pools. */ + uint16_t next; /* Number of pools in use, index of next free pool. */ + rte_spinlock_t resize_sl; /* Lock for resize objects. */ + rte_spinlock_t free_sl; /* Lock for free list access. */ + struct aso_age_list free; /* Free age actions list - ready to use. */ + struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ +}; + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ @@ -475,8 +554,9 @@ struct mlx5_flow_counter_mng { /* Aging information for per port. */ struct mlx5_age_info { uint8_t flags; /* Indicate if is new event or need to be triggered. */ - struct mlx5_counters aged_counters; /* Aged flow counter list. */ - rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ + struct mlx5_counters aged_counters; /* Aged counter list. */ + struct aso_age_list aged_aso; /* Aged ASO actions list. */ + rte_spinlock_t aged_sl; /* Aged flow list lock. */ }; /* Per port data of shared IB device. */ @@ -518,9 +598,9 @@ struct mlx5_flow_tbl_resource { #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) /* Tables for metering splits should be added here. */ -#define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) -#define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) +#define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) +#define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_METER #define MLX5_MAX_TABLES_FDB UINT16_MAX #define MLX5_FLOW_TABLE_FACTOR 10 @@ -560,8 +640,8 @@ struct mlx5_txpp_wq { /* Tx packet pacing internal timestamp. */ struct mlx5_txpp_ts { - rte_atomic64_t ci_ts; - rte_atomic64_t ts; + uint64_t ci_ts; + uint64_t ts; }; /* Tx packet pacing structure. */ @@ -584,11 +664,11 @@ struct mlx5_dev_txpp { struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ /* Statistics counters. */ - rte_atomic32_t err_miss_int; /* Missed service interrupt. */ - rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */ - rte_atomic32_t err_clock_queue; /* Clock Queue errors. */ - rte_atomic32_t err_ts_past; /* Timestamp in the past. */ - rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */ + uint64_t err_miss_int; /* Missed service interrupt. */ + uint64_t err_rearm_queue; /* Rearm Queue errors. */ + uint64_t err_clock_queue; /* Clock Queue errors. */ + uint64_t err_ts_past; /* Timestamp in the past. */ + uint64_t err_ts_future; /* Timestamp in the distant future. */ }; /* Supported flex parser profile ID. */ @@ -612,7 +692,9 @@ struct mlx5_flex_parser_profiles { struct mlx5_dev_ctx_shared { LIST_ENTRY(mlx5_dev_ctx_shared) next; uint32_t refcnt; + uint16_t bond_dev; /* Bond primary device id. */ uint32_t devx:1; /* Opened with DV. */ + uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ uint32_t eqn; /* Event Queue number. */ uint32_t max_port; /* Maximal IB device port index. */ void *ctx; /* Verbs/DV/DevX context. */ @@ -629,7 +711,6 @@ struct mlx5_dev_ctx_shared { /* Packet pacing related structure. */ struct mlx5_dev_txpp txpp; /* Shared DV/DR flow data section. */ - pthread_mutex_t dv_mutex; /* DV context mutex. */ uint32_t dv_meta_mask; /* flow META metadata supported mask. */ uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ @@ -649,10 +730,11 @@ struct mlx5_dev_ctx_shared { struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ struct mlx5_hlist *modify_cmds; struct mlx5_hlist *tag_table; - uint32_t port_id_action_list; /* List of port ID actions. */ - uint32_t push_vlan_action_list; /* List of push VLAN actions. */ - uint32_t sample_action_list; /* List of sample actions. */ - uint32_t dest_array_list; /* List of destination array actions. */ + struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ + struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ + struct mlx5_cache_list sample_action_list; /* List of sample actions. */ + struct mlx5_cache_list dest_array_list; + /* List of destination array actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ void *default_miss_action; /* Default miss action. */ struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; @@ -668,6 +750,8 @@ struct mlx5_dev_ctx_shared { struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; /* Flex parser profiles information. */ void *devx_rx_uar; /* DevX UAR for Rx. */ + struct mlx5_aso_age_mng *aso_age_mng; + /* Management data for aging mechanism using ASO Flow Hit. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; @@ -684,6 +768,24 @@ TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); /* MTR list. */ TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); +/* RSS description. */ +struct mlx5_flow_rss_desc { + uint32_t level; + uint32_t queue_num; /**< Number of entries in @p queue. */ + uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ + uint64_t hash_fields; /* Verbs Hash fields. */ + uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ + uint32_t key_len; /**< RSS hash key len. */ + uint32_t tunnel; /**< Queue in tunnel. */ + uint32_t shared_rss; /**< Shared RSS index. */ + struct mlx5_ind_table_obj *ind_tbl; + /**< Indirection table for shared RSS hash RX queues. */ + union { + uint16_t *queue; /**< Destination queues. */ + const uint16_t *const_q; /**< Const pointer convert. */ + }; +}; + #define MLX5_PROC_PRIV(port_id) \ ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) @@ -717,14 +819,13 @@ struct mlx5_ind_table_obj { struct mlx5_devx_obj *rqt; /* DevX RQT object. */ }; uint32_t queues_n; /**< Number of queues in the list. */ - uint16_t queues[]; /**< Queue list. */ + uint16_t *queues; /**< Queue list. */ }; /* Hash Rx queue. */ __extension__ struct mlx5_hrxq { - ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ - uint32_t refcnt; /* Reference counter. */ + struct mlx5_cache_entry entry; /* Cache entry. */ uint32_t standalone:1; /* This object used in shared action. */ struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ RTE_STD_C11 @@ -737,6 +838,7 @@ struct mlx5_hrxq { #endif uint64_t hash_fields; /* Verbs Hash fields. */ uint32_t rss_key_len; /* Hash key length in bytes. */ + uint32_t idx; /* Hash Rx queue index. */ uint8_t rss_key[]; /* Hash key. */ }; @@ -793,6 +895,10 @@ struct mlx5_obj_ops { void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, struct mlx5_ind_table_obj *ind_tbl); + int (*ind_table_modify)(struct rte_eth_dev *dev, + const unsigned int log_n, + const uint16_t *queues, const uint32_t queues_n, + struct mlx5_ind_table_obj *ind_tbl); void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, int tunnel __rte_unused); @@ -809,6 +915,8 @@ struct mlx5_obj_ops { void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); }; +#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) + struct mlx5_priv { struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ @@ -853,7 +961,7 @@ struct mlx5_priv { struct mlx5_obj_ops obj_ops; /* HW objects operations. */ LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ - uint32_t hrxqs; /* Verbs Hash Rx queues. */ + struct mlx5_cache_list hrxqs; /* Hash Rx queues. */ LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ /* Indirection tables. */ @@ -868,7 +976,6 @@ struct mlx5_priv { struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ struct mlx5_dev_config config; /* Device configuration. */ - struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ @@ -884,8 +991,8 @@ struct mlx5_priv { uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ struct mlx5_mp_id mp_id; /* ID of a multi-process process */ LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ - LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions; - /* shared actions */ + rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ + uint32_t rss_shared_actions; /* RSS shared actions. */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id) @@ -907,6 +1014,7 @@ int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); int mlx5_dev_close(struct rte_eth_dev *dev); +void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); /* Macro to iterate over all valid ports for mlx5 driver. */ #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ @@ -933,6 +1041,7 @@ int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap); bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); +int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); /* mlx5_ethdev.c */ @@ -1191,4 +1300,11 @@ void mlx5_txpp_interrupt_handler(void *cb_arg); eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); +/* mlx5_flow_age.c */ + +int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh); +int mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh); +int mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh); +void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh); + #endif /* RTE_PMD_MLX5_H_ */