X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=46e66eb1c6dde52067f6278cda261b49553d04d9;hb=341c894104983f5608671e8fb2be19ade03ed0e9;hp=8ecb59c93b869be03ba60a210ea337bf8dcadf9b;hpb=aec086c9f1c81b583ca8b9f7b50f32452d27840e;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8ecb59c93b..46e66eb1c6 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -210,6 +210,8 @@ struct mlx5_dev_config { unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ unsigned int dv_flow_en:1; /* Enable DV flow. */ unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ + unsigned int lacp_by_user:1; + /* Enable user to manage LACP traffic. */ unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ unsigned int devx:1; /* Whether devx interface is available or not. */ unsigned int dest_tir:1; /* Whether advanced DR API is available. */ @@ -312,6 +314,12 @@ struct mlx5_drop { MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) #define MLX5_CNT_TO_AGE(cnt) \ ((struct mlx5_age_param *)((cnt) + 1)) +/* + * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET + * defines. The pool size is 512, pool index should never reach + * INT16_MAX. + */ +#define POOL_IDX_INVALID UINT16_MAX struct mlx5_flow_counter_pool; @@ -347,13 +355,14 @@ struct flow_counter_stats { uint64_t bytes; }; +struct mlx5_flow_counter_pool; /* Generic counters information. */ struct mlx5_flow_counter { TAILQ_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next flow counter structure. */ union { uint64_t hits; /**< Reset value of hits packets. */ - int64_t query_gen; /**< Generation of the last release. */ + struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ }; uint64_t bytes; /**< Reset value of bytes. */ void *action; /**< Pointer to the dv action. */ @@ -381,16 +390,15 @@ TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); /* Generic counter pool structure - query is in pool resolution. */ struct mlx5_flow_counter_pool { TAILQ_ENTRY(mlx5_flow_counter_pool) next; - struct mlx5_counters counters; /* Free counter list. */ + struct mlx5_counters counters[2]; /* Free counter list. */ union { struct mlx5_devx_obj *min_dcs; rte_atomic64_t a64_dcs; }; /* The devx object of the minimum counter ID. */ - rte_atomic64_t start_query_gen; /* Query start round. */ - rte_atomic64_t end_query_gen; /* Query end round. */ - uint32_t index; /* Pool index in container. */ - uint8_t type; /* Memory type behind the counter array. */ + uint32_t index:29; /* Pool index in container. */ + uint32_t type:2; /* Memory type behind the counter array. */ + volatile uint32_t query_gen:1; /* Query round. */ rte_spinlock_t sl; /* The pool lock. */ struct mlx5_counter_stats_raw *raw; struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ @@ -420,7 +428,12 @@ TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); struct mlx5_pools_container { rte_atomic16_t n_valid; /* Number of valid pools. */ uint16_t n; /* Number of pools. */ + uint16_t last_pool_idx; /* Last used pool index */ + int min_id; /* The minimum counter ID in the pools. */ + int max_id; /* The maximum counter ID in the pools. */ rte_spinlock_t resize_sl; /* The resize lock. */ + rte_spinlock_t csl; /* The counter free list lock. */ + struct mlx5_counters counters; /* Free counter list. */ struct mlx5_counter_pools pool_list; /* Counter pool list. */ struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ struct mlx5_counter_stats_mem_mng *mem_mng; @@ -440,6 +453,12 @@ struct mlx5_flow_counter_mng { LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; +/* Default miss action resource structure. */ +struct mlx5_flow_default_miss_resource { + void *action; /* Pointer to the rdma-core action. */ + rte_atomic32_t refcnt; /* Default miss action reference counter. */ +}; + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ @@ -500,21 +519,6 @@ struct mlx5_flow_tbl_resource { #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) #define MLX5_MAX_TABLES_FDB UINT16_MAX -#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ -#define MLX5_DBR_SIZE 8 -#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) -#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) - -struct mlx5_devx_dbr_page { - /* Door-bell records, must be first member in structure. */ - uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; - LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ - void *umem; - uint32_t dbr_count; /* Number of door-bell records in use. */ - /* 1 bit marks matching door-bell is in use. */ - uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; -}; - /* ID generation structure. */ struct mlx5_flow_id_pool { uint32_t *free_arr; /**< Pointer to the a array of free values. */ @@ -563,8 +567,11 @@ struct mlx5_dev_ctx_shared { uint32_t port_id_action_list; /* List of port ID actions. */ uint32_t push_vlan_action_list; /* List of push VLAN actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ + struct mlx5_flow_default_miss_resource default_miss; + /* Default miss action resource structure. */ struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; /* Memory Pool for mlx5 flow resources. */ + struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ /* Shared interrupt handler section. */ struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ @@ -655,7 +662,7 @@ struct mlx5_priv { /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ + struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_flow_id_pool *qrss_id_pool; struct mlx5_hlist *mreg_cp_tbl; @@ -682,10 +689,6 @@ struct mlx5_priv { int mlx5_getenv_int(const char *); int mlx5_proc_priv_init(struct rte_eth_dev *dev); -int64_t mlx5_get_dbr(struct rte_eth_dev *dev, - struct mlx5_devx_dbr_page **dbr_page); -int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, - uint64_t offset); int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); @@ -879,6 +882,7 @@ int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, int mlx5_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow_item_eth *eth_spec, struct rte_flow_item_eth *eth_mask); +int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); @@ -920,10 +924,6 @@ void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); /* mlx5_os.c */ struct rte_pci_driver; -const char *mlx5_os_get_ctx_device_name(void *ctx); -const char *mlx5_os_get_ctx_device_path(void *ctx); -const char *mlx5_os_get_dev_device_name(void *dev); -uint32_t mlx5_os_get_umem_id(void *umem); int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); void mlx5_os_free_shared_dr(struct mlx5_priv *priv); int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,