X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=5131a470f11de3146f050dce1fb8418ac268c62d;hb=1260a87b2889e3c3791500d221c4932e50794092;hp=f5d9aad2f435e98a2df7e55323b83f79352db53e;hpb=2eb4d0107acc2515e0ee1eceb49cf45e6d49fe76;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index f5d9aad2f4..5131a470f1 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -10,20 +10,9 @@ #include #include #include -#include #include #include -/* Verbs header. */ -/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ -#ifdef PEDANTIC -#pragma GCC diagnostic ignored "-Wpedantic" -#endif -#include -#ifdef PEDANTIC -#pragma GCC diagnostic error "-Wpedantic" -#endif - #include #include #include @@ -35,12 +24,12 @@ #include #include #include -#include #include #include #include "mlx5_defs.h" #include "mlx5_utils.h" +#include "mlx5_os.h" #include "mlx5_autoconf.h" enum mlx5_ipool_index { @@ -97,11 +86,11 @@ struct mlx5_dev_attr { /** Data associated with devices to spawn. */ struct mlx5_dev_spawn_data { uint32_t ifindex; /**< Network interface index. */ - uint32_t max_port; /**< IB device maximal port index. */ - uint32_t ibv_port; /**< IB device physical port index. */ + uint32_t max_port; /**< Device maximal port index. */ + uint32_t phys_port; /**< Device physical port index. */ int pf_bond; /**< bonding device PF index. < 0 - no bonding */ struct mlx5_switch_info info; /**< Switch information. */ - struct ibv_device *ibv_dev; /**< Associated IB device. */ + void *phys_dev; /**< Associated physical device. */ struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ struct rte_pci_device *pci_dev; /**< Backend PCI device. */ }; @@ -128,18 +117,18 @@ struct mlx5_local_data { }; extern struct mlx5_shared_data *mlx5_shared_data; -extern struct rte_pci_driver mlx5_driver; /* Dev ops structs */ -extern const struct eth_dev_ops mlx5_dev_sec_ops; -extern const struct eth_dev_ops mlx5_dev_ops; +extern const struct eth_dev_ops mlx5_os_dev_ops; +extern const struct eth_dev_ops mlx5_os_dev_sec_ops; +extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; struct mlx5_counter_ctrl { /* Name of the counter. */ char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; /* Name of the counter on the device table. */ char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; - uint32_t ib:1; /**< Nonzero for IB counters. */ + uint32_t dev:1; /**< Nonzero for dev counters. */ }; struct mlx5_xstats_ctrl { @@ -208,10 +197,15 @@ struct mlx5_dev_config { unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ unsigned int dv_flow_en:1; /* Enable DV flow. */ unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ + unsigned int lacp_by_user:1; + /* Enable user to manage LACP traffic. */ unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ unsigned int devx:1; /* Whether devx interface is available or not. */ unsigned int dest_tir:1; /* Whether advanced DR API is available. */ unsigned int reclaim_mode:2; /* Memory reclaim mode. */ + unsigned int rt_timestamp:1; /* realtime timestamp format. */ + unsigned int sys_mem_en:1; /* The default memory allocator. */ + unsigned int decap_en:1; /* Whether decap will be used or not. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ @@ -236,6 +230,8 @@ struct mlx5_dev_config { int txq_inline_min; /* Minimal amount of data bytes to inline. */ int txq_inline_max; /* Max packet size for inlining with SEND. */ int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ + int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ + int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ struct mlx5_hca_attr hca_attr; /* HCA attributes. */ struct mlx5_lro_config lro; /* LRO configuration. */ }; @@ -310,6 +306,12 @@ struct mlx5_drop { MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) #define MLX5_CNT_TO_AGE(cnt) \ ((struct mlx5_age_param *)((cnt) + 1)) +/* + * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET + * defines. The pool size is 512, pool index should never reach + * INT16_MAX. + */ +#define POOL_IDX_INVALID UINT16_MAX struct mlx5_flow_counter_pool; @@ -345,13 +347,14 @@ struct flow_counter_stats { uint64_t bytes; }; +struct mlx5_flow_counter_pool; /* Generic counters information. */ struct mlx5_flow_counter { TAILQ_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next flow counter structure. */ union { uint64_t hits; /**< Reset value of hits packets. */ - int64_t query_gen; /**< Generation of the last release. */ + struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ }; uint64_t bytes; /**< Reset value of bytes. */ void *action; /**< Pointer to the dv action. */ @@ -361,8 +364,9 @@ struct mlx5_flow_counter { struct mlx5_flow_counter_ext { uint32_t shared:1; /**< Share counter ID with other flow rules. */ uint32_t batch: 1; + uint32_t skipped:1; /* This counter is skipped or not. */ /**< Whether the counter was allocated by batch command. */ - uint32_t ref_cnt:30; /**< Reference counter. */ + uint32_t ref_cnt:29; /**< Reference counter. */ uint32_t id; /**< User counter ID. */ union { /**< Holds the counters for the rule. */ #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) @@ -379,16 +383,16 @@ TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); /* Generic counter pool structure - query is in pool resolution. */ struct mlx5_flow_counter_pool { TAILQ_ENTRY(mlx5_flow_counter_pool) next; - struct mlx5_counters counters; /* Free counter list. */ + struct mlx5_counters counters[2]; /* Free counter list. */ union { struct mlx5_devx_obj *min_dcs; rte_atomic64_t a64_dcs; }; /* The devx object of the minimum counter ID. */ - rte_atomic64_t start_query_gen; /* Query start round. */ - rte_atomic64_t end_query_gen; /* Query end round. */ - uint32_t index; /* Pool index in container. */ - uint8_t type; /* Memory type behind the counter array. */ + uint32_t index:28; /* Pool index in container. */ + uint32_t type:2; /* Memory type behind the counter array. */ + uint32_t skip_cnt:1; /* Pool contains skipped counter. */ + volatile uint32_t query_gen:1; /* Query round. */ rte_spinlock_t sl; /* The pool lock. */ struct mlx5_counter_stats_raw *raw; struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ @@ -418,7 +422,12 @@ TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); struct mlx5_pools_container { rte_atomic16_t n_valid; /* Number of valid pools. */ uint16_t n; /* Number of pools. */ + uint16_t last_pool_idx; /* Last used pool index */ + int min_id; /* The minimum counter ID in the pools. */ + int max_id; /* The maximum counter ID in the pools. */ rte_spinlock_t resize_sl; /* The resize lock. */ + rte_spinlock_t csl; /* The counter free list lock. */ + struct mlx5_counters counters; /* Free counter list. */ struct mlx5_counter_pools pool_list; /* Counter pool list. */ struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ struct mlx5_counter_stats_mem_mng *mem_mng; @@ -438,6 +447,12 @@ struct mlx5_flow_counter_mng { LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; +/* Default miss action resource structure. */ +struct mlx5_flow_default_miss_resource { + void *action; /* Pointer to the rdma-core action. */ + rte_atomic32_t refcnt; /* Default miss action reference counter. */ +}; + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ @@ -445,7 +460,7 @@ struct mlx5_flow_counter_mng { #define MLX5_AGE_GET(age_info, BIT) \ ((age_info)->flags & (1 << (BIT))) #define GET_PORT_AGE_INFO(priv) \ - (&((priv)->sh->port[(priv)->ibv_port - 1].age_info)) + (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) /* Aging information for per port. */ struct mlx5_age_info { @@ -455,7 +470,7 @@ struct mlx5_age_info { }; /* Per port data of shared IB device. */ -struct mlx5_ibv_shared_port { +struct mlx5_dev_shared_port { uint32_t ih_port_id; uint32_t devx_ih_port_id; /* @@ -498,21 +513,6 @@ struct mlx5_flow_tbl_resource { #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) #define MLX5_MAX_TABLES_FDB UINT16_MAX -#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ -#define MLX5_DBR_SIZE 8 -#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) -#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) - -struct mlx5_devx_dbr_page { - /* Door-bell records, must be first member in structure. */ - uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; - LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ - void *umem; - uint32_t dbr_count; /* Number of door-bell records in use. */ - /* 1 bit marks matching door-bell is in use. */ - uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; -}; - /* ID generation structure. */ struct mlx5_flow_id_pool { uint32_t *free_arr; /**< Pointer to the a array of free values. */ @@ -523,6 +523,78 @@ struct mlx5_flow_id_pool { uint32_t max_id; /**< Maximum id can be allocated from the pool. */ }; +/* Tx pacing queue structure - for Clock and Rearm queues. */ +struct mlx5_txpp_wq { + /* Completion Queue related data.*/ + struct mlx5_devx_obj *cq; + void *cq_umem; + union { + volatile void *cq_buf; + volatile struct mlx5_cqe *cqes; + }; + volatile uint32_t *cq_dbrec; + uint32_t cq_ci:24; + uint32_t arm_sn:2; + /* Send Queue related data.*/ + struct mlx5_devx_obj *sq; + void *sq_umem; + union { + volatile void *sq_buf; + volatile struct mlx5_wqe *wqes; + }; + uint16_t sq_size; /* Number of WQEs in the queue. */ + uint16_t sq_ci; /* Next WQE to execute. */ + volatile uint32_t *sq_dbrec; +}; + +/* Tx packet pacing internal timestamp. */ +struct mlx5_txpp_ts { + rte_atomic64_t ci_ts; + rte_atomic64_t ts; +}; + +/* Tx packet pacing structure. */ +struct mlx5_dev_txpp { + pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ + uint32_t refcnt; /* Pacing reference counter. */ + uint32_t freq; /* Timestamp frequency, Hz. */ + uint32_t tick; /* Completion tick duration in nanoseconds. */ + uint32_t test; /* Packet pacing test mode. */ + int32_t skew; /* Scheduling skew. */ + uint32_t eqn; /* Event Queue number. */ + struct rte_intr_handle intr_handle; /* Periodic interrupt. */ + void *echan; /* Event Channel. */ + struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ + struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ + void *pp; /* Packet pacing context. */ + uint16_t pp_id; /* Packet pacing context index. */ + uint16_t ts_n; /* Number of captured timestamps. */ + uint16_t ts_p; /* Pointer to statisticks timestamp. */ + struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ + struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ + uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ + /* Statistics counters. */ + rte_atomic32_t err_miss_int; /* Missed service interrupt. */ + rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */ + rte_atomic32_t err_clock_queue; /* Clock Queue errors. */ + rte_atomic32_t err_ts_past; /* Timestamp in the past. */ + rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */ +}; + +/* Supported flex parser profile ID. */ +enum mlx5_flex_parser_profile_id { + MLX5_FLEX_PARSER_ECPRI_0 = 0, + MLX5_FLEX_PARSER_MAX = 8, +}; + +/* Sample ID information of flex parser structure. */ +struct mlx5_flex_parser_profiles { + uint32_t num; /* Actual number of samples. */ + uint32_t ids[8]; /* Sample IDs for this profile. */ + uint8_t offset[8]; /* Bytes offset of each parser. */ + void *obj; /* Flex parser node object. */ +}; + /* * Shared Infiniband device context for Master/Representors * which belong to same IB device with multiple IB ports. @@ -536,12 +608,15 @@ struct mlx5_dev_ctx_shared { void *pd; /* Protection Domain. */ uint32_t pdn; /* Protection Domain number. */ uint32_t tdn; /* Transport Domain number. */ - char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ - char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ + char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ + char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ struct mlx5_dev_attr device_attr; /* Device properties. */ + int numa_node; /* Numa node of backing physical device. */ LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; /**< Called by memory event callback. */ struct mlx5_mr_share_cache share_cache; + /* Packet pacing related structure. */ + struct mlx5_dev_txpp txpp; /* Shared DV/DR flow data section. */ pthread_mutex_t dv_mutex; /* DV context mutex. */ uint32_t dv_meta_mask; /* flow META metadata supported mask. */ @@ -551,26 +626,38 @@ struct mlx5_dev_ctx_shared { void *fdb_domain; /* FDB Direct Rules name space handle. */ void *rx_domain; /* RX Direct Rules name space handle. */ void *tx_domain; /* TX Direct Rules name space handle. */ +#ifndef RTE_ARCH_64 + rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ + rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; + /* UAR same-page access control required in 32bit implementations. */ +#endif struct mlx5_hlist *flow_tbls; /* Direct Rules tables for FDB, NIC TX+RX */ void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */ - LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; + struct mlx5_hlist *modify_cmds; struct mlx5_hlist *tag_table; uint32_t port_id_action_list; /* List of port ID actions. */ uint32_t push_vlan_action_list; /* List of push VLAN actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ + struct mlx5_flow_default_miss_resource default_miss; + /* Default miss action resource structure. */ struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; /* Memory Pool for mlx5 flow resources. */ + struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ /* Shared interrupt handler section. */ struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ - struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */ + void *devx_comp; /* DEVX async comp obj. */ struct mlx5_devx_obj *tis; /* TIS object. */ struct mlx5_devx_obj *td; /* Transport domain. */ struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */ - struct mlx5_ibv_shared_port port[]; /* per device port data array. */ + void *tx_uar; /* Tx/packet pacing shared UAR. */ + struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; + /* Flex parser profiles information. */ + void *devx_rx_uar; /* DevX UAR for Rx. */ + struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; /* Per-process private structure. */ @@ -589,10 +676,46 @@ TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); #define MLX5_PROC_PRIV(port_id) \ ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) +enum mlx5_rxq_obj_type { + MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */ + MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */ + MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN, + /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */ +}; + +/* Verbs/DevX Rx queue elements. */ +struct mlx5_rxq_obj { + LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ + struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ + enum mlx5_rxq_obj_type type; + int fd; /* File descriptor for event channel */ + RTE_STD_C11 + union { + struct { + void *wq; /* Work Queue. */ + void *ibv_cq; /* Completion Queue. */ + void *ibv_channel; + }; + struct { + struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ + struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ + void *devx_channel; + }; + }; +}; + +/* HW objects operations structure. */ +struct mlx5_obj_ops { + int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); + int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); + int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); + void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); +}; + struct mlx5_priv { struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ - uint32_t ibv_port; /* IB device port number. */ + uint32_t dev_port; /* Device port number. */ struct rte_pci_device *pci_dev; /* Backend PCI device. */ struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); @@ -605,6 +728,7 @@ struct mlx5_priv { unsigned int representor:1; /* Device is a port representor. */ unsigned int master:1; /* Device is a E-Switch master. */ unsigned int dr_shared:1; /* DV/DR data is shared. */ + unsigned int txpp_en:1; /* Tx packet pacing enabled. */ unsigned int counter_fallback:1; /* Use counter fallback management. */ unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ @@ -631,6 +755,7 @@ struct mlx5_priv { void *rss_desc; /* Intermediate rss description resources. */ int flow_idx; /* Intermediate device flow index. */ int flow_nested_idx; /* Intermediate device flow index, nested. */ + struct mlx5_obj_ops *obj_ops; /* HW objects operations. */ LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ uint32_t hrxqs; /* Verbs Hash Rx queues. */ @@ -640,7 +765,6 @@ struct mlx5_priv { LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; /* Pointer to next element. */ rte_atomic32_t refcnt; /**< Reference counter. */ - struct ibv_flow_action *verbs_action; /**< Verbs modify header action object. */ uint8_t ft_type; /**< Flow table type, Rx or Tx. */ uint8_t max_lro_msg_size; @@ -653,7 +777,7 @@ struct mlx5_priv { /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ + struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_flow_id_pool *qrss_id_pool; struct mlx5_hlist *mreg_cp_tbl; @@ -662,11 +786,6 @@ struct mlx5_priv { uint8_t mtr_color_reg; /* Meter color match REG_C. */ struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ struct mlx5_flow_meters flow_meters; /* MTR list. */ -#ifndef RTE_ARCH_64 - rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ - rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; - /* UAR same-page access control required in 32bit implementations. */ -#endif uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ struct mlx5_mp_id mp_id; /* ID of a multi-process process */ @@ -680,10 +799,6 @@ struct mlx5_priv { int mlx5_getenv_int(const char *); int mlx5_proc_priv_init(struct rte_eth_dev *dev); -int64_t mlx5_get_dbr(struct rte_eth_dev *dev, - struct mlx5_devx_dbr_page **dbr_page); -int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, - uint64_t offset); int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); @@ -696,9 +811,9 @@ void mlx5_dev_close(struct rte_eth_dev *dev); port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); struct mlx5_dev_ctx_shared * -mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn, - const struct mlx5_dev_config *config); -void mlx5_free_shared_ibctx(struct mlx5_dev_ctx_shared *sh); +mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, + const struct mlx5_dev_config *config); +void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); void mlx5_free_table_hash_list(struct mlx5_priv *priv); int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, @@ -706,45 +821,50 @@ void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, void mlx5_set_metadata_mask(struct rte_eth_dev *dev); int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, struct mlx5_dev_config *config); -int mlx5_init_once(void); +int mlx5_dev_configure(struct rte_eth_dev *dev); +int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); +int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); +int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); +int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, + struct rte_eth_hairpin_cap *cap); +bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); +int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); /* mlx5_ethdev.c */ -int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); -int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); +int mlx5_dev_configure(struct rte_eth_dev *dev); +int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, + size_t fw_size); +int mlx5_dev_infos_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *info); +const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); +int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); +int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, + struct rte_eth_hairpin_cap *cap); +eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); +struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); +struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); +int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); + +/* mlx5_ethdev_os.c */ + unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); -int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); +int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); -int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, - unsigned int flags); -int mlx5_dev_configure(struct rte_eth_dev *dev); -int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); +int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); -int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); -const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); -int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); -int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); -void mlx5_dev_link_status_handler(void *arg); void mlx5_dev_interrupt_handler(void *arg); void mlx5_dev_interrupt_handler_devx(void *arg); -void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); -void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); int mlx5_set_link_down(struct rte_eth_dev *dev); int mlx5_set_link_up(struct rte_eth_dev *dev); int mlx5_is_removed(struct rte_eth_dev *dev); -eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); -eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); -struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); -struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); -void mlx5_sysfs_check_switch_info(bool device_dir, - struct mlx5_switch_info *switch_info); void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, @@ -753,18 +873,17 @@ int mlx5_get_module_info(struct rte_eth_dev *dev, struct rte_eth_dev_module_info *modinfo); int mlx5_get_module_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *info); -int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, - struct rte_eth_hairpin_cap *cap); -int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); +int mlx5_os_read_dev_stat(struct mlx5_priv *priv, + const char *ctr_name, uint64_t *stat); +int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); +int mlx5_os_get_stats_n(struct rte_eth_dev *dev); +void mlx5_os_stats_init(struct rte_eth_dev *dev); /* mlx5_mac.c */ -int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, uint32_t index, uint32_t vmdq); -struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init - (struct rte_eth_dev *dev, uint32_t ifindex); int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *mc_addr_set, @@ -793,7 +912,6 @@ int mlx5_allmulticast_disable(struct rte_eth_dev *dev); /* mlx5_stats.c */ -void mlx5_stats_init(struct rte_eth_dev *dev); int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); int mlx5_stats_reset(struct rte_eth_dev *dev); int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, @@ -808,11 +926,15 @@ int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); -void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); + +/* mlx5_vlan_os.c */ + +void mlx5_vlan_vmwa_exit(void *ctx); void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, struct mlx5_vf_vlan *vf_vlan); void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, struct mlx5_vf_vlan *vf_vlan); +void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); /* mlx5_trigger.c */ @@ -826,7 +948,6 @@ int mlx5_traffic_restart(struct rte_eth_dev *dev); int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); -int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); void mlx5_flow_print(struct rte_flow *flow); int mlx5_flow_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -867,6 +988,7 @@ int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, int mlx5_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow_item_eth *eth_spec, struct rte_flow_item_eth *eth_mask); +int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); @@ -884,11 +1006,16 @@ void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, uint32_t nb_contexts, struct rte_flow_error *error); -/* mlx5_mp.c */ -int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer); -int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer); -void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); -void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); +/* mlx5_mp_os.c */ + +int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, + const void *peer); +int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, + const void *peer); +void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); +void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); +int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, + enum mlx5_mp_req_type req_type); /* mlx5_socket.c */ @@ -908,9 +1035,6 @@ void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); /* mlx5_os.c */ struct rte_pci_driver; -const char *mlx5_os_get_ctx_device_name(void *ctx); -const char *mlx5_os_get_ctx_device_path(void *ctx); -uint32_t mlx5_os_get_umem_id(void *umem); int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); void mlx5_os_free_shared_dr(struct mlx5_priv *priv); int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, @@ -921,4 +1045,35 @@ int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); +void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, + mlx5_dereg_mr_t *dereg_mr_cb); +void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); +int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, + uint32_t index); +int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, + struct rte_ether_addr *mac_addr, + int vf_index); +int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); +int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); +int mlx5_os_set_nonblock_channel_fd(int fd); +void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); + +/* mlx5_txpp.c */ + +int mlx5_txpp_start(struct rte_eth_dev *dev); +void mlx5_txpp_stop(struct rte_eth_dev *dev); +int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); +int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *stats, + unsigned int n, unsigned int n_used); +int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); +int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + unsigned int n, unsigned int n_used); +void mlx5_txpp_interrupt_handler(void *cb_arg); + +/* mlx5_rxtx.c */ + +eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); + #endif /* RTE_PMD_MLX5_H_ */