X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=5196a9ea76b276181691cbde595266eb7aa11a23;hb=641dbe4fb053cbf300bceb991afaee5207ad90d9;hp=2fbeb9112d57f1b46d3742cf4c7db1d65c12eb82;hpb=f1ae0b3590964c0e9931c20dd0a03cb1ab92e771;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 2fbeb9112d..5196a9ea76 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include #include @@ -26,6 +26,7 @@ #include #include #include +#include #include "mlx5_defs.h" #include "mlx5_utils.h" @@ -140,9 +141,9 @@ struct mlx5_local_data { extern struct mlx5_shared_data *mlx5_shared_data; /* Dev ops structs */ -extern const struct eth_dev_ops mlx5_os_dev_ops; -extern const struct eth_dev_ops mlx5_os_dev_sec_ops; -extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; +extern const struct eth_dev_ops mlx5_dev_ops; +extern const struct eth_dev_ops mlx5_dev_sec_ops; +extern const struct eth_dev_ops mlx5_dev_ops_isolate; struct mlx5_counter_ctrl { /* Name of the counter. */ @@ -212,7 +213,6 @@ struct mlx5_dev_config { unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ unsigned int cqe_comp:1; /* CQE compression is enabled. */ unsigned int cqe_comp_fmt:3; /* CQE compression format. */ - unsigned int cqe_pad:1; /* CQE padding is enabled. */ unsigned int tso:1; /* Whether TSO is supported. */ unsigned int rx_vec_en:1; /* Rx vector is enabled. */ unsigned int mr_ext_memseg_en:1; @@ -467,13 +467,7 @@ struct mlx5_flow_counter_mng { struct mlx5_aso_cq { uint16_t log_desc_n; uint32_t cq_ci:24; - struct mlx5_devx_obj *cq; - struct mlx5dv_devx_umem *umem_obj; - union { - volatile void *umem_buf; - volatile struct mlx5_cqe *cqes; - }; - volatile uint32_t *db_rec; + struct mlx5_devx_cq cq_obj; uint64_t errors; }; @@ -493,13 +487,7 @@ struct mlx5_aso_sq_elem { struct mlx5_aso_sq { uint16_t log_desc_n; struct mlx5_aso_cq cq; - struct mlx5_devx_obj *sq; - struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */ - union { - volatile void *umem_buf; - volatile struct mlx5_aso_wqe *wqes; - }; - volatile uint32_t *db_rec; + struct mlx5_devx_sq sq_obj; volatile uint64_t *uar_addr; struct mlx5_aso_devx_mr mr; uint16_t pi; @@ -540,6 +528,16 @@ struct mlx5_aso_age_mng { struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ }; +/* Management structure for geneve tlv option */ +struct mlx5_geneve_tlv_option_resource { + struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ + rte_be16_t option_class; /* geneve tlv opt class.*/ + uint8_t option_type; /* geneve tlv opt type.*/ + uint8_t length; /* geneve tlv opt length. */ + uint32_t refcnt; /* geneve tlv object reference counter */ +}; + + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ @@ -617,25 +615,13 @@ struct mlx5_flow_id_pool { /* Tx pacing queue structure - for Clock and Rearm queues. */ struct mlx5_txpp_wq { /* Completion Queue related data.*/ - struct mlx5_devx_obj *cq; - void *cq_umem; - union { - volatile void *cq_buf; - volatile struct mlx5_cqe *cqes; - }; - volatile uint32_t *cq_dbrec; + struct mlx5_devx_cq cq_obj; uint32_t cq_ci:24; uint32_t arm_sn:2; /* Send Queue related data.*/ - struct mlx5_devx_obj *sq; - void *sq_umem; - union { - volatile void *sq_buf; - volatile struct mlx5_wqe *wqes; - }; + struct mlx5_devx_sq sq_obj; uint16_t sq_size; /* Number of WQEs in the queue. */ uint16_t sq_ci; /* Next WQE to execute. */ - volatile uint32_t *sq_dbrec; }; /* Tx packet pacing internal timestamp. */ @@ -695,7 +681,6 @@ struct mlx5_dev_ctx_shared { uint16_t bond_dev; /* Bond primary device id. */ uint32_t devx:1; /* Opened with DV. */ uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ - uint32_t eqn; /* Event Queue number. */ uint32_t max_port; /* Maximal IB device port index. */ void *ctx; /* Verbs/DV/DevX context. */ void *pd; /* Protection Domain. */ @@ -752,10 +737,16 @@ struct mlx5_dev_ctx_shared { void *devx_rx_uar; /* DevX UAR for Rx. */ struct mlx5_aso_age_mng *aso_age_mng; /* Management data for aging mechanism using ASO Flow Hit. */ + struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; + /* Management structure for geneve tlv option */ + rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; -/* Per-process private structure. */ +/* + * Per-process private structure. + * Caution, secondary process may rebuild the struct during port start. + */ struct mlx5_proc_priv { size_t uar_table_sz; /* Size of UAR register table. */ @@ -801,9 +792,10 @@ struct mlx5_rxq_obj { void *ibv_cq; /* Completion Queue. */ void *ibv_channel; }; + struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ struct { - struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ - struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ + struct mlx5_devx_rq rq_obj; /* DevX RQ object. */ + struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ void *devx_channel; }; }; @@ -859,16 +851,10 @@ struct mlx5_txq_obj { }; struct { struct rte_eth_dev *dev; - struct mlx5_devx_obj *cq_devx; - void *cq_umem; - void *cq_buf; - int64_t cq_dbrec_offset; - struct mlx5_devx_dbr_page *cq_dbrec_page; - struct mlx5_devx_obj *sq_devx; - void *sq_umem; - void *sq_buf; - int64_t sq_dbrec_offset; - struct mlx5_devx_dbr_page *sq_dbrec_page; + struct mlx5_devx_cq cq_obj; + /* DevX CQ object and its resources. */ + struct mlx5_devx_sq sq_obj; + /* DevX SQ object and its resources. */ }; }; }; @@ -950,7 +936,7 @@ struct mlx5_priv { int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ unsigned int if_index; /* Associated kernel network device index. */ uint32_t bond_ifindex; /**< Bond interface index. */ - char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ + char bond_name[MLX5_NAMESIZE]; /**< Bond interface name. */ /* RX/TX queues. */ unsigned int rxqs_n; /* RX queues array size. */ unsigned int txqs_n; /* TX queues array size. */ @@ -985,7 +971,6 @@ struct mlx5_priv { /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_hlist *mreg_cp_tbl; /* Hash table of Rx metadata register copy table. */ @@ -1016,6 +1001,7 @@ struct rte_hairpin_peer_info { int mlx5_getenv_int(const char *); int mlx5_proc_priv_init(struct rte_eth_dev *dev); +void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); @@ -1067,6 +1053,8 @@ int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); /* mlx5_ethdev_os.c */ +int mlx5_get_ifname(const struct rte_eth_dev *dev, + char (*ifname)[MLX5_NAMESIZE]); unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);