X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=5b5fdff6ee87bdc1ee7a64b8879dc42961835cd1;hb=f6ac14f13b040fb44db6ed4ab392865fb6648201;hp=872fccb97115cdfa81e98238769bc44d68d175ba;hpb=7b4f1e6bd367855716d84e95a1dd85ac3647a4c8;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 872fccb971..5b5fdff6ee 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -35,33 +35,13 @@ #include #include #include +#include #include "mlx5_defs.h" #include "mlx5_utils.h" #include "mlx5_mr.h" #include "mlx5_autoconf.h" -enum { - PCI_VENDOR_ID_MELLANOX = 0x15b3, -}; - -enum { - PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, - PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, - PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, - PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, - PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, - PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, - PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, - PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, - PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, - PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, - PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, - PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, - PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, - PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, -}; - /* Request types for IPC. */ enum mlx5_mp_req_type { MLX5_MP_REQ_VERBS_CMD_FD = 1, @@ -96,24 +76,6 @@ struct mlx5_mp_param { /** Key string for IPC. */ #define MLX5_MP_NAME "net_mlx5_mp" -/* Recognized Infiniband device physical port name types. */ -enum mlx5_phys_port_name_type { - MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ - MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ - MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ -}; - -/** Switch information returned by mlx5_nl_switch_info(). */ -struct mlx5_switch_info { - uint32_t master:1; /**< Master device. */ - uint32_t representor:1; /**< Representor device. */ - enum mlx5_phys_port_name_type name_type; /** < Port name type. */ - int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ - int32_t port_name; /**< Representor port name. */ - uint64_t switch_id; /**< Switch identifier. */ -}; LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); @@ -150,12 +112,15 @@ struct mlx5_xstats_ctrl { /* Index in the device counters table. */ uint16_t dev_table_idx[MLX5_MAX_XSTATS]; uint64_t base[MLX5_MAX_XSTATS]; + uint64_t xstats[MLX5_MAX_XSTATS]; + uint64_t hw_stats[MLX5_MAX_XSTATS]; struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; }; struct mlx5_stats_ctrl { /* Base for imissed counter. */ uint64_t imissed_base; + uint64_t imissed; }; /* Flow list . */ @@ -229,6 +194,7 @@ struct mlx5_dev_config { unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ unsigned int ind_table_max_size; /* Maximum indirection table size. */ unsigned int max_dump_files_num; /* Maximum dump files per queue. */ + unsigned int log_hp_size; /* Single hairpin queue data size in total. */ int txqs_inline; /* Queue number threshold for inlining. */ int txq_inline_min; /* Minimal amount of data bytes to inline. */ int txq_inline_max; /* Max packet size for inlining with SEND. */ @@ -247,30 +213,12 @@ enum mlx5_verbs_alloc_type { MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, }; -/* VLAN netdev for VLAN workaround. */ -struct mlx5_vlan_dev { - uint32_t refcnt; - uint32_t ifindex; /**< Own interface index. */ -}; - /* Structure for VF VLAN workaround. */ struct mlx5_vf_vlan { uint32_t tag:12; uint32_t created:1; }; -/* - * Array of VLAN devices created on the base of VF - * used for workaround in virtual environments. - */ -struct mlx5_vlan_vmwa_context { - int nl_socket; - uint32_t nl_sn; - uint32_t vf_ifindex; - struct rte_eth_dev *dev; - struct mlx5_vlan_dev vlan_dev[4096]; -}; - /** * Verbs allocator needs a context to know in the callback which kind of * resources it is allocating. @@ -290,6 +238,20 @@ struct mlx5_drop { #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 +#define MLX5_CNT_CONTAINER_RESIZE 64 +/* + * The pool index and offset of counter in the pool array makes up the + * counter index. In case the counter is from pool 0 and offset 0, it + * should plus 1 to avoid index 0, since 0 means invalid counter index + * currently. + */ +#define MLX5_MAKE_CNT_IDX(pi, offset) \ + ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) +#define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \ + ((pool) + 1))[((cnt) - (pool)->counters_raw)]) +#define MLX5_GET_POOL_CNT_EXT(pool, offset) \ + (&((struct mlx5_flow_counter_ext *) \ + ((pool) + 1))[offset]) struct mlx5_flow_counter_pool; @@ -298,15 +260,25 @@ struct flow_counter_stats { uint64_t bytes; }; -/* Counters information. */ +/* Generic counters information. */ struct mlx5_flow_counter { TAILQ_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next flow counter structure. */ + union { + uint64_t hits; /**< Reset value of hits packets. */ + int64_t query_gen; /**< Generation of the last release. */ + }; + uint64_t bytes; /**< Reset value of bytes. */ + void *action; /**< Pointer to the dv action. */ +}; + +/* Extend counters information for none batch counters. */ +struct mlx5_flow_counter_ext { uint32_t shared:1; /**< Share counter ID with other flow rules. */ uint32_t batch: 1; /**< Whether the counter was allocated by batch command. */ uint32_t ref_cnt:30; /**< Reference counter. */ - uint32_t id; /**< Counter ID. */ + uint32_t id; /**< User counter ID. */ union { /**< Holds the counters for the rule. */ #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) struct ibv_counter_set *cs; @@ -314,19 +286,13 @@ struct mlx5_flow_counter { struct ibv_counters *cs; #endif struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ - struct mlx5_flow_counter_pool *pool; /**< The counter pool. */ - }; - union { - uint64_t hits; /**< Reset value of hits packets. */ - int64_t query_gen; /**< Generation of the last release. */ }; - uint64_t bytes; /**< Reset value of bytes. */ - void *action; /**< Pointer to the dv action. */ }; + TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); -/* Counter pool structure - query is in pool resolution. */ +/* Generic counter pool structure - query is in pool resolution. */ struct mlx5_flow_counter_pool { TAILQ_ENTRY(mlx5_flow_counter_pool) next; struct mlx5_counters counters; /* Free counter list. */ @@ -335,12 +301,14 @@ struct mlx5_flow_counter_pool { rte_atomic64_t a64_dcs; }; /* The devx object of the minimum counter ID. */ - rte_atomic64_t query_gen; - uint32_t n_counters: 16; /* Number of devx allocated counters. */ + rte_atomic64_t start_query_gen; /* Query start round. */ + rte_atomic64_t end_query_gen; /* Query end round. */ + uint32_t index; /* Pool index in container. */ rte_spinlock_t sl; /* The pool lock. */ struct mlx5_counter_stats_raw *raw; struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ - struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */ + struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL]; + /* The pool counters memory. */ }; struct mlx5_counter_stats_raw; @@ -573,6 +541,8 @@ struct mlx5_priv { struct mlx5_drop drop_queue; /* Flow drop queues. */ struct mlx5_flows flows; /* RTE Flow rules. */ struct mlx5_flows ctrl_flows; /* Control flow rules. */ + void *inter_flows; /* Intermediate resources for flow creation. */ + int flow_idx; /* Intermediate device flow index. */ LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ @@ -595,9 +565,8 @@ struct mlx5_priv { /* Context for Verbs allocator. */ int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ - uint32_t nl_sn; /* Netlink message sequence number. */ LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ - struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ + struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ struct mlx5_flow_id_pool *qrss_id_pool; struct mlx5_hlist *mreg_cp_tbl; /* Hash table of Rx metadata register copy table. */ @@ -611,6 +580,7 @@ struct mlx5_priv { /* UAR same-page access control required in 32bit implementations. */ #endif uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ + uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id) @@ -655,8 +625,6 @@ int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); -int mlx5_dev_to_pci_addr(const char *dev_path, - struct rte_pci_addr *pci_addr); void mlx5_dev_link_status_handler(void *arg); void mlx5_dev_interrupt_handler(void *arg); void mlx5_dev_interrupt_handler_devx(void *arg); @@ -675,8 +643,6 @@ int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); void mlx5_sysfs_check_switch_info(bool device_dir, struct mlx5_switch_info *switch_info); -void mlx5_nl_check_switch_info(bool nun_vf_set, - struct mlx5_switch_info *switch_info); void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, @@ -695,6 +661,8 @@ int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, uint32_t index, uint32_t vmdq); +struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init + (struct rte_eth_dev *dev, uint32_t ifindex); int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *mc_addr_set, @@ -738,6 +706,11 @@ int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); +void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); +void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vf_vlan); +void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vf_vlan); /* mlx5_trigger.c */ @@ -765,7 +738,8 @@ struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, struct rte_flow_error *error); -void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); +void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list, + bool active); int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, const struct rte_flow_action *action, void *data, @@ -778,6 +752,10 @@ int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, void *arg); int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); +int mlx5_flow_start_default(struct rte_eth_dev *dev); +void mlx5_flow_stop_default(struct rte_eth_dev *dev); +void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev); +void mlx5_flow_free_intermediate(struct rte_eth_dev *dev); int mlx5_flow_verify(struct rte_eth_dev *dev); int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, @@ -795,9 +773,9 @@ void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, uint64_t async_id, int status); void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh); void mlx5_flow_query_alarm(void *arg); -struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev); -void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt); -int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt, +uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); +void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); +int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, bool clear, uint64_t *pkts, uint64_t *bytes); int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, struct rte_flow_error *error); @@ -817,33 +795,6 @@ void mlx5_mp_uninit_secondary(void); /* mlx5_socket.c */ int mlx5_pmd_socket_init(void); -void mlx5_pmd_socket_uninit(void); - -/* mlx5_nl.c */ - -int mlx5_nl_init(int protocol); -int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, - uint32_t index); -int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac, - uint32_t index); -void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); -void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); -int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); -int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); -unsigned int mlx5_nl_portnum(int nl, const char *name); -unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); -int mlx5_nl_vf_mac_addr_modify(struct rte_eth_dev *dev, - struct rte_ether_addr *mac, int vf_index); -int mlx5_nl_switch_info(int nl, unsigned int ifindex, - struct mlx5_switch_info *info); - -struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, - uint32_t ifindex); -void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx); -void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, - struct mlx5_vf_vlan *vf_vlan); -void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, - struct mlx5_vf_vlan *vf_vlan); /* mlx5_flow_meter.c */