X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=721edab929057b18685f4aede66a39a49eaff352;hb=bd885ab120e2335f978a28ee0aa4303017390e15;hp=867975003295686d4429199d306177ba1a2e36e0;hpb=86d259cec852ef8735bd1fc459d328e607d7d7e8;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8679750032..721edab929 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -39,6 +39,8 @@ enum mlx5_ipool_index { MLX5_IPOOL_TAG, /* Pool for tag resource. */ MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ MLX5_IPOOL_JUMP, /* Pool for jump resource. */ + MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ + MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ #endif MLX5_IPOOL_MTR, /* Pool for meter resource. */ MLX5_IPOOL_MCP, /* Pool for metadata resource. */ @@ -162,6 +164,9 @@ struct mlx5_stats_ctrl { /* Maximal size of aggregated LRO packet. */ #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) +/* Maximal number of segments to split. */ +#define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) + /* LRO configurations structure. */ struct mlx5_lro_config { uint32_t supported:1; /* Whether LRO is supported. */ @@ -206,6 +211,7 @@ struct mlx5_dev_config { unsigned int rt_timestamp:1; /* realtime timestamp format. */ unsigned int sys_mem_en:1; /* The default memory allocator. */ unsigned int decap_en:1; /* Whether decap will be used or not. */ + unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ @@ -270,20 +276,16 @@ struct mlx5_drop { #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 #define MLX5_CNT_CONTAINER_RESIZE 64 -#define MLX5_CNT_AGE_OFFSET 0x80000000 -#define CNT_SIZE (sizeof(struct mlx5_flow_counter)) -#define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext)) -#define AGE_SIZE (sizeof(struct mlx5_age_param)) -#define MLX5_AGING_TIME_DELAY 7 -#define CNT_POOL_TYPE_EXT (1 << 0) -#define CNT_POOL_TYPE_AGE (1 << 1) -#define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT) -#define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE) -#define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0) +#define MLX5_CNT_SHARED_OFFSET 0x80000000 +#define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) +#define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ + MLX5_CNT_BATCH_OFFSET) +#define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) +#define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) + #define MLX5_CNT_LEN(pool) \ - (CNT_SIZE + \ - (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \ - (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0)) + (MLX5_CNT_SIZE + \ + ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) #define MLX5_POOL_GET_CNT(pool, index) \ ((struct mlx5_flow_counter *) \ ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) @@ -298,12 +300,6 @@ struct mlx5_drop { */ #define MLX5_MAKE_CNT_IDX(pi, offset) \ ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) -#define MLX5_CNT_TO_CNT_EXT(pool, cnt) \ - ((struct mlx5_flow_counter_ext *)\ - ((uint8_t *)((cnt) + 1) + \ - (IS_AGE_POOL(pool) ? AGE_SIZE : 0))) -#define MLX5_GET_POOL_CNT_EXT(pool, offset) \ - MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) #define MLX5_CNT_TO_AGE(cnt) \ ((struct mlx5_age_param *)((cnt) + 1)) /* @@ -313,32 +309,26 @@ struct mlx5_drop { */ #define POOL_IDX_INVALID UINT16_MAX -struct mlx5_flow_counter_pool; - -/*age status*/ +/* Age status. */ enum { AGE_FREE, /* Initialized state. */ AGE_CANDIDATE, /* Counter assigned to flows. */ AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ }; -#define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \ - [(batch) * 2 + (age)]) - -enum { - MLX5_CCONT_TYPE_SINGLE, - MLX5_CCONT_TYPE_SINGLE_FOR_AGE, - MLX5_CCONT_TYPE_BATCH, - MLX5_CCONT_TYPE_BATCH_FOR_AGE, - MLX5_CCONT_TYPE_MAX, +enum mlx5_counter_type { + MLX5_COUNTER_TYPE_ORIGIN, + MLX5_COUNTER_TYPE_AGE, + MLX5_COUNTER_TYPE_MAX, }; /* Counter age parameter. */ struct mlx5_age_param { - rte_atomic16_t state; /**< Age state. */ + uint16_t state; /**< Age state (atomically accessed). */ uint16_t port_id; /**< Port id of the counter. */ - uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */ - uint32_t expire:16; /**< Expire time(0.1sec) in the future. */ + uint32_t timeout:24; /**< Aging timeout in seconds. */ + uint32_t sec_since_last_hit; + /**< Time in seconds since last hit (atomically accessed). */ void *context; /**< Flow counter age context. */ }; @@ -347,35 +337,63 @@ struct flow_counter_stats { uint64_t bytes; }; +/* Shared counters information for counters. */ +struct mlx5_flow_counter_shared { + uint32_t id; /**< User counter ID. */ +}; + +/* Shared counter configuration. */ +struct mlx5_shared_counter_conf { + struct rte_eth_dev *dev; /* The device shared counter belongs to. */ + uint32_t id; /* The shared counter ID. */ +}; + struct mlx5_flow_counter_pool; /* Generic counters information. */ struct mlx5_flow_counter { - TAILQ_ENTRY(mlx5_flow_counter) next; - /**< Pointer to the next flow counter structure. */ + union { + /* + * User-defined counter shared info is only used during + * counter active time. And aging counter sharing is not + * supported, so active shared counter will not be chained + * to the aging list. For shared counter, only when it is + * released, the TAILQ entry memory will be used, at that + * time, shared memory is not used anymore. + * + * Similarly to none-batch counter dcs, since it doesn't + * support aging, while counter is allocated, the entry + * memory is not used anymore. In this case, as bytes + * memory is used only when counter is allocated, and + * entry memory is used only when counter is free. The + * dcs pointer can be saved to these two different place + * at different stage. It will eliminate the individual + * counter extend struct. + */ + TAILQ_ENTRY(mlx5_flow_counter) next; + /**< Pointer to the next flow counter structure. */ + struct { + struct mlx5_flow_counter_shared shared_info; + /**< Shared counter information. */ + void *dcs_when_active; + /* + * For non-batch mode, the dcs will be saved + * here when the counter is free. + */ + }; + }; union { uint64_t hits; /**< Reset value of hits packets. */ struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ }; - uint64_t bytes; /**< Reset value of bytes. */ - void *action; /**< Pointer to the dv action. */ -}; - -/* Extend counters information for none batch counters. */ -struct mlx5_flow_counter_ext { - uint32_t shared:1; /**< Share counter ID with other flow rules. */ - uint32_t batch: 1; - uint32_t skipped:1; /* This counter is skipped or not. */ - /**< Whether the counter was allocated by batch command. */ - uint32_t ref_cnt:29; /**< Reference counter. */ - uint32_t id; /**< User counter ID. */ - union { /**< Holds the counters for the rule. */ -#if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) - struct ibv_counter_set *cs; -#elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) - struct ibv_counters *cs; -#endif - struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ + union { + uint64_t bytes; /**< Reset value of bytes. */ + void *dcs_when_free; + /* + * For non-batch mode, the dcs will be saved here + * when the counter is free. + */ }; + void *action; /**< Pointer to the dv action. */ }; TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); @@ -389,17 +407,18 @@ struct mlx5_flow_counter_pool { rte_atomic64_t a64_dcs; }; /* The devx object of the minimum counter ID. */ - uint32_t index:28; /* Pool index in container. */ - uint32_t type:2; /* Memory type behind the counter array. */ - uint32_t skip_cnt:1; /* Pool contains skipped counter. */ + uint64_t time_of_last_age_check; + /* System time (from rte_rdtsc()) read in the last aging check. */ + uint32_t index:30; /* Pool index in container. */ + uint32_t is_aged:1; /* Pool with aging counter. */ volatile uint32_t query_gen:1; /* Query round. */ rte_spinlock_t sl; /* The pool lock. */ + rte_spinlock_t csl; /* The pool counter free list lock. */ struct mlx5_counter_stats_raw *raw; - struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ + struct mlx5_counter_stats_raw *raw_hw; + /* The raw on HW working. */ }; -struct mlx5_counter_stats_raw; - /* Memory management structure for group of counter statistics raws. */ struct mlx5_counter_stats_mem_mng { LIST_ENTRY(mlx5_counter_stats_mem_mng) next; @@ -411,38 +430,33 @@ struct mlx5_counter_stats_mem_mng { /* Raw memory structure for the counter statistics values of a pool. */ struct mlx5_counter_stats_raw { LIST_ENTRY(mlx5_counter_stats_raw) next; - int min_dcs_id; struct mlx5_counter_stats_mem_mng *mem_mng; volatile struct flow_counter_stats *data; }; TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); -/* Container structure for counter pools. */ -struct mlx5_pools_container { - rte_atomic16_t n_valid; /* Number of valid pools. */ +/* Counter global management structure. */ +struct mlx5_flow_counter_mng { + volatile uint16_t n_valid; /* Number of valid pools. */ uint16_t n; /* Number of pools. */ uint16_t last_pool_idx; /* Last used pool index */ int min_id; /* The minimum counter ID in the pools. */ int max_id; /* The maximum counter ID in the pools. */ - rte_spinlock_t resize_sl; /* The resize lock. */ - rte_spinlock_t csl; /* The counter free list lock. */ - struct mlx5_counters counters; /* Free counter list. */ - struct mlx5_counter_pools pool_list; /* Counter pool list. */ + rte_spinlock_t pool_update_sl; /* The pool update lock. */ + rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; + /* The counter free list lock. */ + struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; + /* Free counter list. */ struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ struct mlx5_counter_stats_mem_mng *mem_mng; /* Hold the memory management for the next allocated pools raws. */ -}; - -/* Counter global management structure. */ -struct mlx5_flow_counter_mng { - struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX]; struct mlx5_counters flow_counters; /* Legacy flow counter list. */ uint8_t pending_queries; - uint8_t batch; uint16_t pool_index; - uint8_t age; uint8_t query_thread_on; + bool relaxed_ordering; + bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; @@ -461,10 +475,12 @@ struct mlx5_flow_default_miss_resource { ((age_info)->flags & (1 << (BIT))) #define GET_PORT_AGE_INFO(priv) \ (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) +/* Current time in seconds. */ +#define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) /* Aging information for per port. */ struct mlx5_age_info { - uint8_t flags; /*Indicate if is new event or need be trigered*/ + uint8_t flags; /* Indicate if is new event or need to be triggered. */ struct mlx5_counters aged_counters; /* Aged flow counter list. */ rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ }; @@ -512,6 +528,7 @@ struct mlx5_flow_tbl_resource { #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) #define MLX5_MAX_TABLES_FDB UINT16_MAX +#define MLX5_FLOW_TABLE_FACTOR 10 /* ID generation structure. */ struct mlx5_flow_id_pool { @@ -622,7 +639,6 @@ struct mlx5_dev_ctx_shared { uint32_t dv_meta_mask; /* flow META metadata supported mask. */ uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ - uint32_t dv_refcnt; /* DV/DR data reference counter. */ void *fdb_domain; /* FDB Direct Rules name space handle. */ void *rx_domain; /* RX Direct Rules name space handle. */ void *tx_domain; /* TX Direct Rules name space handle. */ @@ -632,6 +648,7 @@ struct mlx5_dev_ctx_shared { /* UAR same-page access control required in 32bit implementations. */ #endif struct mlx5_hlist *flow_tbls; + struct mlx5_flow_tunnel_hub *tunnel_hub; /* Direct Rules tables for FDB, NIC TX+RX */ void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ @@ -640,6 +657,8 @@ struct mlx5_dev_ctx_shared { struct mlx5_hlist *tag_table; uint32_t port_id_action_list; /* List of port ID actions. */ uint32_t push_vlan_action_list; /* List of push VLAN actions. */ + uint32_t sample_action_list; /* List of sample actions. */ + uint32_t dest_array_list; /* List of destination array actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ struct mlx5_flow_default_miss_resource default_miss; /* Default miss action resource structure. */ @@ -676,18 +695,10 @@ TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); #define MLX5_PROC_PRIV(port_id) \ ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) -enum mlx5_rxq_obj_type { - MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */ - MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */ - MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN, - /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */ -}; - /* Verbs/DevX Rx queue elements. */ struct mlx5_rxq_obj { LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ - enum mlx5_rxq_obj_type type; int fd; /* File descriptor for event channel */ RTE_STD_C11 union { @@ -718,9 +729,11 @@ struct mlx5_ind_table_obj { }; /* Hash Rx queue. */ +__extension__ struct mlx5_hrxq { ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t shared:1; /* This object used in shared action. */ struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ RTE_STD_C11 union { @@ -735,18 +748,10 @@ struct mlx5_hrxq { uint8_t rss_key[]; /* Hash key. */ }; -enum mlx5_txq_obj_type { - MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */ - MLX5_TXQ_OBJ_TYPE_DEVX_SQ, /* mlx5_txq_obj with mlx5_devx_sq. */ - MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN, - /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */ -}; - /* Verbs/DevX Tx queue elements. */ struct mlx5_txq_obj { LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ - enum mlx5_txq_obj_type type; /* The txq object type. */ RTE_STD_C11 union { struct { @@ -774,23 +779,42 @@ struct mlx5_txq_obj { }; }; +enum mlx5_rxq_modify_type { + MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ + MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ + MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ + MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ +}; + +enum mlx5_txq_modify_type { + MLX5_TXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ + MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ + MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ +}; + /* HW objects operations structure. */ struct mlx5_obj_ops { int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); - int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, bool is_start); + int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, struct mlx5_ind_table_obj *ind_tbl); void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, int tunnel __rte_unused); + int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, + const uint8_t *rss_key, + uint64_t hash_fields, + const struct mlx5_ind_table_obj *ind_tbl); void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); int (*drop_action_create)(struct rte_eth_dev *dev); void (*drop_action_destroy)(struct rte_eth_dev *dev); - struct mlx5_txq_obj *(*txq_obj_new)(struct rte_eth_dev *dev, - uint16_t idx); + int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); + int (*txq_obj_modify)(struct mlx5_txq_obj *obj, + enum mlx5_txq_modify_type type, uint8_t dev_port); void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); }; @@ -809,11 +833,10 @@ struct mlx5_priv { unsigned int isolated:1; /* Whether isolated mode is enabled. */ unsigned int representor:1; /* Device is a port representor. */ unsigned int master:1; /* Device is a E-Switch master. */ - unsigned int dr_shared:1; /* DV/DR data is shared. */ unsigned int txpp_en:1; /* Tx packet pacing enabled. */ - unsigned int counter_fallback:1; /* Use counter fallback management. */ unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ + unsigned int sampler_en:1; /* Whether support sampler. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ @@ -874,6 +897,8 @@ struct mlx5_priv { uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ struct mlx5_mp_id mp_id; /* ID of a multi-process process */ LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ + LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions; + /* shared actions */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id) @@ -1025,7 +1050,7 @@ void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); /* mlx5_trigger.c */ int mlx5_dev_start(struct rte_eth_dev *dev); -void mlx5_dev_stop(struct rte_eth_dev *dev); +int mlx5_dev_stop(struct rte_eth_dev *dev); int mlx5_traffic_enable(struct rte_eth_dev *dev); void mlx5_traffic_disable(struct rte_eth_dev *dev); int mlx5_traffic_restart(struct rte_eth_dev *dev);