X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=721edab929057b18685f4aede66a39a49eaff352;hb=bd885ab120e2335f978a28ee0aa4303017390e15;hp=e3ac07fbed62961a84da77488dc9c71a83ef4ff6;hpb=df051a3e77c3cfa7277a71a6be2e1aa314a51ac3;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index e3ac07fbed..721edab929 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -164,6 +164,9 @@ struct mlx5_stats_ctrl { /* Maximal size of aggregated LRO packet. */ #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) +/* Maximal number of segments to split. */ +#define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) + /* LRO configurations structure. */ struct mlx5_lro_config { uint32_t supported:1; /* Whether LRO is supported. */ @@ -208,6 +211,7 @@ struct mlx5_dev_config { unsigned int rt_timestamp:1; /* realtime timestamp format. */ unsigned int sys_mem_en:1; /* The default memory allocator. */ unsigned int decap_en:1; /* Whether decap will be used or not. */ + unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ @@ -276,17 +280,12 @@ struct mlx5_drop { #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ MLX5_CNT_BATCH_OFFSET) -#define CNT_SIZE (sizeof(struct mlx5_flow_counter)) -#define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext)) -#define AGE_SIZE (sizeof(struct mlx5_age_param)) -#define CNT_POOL_TYPE_EXT (1 << 0) -#define CNT_POOL_TYPE_AGE (1 << 1) -#define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT) -#define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE) +#define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) +#define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) + #define MLX5_CNT_LEN(pool) \ - (CNT_SIZE + \ - (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \ - (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0)) + (MLX5_CNT_SIZE + \ + ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) #define MLX5_POOL_GET_CNT(pool, index) \ ((struct mlx5_flow_counter *) \ ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) @@ -301,12 +300,6 @@ struct mlx5_drop { */ #define MLX5_MAKE_CNT_IDX(pi, offset) \ ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) -#define MLX5_CNT_TO_CNT_EXT(pool, cnt) \ - ((struct mlx5_flow_counter_ext *)\ - ((uint8_t *)((cnt) + 1) + \ - (IS_AGE_POOL(pool) ? AGE_SIZE : 0))) -#define MLX5_GET_POOL_CNT_EXT(pool, offset) \ - MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) #define MLX5_CNT_TO_AGE(cnt) \ ((struct mlx5_age_param *)((cnt) + 1)) /* @@ -323,14 +316,6 @@ enum { AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ }; -#define MLX5_CNT_CONTAINER(sh, batch) (&(sh)->cmng.ccont[batch]) - -enum { - MLX5_CCONT_TYPE_SINGLE, - MLX5_CCONT_TYPE_BATCH, - MLX5_CCONT_TYPE_MAX, -}; - enum mlx5_counter_type { MLX5_COUNTER_TYPE_ORIGIN, MLX5_COUNTER_TYPE_AGE, @@ -354,10 +339,15 @@ struct flow_counter_stats { /* Shared counters information for counters. */ struct mlx5_flow_counter_shared { - uint32_t ref_cnt; /**< Reference counter. */ uint32_t id; /**< User counter ID. */ }; +/* Shared counter configuration. */ +struct mlx5_shared_counter_conf { + struct rte_eth_dev *dev; /* The device shared counter belongs to. */ + uint32_t id; /* The shared counter ID. */ +}; + struct mlx5_flow_counter_pool; /* Generic counters information. */ struct mlx5_flow_counter { @@ -369,31 +359,41 @@ struct mlx5_flow_counter { * to the aging list. For shared counter, only when it is * released, the TAILQ entry memory will be used, at that * time, shared memory is not used anymore. + * + * Similarly to none-batch counter dcs, since it doesn't + * support aging, while counter is allocated, the entry + * memory is not used anymore. In this case, as bytes + * memory is used only when counter is allocated, and + * entry memory is used only when counter is free. The + * dcs pointer can be saved to these two different place + * at different stage. It will eliminate the individual + * counter extend struct. */ TAILQ_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next flow counter structure. */ - struct mlx5_flow_counter_shared shared_info; - /**< Shared counter information. */ + struct { + struct mlx5_flow_counter_shared shared_info; + /**< Shared counter information. */ + void *dcs_when_active; + /* + * For non-batch mode, the dcs will be saved + * here when the counter is free. + */ + }; }; union { uint64_t hits; /**< Reset value of hits packets. */ struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ }; - uint64_t bytes; /**< Reset value of bytes. */ - void *action; /**< Pointer to the dv action. */ -}; - -/* Extend counters information for none batch fallback counters. */ -struct mlx5_flow_counter_ext { - uint32_t skipped:1; /* This counter is skipped or not. */ union { -#if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) - struct ibv_counter_set *cs; -#elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) - struct ibv_counters *cs; -#endif - struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ + uint64_t bytes; /**< Reset value of bytes. */ + void *dcs_when_free; + /* + * For non-batch mode, the dcs will be saved here + * when the counter is free. + */ }; + void *action; /**< Pointer to the dv action. */ }; TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); @@ -409,13 +409,14 @@ struct mlx5_flow_counter_pool { /* The devx object of the minimum counter ID. */ uint64_t time_of_last_age_check; /* System time (from rte_rdtsc()) read in the last aging check. */ - uint32_t index:28; /* Pool index in container. */ - uint32_t type:2; /* Memory type behind the counter array. */ - uint32_t skip_cnt:1; /* Pool contains skipped counter. */ + uint32_t index:30; /* Pool index in container. */ + uint32_t is_aged:1; /* Pool with aging counter. */ volatile uint32_t query_gen:1; /* Query round. */ rte_spinlock_t sl; /* The pool lock. */ + rte_spinlock_t csl; /* The pool counter free list lock. */ struct mlx5_counter_stats_raw *raw; - struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ + struct mlx5_counter_stats_raw *raw_hw; + /* The raw on HW working. */ }; /* Memory management structure for group of counter statistics raws. */ @@ -429,38 +430,33 @@ struct mlx5_counter_stats_mem_mng { /* Raw memory structure for the counter statistics values of a pool. */ struct mlx5_counter_stats_raw { LIST_ENTRY(mlx5_counter_stats_raw) next; - int min_dcs_id; struct mlx5_counter_stats_mem_mng *mem_mng; volatile struct flow_counter_stats *data; }; TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); -/* Container structure for counter pools. */ -struct mlx5_pools_container { - rte_atomic16_t n_valid; /* Number of valid pools. */ +/* Counter global management structure. */ +struct mlx5_flow_counter_mng { + volatile uint16_t n_valid; /* Number of valid pools. */ uint16_t n; /* Number of pools. */ uint16_t last_pool_idx; /* Last used pool index */ int min_id; /* The minimum counter ID in the pools. */ int max_id; /* The maximum counter ID in the pools. */ - rte_spinlock_t resize_sl; /* The resize lock. */ - rte_spinlock_t csl; /* The counter free list lock. */ + rte_spinlock_t pool_update_sl; /* The pool update lock. */ + rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; + /* The counter free list lock. */ struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; /* Free counter list. */ - struct mlx5_counter_pools pool_list; /* Counter pool list. */ struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ struct mlx5_counter_stats_mem_mng *mem_mng; /* Hold the memory management for the next allocated pools raws. */ -}; - -/* Counter global management structure. */ -struct mlx5_flow_counter_mng { - struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX]; struct mlx5_counters flow_counters; /* Legacy flow counter list. */ uint8_t pending_queries; - uint8_t batch; uint16_t pool_index; uint8_t query_thread_on; + bool relaxed_ordering; + bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; @@ -643,7 +639,6 @@ struct mlx5_dev_ctx_shared { uint32_t dv_meta_mask; /* flow META metadata supported mask. */ uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ - uint32_t dv_refcnt; /* DV/DR data reference counter. */ void *fdb_domain; /* FDB Direct Rules name space handle. */ void *rx_domain; /* RX Direct Rules name space handle. */ void *tx_domain; /* TX Direct Rules name space handle. */ @@ -653,6 +648,7 @@ struct mlx5_dev_ctx_shared { /* UAR same-page access control required in 32bit implementations. */ #endif struct mlx5_hlist *flow_tbls; + struct mlx5_flow_tunnel_hub *tunnel_hub; /* Direct Rules tables for FDB, NIC TX+RX */ void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ @@ -733,9 +729,11 @@ struct mlx5_ind_table_obj { }; /* Hash Rx queue. */ +__extension__ struct mlx5_hrxq { ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t shared:1; /* This object used in shared action. */ struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ RTE_STD_C11 union { @@ -807,6 +805,10 @@ struct mlx5_obj_ops { void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, int tunnel __rte_unused); + int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, + const uint8_t *rss_key, + uint64_t hash_fields, + const struct mlx5_ind_table_obj *ind_tbl); void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); int (*drop_action_create)(struct rte_eth_dev *dev); void (*drop_action_destroy)(struct rte_eth_dev *dev); @@ -831,9 +833,7 @@ struct mlx5_priv { unsigned int isolated:1; /* Whether isolated mode is enabled. */ unsigned int representor:1; /* Device is a port representor. */ unsigned int master:1; /* Device is a E-Switch master. */ - unsigned int dr_shared:1; /* DV/DR data is shared. */ unsigned int txpp_en:1; /* Tx packet pacing enabled. */ - unsigned int counter_fallback:1; /* Use counter fallback management. */ unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ unsigned int sampler_en:1; /* Whether support sampler. */ @@ -897,6 +897,8 @@ struct mlx5_priv { uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ struct mlx5_mp_id mp_id; /* ID of a multi-process process */ LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ + LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions; + /* shared actions */ }; #define PORT_ID(priv) ((priv)->dev_data->port_id)