X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=82fcb29be63e3b06aa3ab519e7a192ca48afbe9e;hb=f6d9ab4e769f0f95ecac1b418106e9f8137ca60c;hp=ef05d9f975260d82d265a1c38c7f4be619f7fafe;hpb=79e35d0d59793d6f70d13aee25aa2df3deefcd8e;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index ef05d9f975..82fcb29be6 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -33,7 +33,6 @@ #include "mlx5_utils.h" #include "mlx5_mr.h" -#include "mlx5_rxtx.h" #include "mlx5_autoconf.h" #include "mlx5_defs.h" @@ -81,16 +80,26 @@ struct mlx5_mp_param { /** Key string for IPC. */ #define MLX5_MP_NAME "net_mlx5_mp" +/* Recognized Infiniband device physical port name types. */ +enum mlx5_phys_port_name_type { + MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ + MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ + MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ + MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ + MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ +}; + /** Switch information returned by mlx5_nl_switch_info(). */ struct mlx5_switch_info { uint32_t master:1; /**< Master device. */ uint32_t representor:1; /**< Representor device. */ - uint32_t port_name_new:1; /**< Rep. port name is in new format. */ + enum mlx5_phys_port_name_type name_type; /** < Port name type. */ + int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ int32_t port_name; /**< Representor port name. */ uint64_t switch_id; /**< Switch identifier. */ }; -LIST_HEAD(mlx5_dev_list, mlx5_priv); +LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); /* Shared data between primary and secondary processes. */ struct mlx5_shared_data { @@ -98,8 +107,6 @@ struct mlx5_shared_data { /* Global spinlock for primary and secondary processes. */ int init_done; /* Whether primary has done initialization. */ unsigned int secondary_cnt; /* Number of secondary processes init'd. */ - void *uar_base; - /* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */ struct mlx5_dev_list mem_event_cb_list; rte_rwlock_t mem_event_rwlock; }; @@ -107,8 +114,6 @@ struct mlx5_shared_data { /* Per-process data structure, not visible to other processes. */ struct mlx5_local_data { int init_done; /* Whether a secondary has done initialization. */ - void *uar_base; - /* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */ }; extern struct mlx5_shared_data *mlx5_shared_data; @@ -143,6 +148,11 @@ struct mlx5_devx_counter_set { int id; /* Flow counter ID */ }; +/* HCA attributes. */ +struct mlx5_hca_attr { + uint32_t eswitch_manager:1; +}; + /* Flow list . */ TAILQ_HEAD(mlx5_flows, rte_flow); @@ -176,6 +186,7 @@ struct mlx5_dev_config { /* Whether memseg should be extended for MR creation. */ unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ + unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ unsigned int dv_flow_en:1; /* Enable DV flow. */ unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ unsigned int devx:1; /* Whether devx interface is available or not. */ @@ -197,6 +208,7 @@ struct mlx5_dev_config { int txqs_inline; /* Queue number threshold for inlining. */ int txqs_vec; /* Queue number threshold for vectorized Tx. */ int inline_max_packet_sz; /* Max packet size for inlining. */ + struct mlx5_hca_attr hca_attr; /* HCA attributes. */ }; /** @@ -246,6 +258,7 @@ struct mlx5_flow_tbl_resource { }; #define MLX5_MAX_TABLES 1024 +#define MLX5_MAX_TABLES_FDB 32 #define MLX5_GROUP_FACTOR 1 /* @@ -262,20 +275,36 @@ struct mlx5_ibv_shared { char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ struct ibv_device_attr_ex device_attr; /* Device properties. */ + struct rte_pci_device *pci_dev; /* Backend PCI device. */ + LIST_ENTRY(mlx5_ibv_shared) mem_event_cb; + /**< Called by memory event callback. */ + struct { + uint32_t dev_gen; /* Generation number to flush local caches. */ + rte_rwlock_t rwlock; /* MR Lock. */ + struct mlx5_mr_btree cache; /* Global MR cache table. */ + struct mlx5_mr_list mr_list; /* Registered MR list. */ + struct mlx5_mr_list mr_free_list; /* Freed MR list. */ + } mr; /* Shared DV/DR flow data section. */ pthread_mutex_t dv_mutex; /* DV context mutex. */ uint32_t dv_refcnt; /* DV/DR data reference counter. */ + void *fdb_ns; /* FDB Direct Rules name space handle. */ + struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB]; + /* FDB Direct Rules tables. */ void *rx_ns; /* RX Direct Rules name space handle. */ struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES]; /* RX Direct Rules tables. */ void *tx_ns; /* TX Direct Rules name space handle. */ struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES]; + void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ /* TX Direct Rules tables/ */ LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags; LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl; + LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource) + port_id_action_list; /* List of port ID actions. */ /* Shared interrupt handler section. */ pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ uint32_t intr_cnt; /* Interrupt handler reference counter. */ @@ -283,9 +312,18 @@ struct mlx5_ibv_shared { struct mlx5_ibv_shared_port port[]; /* per device port data array. */ }; +/* Per-process private structure. */ +struct mlx5_proc_priv { + size_t uar_table_sz; + /* Size of UAR register table. */ + void *uar_table[]; + /* Table of UAR registers for each process. */ +}; + +#define MLX5_PROC_PRIV(port_id) \ + ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) + struct mlx5_priv { - LIST_ENTRY(mlx5_priv) mem_event_cb; - /**< Called by memory event callback. */ struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ struct mlx5_ibv_shared *sh; /* Shared IB device context. */ uint32_t ibv_port; /* IB device port number. */ @@ -317,13 +355,6 @@ struct mlx5_priv { struct mlx5_flows ctrl_flows; /* Control flow rules. */ LIST_HEAD(counters, mlx5_flow_counter) flow_counters; /* Flow counters. */ - struct { - uint32_t dev_gen; /* Generation number to flush local caches. */ - rte_rwlock_t rwlock; /* MR Lock. */ - struct mlx5_mr_btree cache; /* Global MR cache table. */ - struct mlx5_mr_list mr_list; /* Registered MR list. */ - struct mlx5_mr_list mr_free_list; /* Freed MR list. */ - } mr; LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ @@ -360,10 +391,12 @@ struct mlx5_priv { /* mlx5.c */ int mlx5_getenv_int(const char *); +int mlx5_proc_priv_init(struct rte_eth_dev *dev); /* mlx5_ethdev.c */ int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); +int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); @@ -394,9 +427,15 @@ eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); unsigned int mlx5_dev_to_port_id(const struct rte_device *dev, uint16_t *port_list, unsigned int port_list_n); +int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id, + uint16_t *es_port_id); int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); -bool mlx5_translate_port_name(const char *port_name_in, +void mlx5_sysfs_check_switch_info(bool device_dir, + struct mlx5_switch_info *switch_info); +void mlx5_nl_check_switch_info(bool nun_vf_set, + struct mlx5_switch_info *switch_info); +void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); /* mlx5_mac.c */ @@ -531,4 +570,6 @@ int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj); int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx, int clear, uint64_t *pkts, uint64_t *bytes); +int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, + struct mlx5_hca_attr *attr); #endif /* RTE_PMD_MLX5_H_ */