X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5.h;h=d69b6a357be321c274e4a55c050d300005674ba3;hb=cf8971db657c7b1d940d66274ff73ae8cb8b0708;hp=22a21f1e5f649dcc5d8490f00d0de1d1610fa9ea;hpb=b6e9c33c82582bf88c90220e3a8c1f6a8ace843f;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 22a21f1e5f..d69b6a357b 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -275,10 +275,14 @@ struct mlx5_dev_config { unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ - unsigned int stride_num_n; /* Number of strides. */ - unsigned int stride_size_n; /* Size of a stride. */ - unsigned int min_stride_size_n; /* Min size of a stride. */ - unsigned int max_stride_size_n; /* Max size of a stride. */ + unsigned int log_stride_num; /* Log number of strides. */ + unsigned int log_stride_size; /* Log size of a stride. */ + unsigned int log_min_stride_size; /* Log min size of a stride.*/ + unsigned int log_max_stride_size; /* Log max size of a stride.*/ + unsigned int log_min_stride_num; /* Log min num of strides. */ + unsigned int log_max_stride_num; /* Log max num of strides. */ + unsigned int log_min_stride_wqe_size; + /* Log min WQE size, (size of single stride)*(num of strides).*/ unsigned int max_memcpy_len; /* Maximum packet size to memcpy Rx packets. */ unsigned int min_rxqs_num; @@ -295,7 +299,6 @@ struct mlx5_dev_config { int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ - struct mlx5_hca_attr hca_attr; /* HCA attributes. */ struct mlx5_lro_config lro; /* LRO configuration. */ }; @@ -462,8 +465,7 @@ struct mlx5_flow_counter_pool { struct mlx5_counter_stats_mem_mng { LIST_ENTRY(mlx5_counter_stats_mem_mng) next; struct mlx5_counter_stats_raw *raws; - struct mlx5_devx_obj *dm; - void *umem; + struct mlx5_pmd_wrapped_mr wm; }; /* Raw memory structure for the counter statistics values of a pool. */ @@ -494,8 +496,6 @@ struct mlx5_flow_counter_mng { uint8_t pending_queries; uint16_t pool_index; uint8_t query_thread_on; - bool relaxed_ordering_read; - bool relaxed_ordering_write; bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; @@ -530,7 +530,6 @@ struct mlx5_aso_sq { rte_spinlock_t sqsl; struct mlx5_aso_cq cq; struct mlx5_devx_sq sq_obj; - volatile uint64_t *uar_addr; struct mlx5_pmd_mr mr; uint16_t pi; uint32_t head; @@ -637,6 +636,8 @@ struct mlx5_dev_shared_port { #define MLX5_MTR_TABLE_ID_DROP 2 /* Priority of the meter policy matcher. */ #define MLX5_MTR_POLICY_MATCHER_PRIO 0 +/* Green & yellow color valid for now. */ +#define MLX5_MTR_POLICY_MODE_ALL 0 /* Default policy. */ #define MLX5_MTR_POLICY_MODE_DEF 1 /* Only green color valid. */ @@ -979,7 +980,7 @@ struct mlx5_flow_id_pool { uint32_t base_index; /**< The next index that can be used without any free elements. */ uint32_t *curr; /**< Pointer to the index to pop. */ - uint32_t *last; /**< Pointer to the last element in the empty arrray. */ + uint32_t *last; /**< Pointer to the last element in the empty array. */ uint32_t max_id; /**< Maximum id can be allocated from the pool. */ }; @@ -1016,7 +1017,7 @@ struct mlx5_dev_txpp { void *pp; /* Packet pacing context. */ uint16_t pp_id; /* Packet pacing context index. */ uint16_t ts_n; /* Number of captured timestamps. */ - uint16_t ts_p; /* Pointer to statisticks timestamp. */ + uint16_t ts_p; /* Pointer to statistics timestamp. */ struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ @@ -1120,7 +1121,7 @@ struct mlx5_flex_parser_devx { uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; }; -/* Pattern field dscriptor - how to translate flex pattern into samples. */ +/* Pattern field descriptor - how to translate flex pattern into samples. */ __extension__ struct mlx5_flex_pattern_field { uint16_t width:6; @@ -1145,7 +1146,6 @@ struct mlx5_flex_item { struct mlx5_dev_ctx_shared { LIST_ENTRY(mlx5_dev_ctx_shared) next; uint32_t refcnt; - uint32_t devx:1; /* Opened with DV. */ uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ uint32_t steering_format_version:4; /* Indicates the device steering logic format. */ @@ -1171,12 +1171,12 @@ struct mlx5_dev_ctx_shared { /* Shared DV/DR flow data section. */ uint32_t dv_meta_mask; /* flow META metadata supported mask. */ uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ - uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ + uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */ void *fdb_domain; /* FDB Direct Rules name space handle. */ void *rx_domain; /* RX Direct Rules name space handle. */ void *tx_domain; /* TX Direct Rules name space handle. */ #ifndef RTE_ARCH_64 - rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ + rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; /* UAR same-page access control required in 32bit implementations. */ #endif @@ -1205,11 +1205,11 @@ struct mlx5_dev_ctx_shared { struct mlx5_devx_obj *tis[16]; /* TIS object. */ struct mlx5_devx_obj *td; /* Transport domain. */ struct mlx5_lag lag; /* LAG attributes */ - void *tx_uar; /* Tx/packet pacing shared UAR. */ + struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ + struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ struct mlx5_ecpri_parser_profile ecpri_parser; /* Flex parser profiles information. */ - void *devx_rx_uar; /* DevX UAR for Rx. */ LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ struct mlx5_aso_age_mng *aso_age_mng; /* Management data for aging mechanism using ASO Flow Hit. */ @@ -1234,7 +1234,7 @@ struct mlx5_dev_ctx_shared { struct mlx5_proc_priv { size_t uar_table_sz; /* Size of UAR register table. */ - void *uar_table[]; + struct mlx5_uar_data uar_table[]; /* Table of UAR registers for each process. */ }; @@ -1411,6 +1411,7 @@ struct mlx5_priv { unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ unsigned int lb_used:1; /* Loopback queue is referred to. */ + uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ @@ -1516,6 +1517,9 @@ void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); port_id < RTE_MAX_ETHPORTS; \ port_id = mlx5_eth_find_next(port_id + 1, dev)) int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); +void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, + struct mlx5_dev_config *config, + struct mlx5_hca_attr *hca_attr); struct mlx5_dev_ctx_shared * mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, const struct mlx5_dev_config *config); @@ -1526,16 +1530,12 @@ int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, struct mlx5_dev_config *config); void mlx5_set_metadata_mask(struct rte_eth_dev *dev); -int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, +int mlx5_dev_check_sibling_config(struct mlx5_dev_ctx_shared *sh, struct mlx5_dev_config *config, struct rte_device *dpdk_dev); -int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); -int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); -int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); -int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, - struct rte_eth_hairpin_cap *cap); bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); +void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev); int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); @@ -1553,10 +1553,8 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev, (((repr_id) >> 12) & 3) uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, enum rte_eth_representor_type hpf_type); -int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, - size_t fw_size); -int mlx5_dev_infos_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *info); +int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); +int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, @@ -1791,6 +1789,7 @@ int mlx5_flow_meter_flush(struct rte_eth_dev *dev, void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); /* mlx5_os.c */ + struct rte_pci_driver; int mlx5_os_get_dev_attr(struct mlx5_common_device *dev, struct mlx5_dev_attr *dev_attr);