X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_defs.h;h=018d3f0f0cd4f1fba12cdf01327104e6a6f0dcc4;hb=5e393509121c2188b8d58ee7d184e1cad31c88d9;hp=bfe6655800c6e01414857bb620686ea7b8236bb2;hpb=09d8b41699bb0d90f736015a977fd3613769b4e0;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index bfe6655800..018d3f0f0c 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -6,20 +6,12 @@ #ifndef RTE_PMD_MLX5_DEFS_H_ #define RTE_PMD_MLX5_DEFS_H_ -#include +#include +#include -#include "mlx5_autoconf.h" - -/* Reported driver name. */ -#define MLX5_DRIVER_NAME "net_mlx5" +#include -/* Maximum number of simultaneous unicast MAC addresses. */ -#define MLX5_MAX_UC_MAC_ADDRESSES 128 -/* Maximum number of simultaneous Multicast MAC addresses. */ -#define MLX5_MAX_MC_MAC_ADDRESSES 128 -/* Maximum number of simultaneous MAC addresses. */ -#define MLX5_MAX_MAC_ADDRESSES \ - (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) +#include "mlx5_autoconf.h" /* Maximum number of simultaneous VLAN filters. */ #define MLX5_MAX_VLAN_IDS 128 @@ -28,7 +20,7 @@ * Request TX completion every time descriptors reach this threshold since * the previous request. Must be a power of two for performance reasons. */ -#define MLX5_TX_COMP_THRESH 32 +#define MLX5_TX_COMP_THRESH 32u /* * Request TX completion every time the total number of WQEBBs used for inlining @@ -37,11 +29,11 @@ */ #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) -/* Size of per-queue MR cache array for linear search. */ -#define MLX5_MR_CACHE_N 8 - -/* Size of MR cache table for binary search. */ -#define MLX5_MR_BTREE_CACHE_N 256 +/* + * Maximal amount of normal completion CQEs + * processed in one call of tx_burst() routine. + */ +#define MLX5_TX_COMP_MAX_CQE 2u /* * If defined, only use software counters. The PMD will never ask the hardware @@ -55,18 +47,28 @@ #define MLX5_ALARM_TIMEOUT_US 100000 /* Maximum number of extended statistics counters. */ -#define MLX5_MAX_XSTATS 32 +#define MLX5_MAX_XSTATS 64 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ -#define MLX5_MAX_TSO_HEADER 192 - -/* Default maximum number of Tx queues for vectorized Tx. */ -#if defined(RTE_ARCH_ARM64) -#define MLX5_VPMD_MAX_TXQS 8 -#else -#define MLX5_VPMD_MAX_TXQS 4 -#endif -#define MLX5_VPMD_MAX_TXQS_BLUEFIELD 16 +#define MLX5_MAX_TSO_HEADER 192U + +/* Inline data size required by NICs. */ +#define MLX5_INLINE_HSIZE_NONE 0 +#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_tcp_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_udp_hdr) + \ + sizeof(struct rte_vxlan_hdr) + \ + sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ + sizeof(struct rte_tcp_hdr)) /* Threshold of buffer replenishment for vectorized Rx. */ #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ @@ -75,31 +77,26 @@ /* Maximum size of burst for vectorized Rx. */ #define MLX5_VPMD_RX_MAX_BURST 64U -/* - * Maximum size of burst for vectorized Tx. This is related to the maximum size - * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW. - * Careful when changing, large value can cause WQE DS to overlap. - */ -#define MLX5_VPMD_TX_MAX_BURST 32U +/* Recommended optimal burst size. */ +#define MLX5_RX_DEFAULT_BURST 64U +#define MLX5_TX_DEFAULT_BURST 64U /* Number of packets vectorized Rx can simultaneously process in a loop. */ #define MLX5_VPMD_DESCS_PER_LOOP 4 +/* Mask of RSS on source only or destination only. */ +#define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \ + RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY) + /* Supported RSS */ -#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP)) +#define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \ + MLX5_RSS_SRC_DST_ONLY | RTE_ETH_RSS_ESP)) /* Timeout in seconds to get a valid link status. */ #define MLX5_LINK_STATUS_TIMEOUT 10 -/* Reserved address space for UAR mapping. */ -#define MLX5_UAR_SIZE (1ULL << (sizeof(uintptr_t) * 4)) - -/* Offset of reserved UAR address space to hugepage memory. Offset is used here - * to minimize possibility of address next to hugepage being used by other code - * in either primary or secondary process, failing to map TX UAR would make TX - * packets invisible to HW. - */ -#define MLX5_UAR_OFFSET (1ULL << (sizeof(uintptr_t) * 4)) +/* Number of times to retry retrieving the physical link information. */ +#define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 /* Maximum number of UAR pages used by a port, * These are the size and mask for an array of mutexes used to synchronize @@ -116,7 +113,10 @@ #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ -#define MLX5_MPRQ_STRIDE_NUM_N 6U +#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM 6U + +/* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ +#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE 11U /* Two-byte shift is disabled for Multi-Packet RQ. */ #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 @@ -133,8 +133,56 @@ /* Cache size of mempool for Multi-Packet RQ. */ #define MLX5_MPRQ_MP_CACHE_SZ 32U -/* Definition of static_assert found in /usr/include/assert.h */ -#ifndef HAVE_STATIC_ASSERT +/* MLX5_DV_XMETA_EN supported values. */ +#define MLX5_XMETA_MODE_LEGACY 0 +#define MLX5_XMETA_MODE_META16 1 +#define MLX5_XMETA_MODE_META32 2 +/* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ +#define MLX5_XMETA_MODE_MISS_INFO 3 + +/* Tx accurate scheduling on timestamps parameters. */ +#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ +#define MLX5_TXPP_CLKQ_SIZE 1 +#define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) +#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ + MLX5_TXPP_REARM) * 2) +#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) +/* The minimal size test packet to put into one WQE, padded by HW. */ +#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_ipv4_hdr)) + +/* Size of the simple hash table for metadata register table. */ +#define MLX5_FLOW_MREG_HTABLE_SZ 64 +#define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" +#define MLX5_DEFAULT_COPY_ID UINT32_MAX + +/* Size of the simple hash table for header modify table. */ +#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15) + +/* Size of the simple hash table for encap decap table. */ +#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12) + +/* Size of the hash table for tag table. */ +#define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15) + +/* Size fo the hash table for SFT table. */ +#define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096 + +/* Hairpin TX/RX queue configuration parameters. */ +#define MLX5_HAIRPIN_QUEUE_STRIDE 6 +#define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) + +/* Maximum number of indirect actions supported by rte_flow */ +#define MLX5_MAX_INDIRECT_ACTIONS 3 + +/* Maximum number of external Rx queues supported by rte_flow */ +#define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1) + +/* + * Linux definition of static_assert is found in /usr/include/assert.h. + * Windows does not require a redefinition. + */ +#if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS) #define static_assert _Static_assert #endif