X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_defs.h;h=018d3f0f0cd4f1fba12cdf01327104e6a6f0dcc4;hb=75315881c23f3aa7c04fb19c50915e64dd97bd38;hp=a8626a4acde2a87f47f60ec1ac344bb93b29ff01;hpb=551c94c83efbce7e860e36963daae8f62f6e87af;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index a8626a4acd..018d3f0f0c 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -6,13 +6,12 @@ #ifndef RTE_PMD_MLX5_DEFS_H_ #define RTE_PMD_MLX5_DEFS_H_ -#include +#include #include -#include "mlx5_autoconf.h" +#include -/* Reported driver name. */ -#define MLX5_DRIVER_NAME "net_mlx5" +#include "mlx5_autoconf.h" /* Maximum number of simultaneous VLAN filters. */ #define MLX5_MAX_VLAN_IDS 128 @@ -36,13 +35,6 @@ */ #define MLX5_TX_COMP_MAX_CQE 2u - -/* Size of per-queue MR cache array for linear search. */ -#define MLX5_MR_CACHE_N 8 - -/* Size of MR cache table for binary search. */ -#define MLX5_MR_BTREE_CACHE_N 256 - /* * If defined, only use software counters. The PMD will never ask the hardware * for these, and many of them won't be available. @@ -51,18 +43,14 @@ #define MLX5_PMD_SOFT_COUNTERS 1 #endif -/* Switch port ID parameters for bonding configurations. */ -#define MLX5_PORT_ID_BONDING_PF_MASK 0xf -#define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf - /* Alarm timeout. */ #define MLX5_ALARM_TIMEOUT_US 100000 /* Maximum number of extended statistics counters. */ -#define MLX5_MAX_XSTATS 32 +#define MLX5_MAX_XSTATS 64 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ -#define MLX5_MAX_TSO_HEADER (128u + 34u) +#define MLX5_MAX_TSO_HEADER 192U /* Inline data size required by NICs. */ #define MLX5_INLINE_HSIZE_NONE 0 @@ -97,12 +85,12 @@ #define MLX5_VPMD_DESCS_PER_LOOP 4 /* Mask of RSS on source only or destination only. */ -#define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ - ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) +#define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \ + RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY) /* Supported RSS */ -#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ - MLX5_RSS_SRC_DST_ONLY)) +#define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \ + MLX5_RSS_SRC_DST_ONLY | RTE_ETH_RSS_ESP)) /* Timeout in seconds to get a valid link status. */ #define MLX5_LINK_STATUS_TIMEOUT 10 @@ -124,27 +112,11 @@ #define MLX5_UAR_PAGE_NUM_MAX 64 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) -/* Fields of memory mapping type in offset parameter of mmap() */ -#define MLX5_UAR_MMAP_CMD_SHIFT 8 -#define MLX5_UAR_MMAP_CMD_MASK 0xff - -/* Environment variable to control the doorbell register mapping. */ -#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" -#if defined(RTE_ARCH_ARM64) -#define MLX5_SHUT_UP_BF_DEFAULT "0" -#else -#define MLX5_SHUT_UP_BF_DEFAULT "1" -#endif - -#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD -#define MLX5_MMAP_GET_NC_PAGES_CMD 3 -#endif - /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ -#define MLX5_MPRQ_STRIDE_NUM_N 6U +#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM 6U /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ -#define MLX5_MPRQ_STRIDE_SIZE_N 11U +#define MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE 11U /* Two-byte shift is disabled for Multi-Packet RQ. */ #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 @@ -165,13 +137,11 @@ #define MLX5_XMETA_MODE_LEGACY 0 #define MLX5_XMETA_MODE_META16 1 #define MLX5_XMETA_MODE_META32 2 - -/* MLX5_TX_DB_NC supported values. */ -#define MLX5_TXDB_CACHED 0 -#define MLX5_TXDB_NCACHED 1 -#define MLX5_TXDB_HEURISTIC 2 +/* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ +#define MLX5_XMETA_MODE_MISS_INFO 3 /* Tx accurate scheduling on timestamps parameters. */ +#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ #define MLX5_TXPP_CLKQ_SIZE 1 #define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) #define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ @@ -182,16 +152,37 @@ sizeof(struct rte_ipv4_hdr)) /* Size of the simple hash table for metadata register table. */ -#define MLX5_FLOW_MREG_HTABLE_SZ 4096 +#define MLX5_FLOW_MREG_HTABLE_SZ 64 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" #define MLX5_DEFAULT_COPY_ID UINT32_MAX +/* Size of the simple hash table for header modify table. */ +#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15) + +/* Size of the simple hash table for encap decap table. */ +#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12) + +/* Size of the hash table for tag table. */ +#define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15) + +/* Size fo the hash table for SFT table. */ +#define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096 + /* Hairpin TX/RX queue configuration parameters. */ #define MLX5_HAIRPIN_QUEUE_STRIDE 6 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) -/* Definition of static_assert found in /usr/include/assert.h */ -#ifndef HAVE_STATIC_ASSERT +/* Maximum number of indirect actions supported by rte_flow */ +#define MLX5_MAX_INDIRECT_ACTIONS 3 + +/* Maximum number of external Rx queues supported by rte_flow */ +#define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1) + +/* + * Linux definition of static_assert is found in /usr/include/assert.h. + * Windows does not require a redefinition. + */ +#if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS) #define static_assert _Static_assert #endif