X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_defs.h;h=258475ed2c54efd20cda75b32ed80c8c4d549c90;hb=693c7d4b1e12024cd429ef563e9df5cc2c477aee;hp=260f584298d03ae47a288a3c30cb86a8599c8bdd;hpb=ecb160456aed51ccf69dc96cb835c259d611d276;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 260f584298..258475ed2c 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -6,13 +6,12 @@ #ifndef RTE_PMD_MLX5_DEFS_H_ #define RTE_PMD_MLX5_DEFS_H_ -#include +#include #include -#include "mlx5_autoconf.h" +#include -/* Reported driver name. */ -#define MLX5_DRIVER_NAME "net_mlx5" +#include "mlx5_autoconf.h" /* Maximum number of simultaneous VLAN filters. */ #define MLX5_MAX_VLAN_IDS 128 @@ -36,13 +35,6 @@ */ #define MLX5_TX_COMP_MAX_CQE 2u - -/* Size of per-queue MR cache array for linear search. */ -#define MLX5_MR_CACHE_N 8 - -/* Size of MR cache table for binary search. */ -#define MLX5_MR_BTREE_CACHE_N 256 - /* * If defined, only use software counters. The PMD will never ask the hardware * for these, and many of them won't be available. @@ -51,10 +43,6 @@ #define MLX5_PMD_SOFT_COUNTERS 1 #endif -/* Switch port ID parameters for bonding configurations. */ -#define MLX5_PORT_ID_BONDING_PF_MASK 0xf -#define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf - /* Alarm timeout. */ #define MLX5_ALARM_TIMEOUT_US 100000 @@ -97,11 +85,11 @@ #define MLX5_VPMD_DESCS_PER_LOOP 4 /* Mask of RSS on source only or destination only. */ -#define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ - ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) +#define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \ + RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY) /* Supported RSS */ -#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ +#define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \ MLX5_RSS_SRC_DST_ONLY)) /* Timeout in seconds to get a valid link status. */ @@ -124,22 +112,6 @@ #define MLX5_UAR_PAGE_NUM_MAX 64 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) -/* Fields of memory mapping type in offset parameter of mmap() */ -#define MLX5_UAR_MMAP_CMD_SHIFT 8 -#define MLX5_UAR_MMAP_CMD_MASK 0xff - -/* Environment variable to control the doorbell register mapping. */ -#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" -#if defined(RTE_ARCH_ARM64) -#define MLX5_SHUT_UP_BF_DEFAULT "0" -#else -#define MLX5_SHUT_UP_BF_DEFAULT "1" -#endif - -#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD -#define MLX5_MMAP_GET_NC_PAGES_CMD 3 -#endif - /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ #define MLX5_MPRQ_STRIDE_NUM_N 6U @@ -165,23 +137,49 @@ #define MLX5_XMETA_MODE_LEGACY 0 #define MLX5_XMETA_MODE_META16 1 #define MLX5_XMETA_MODE_META32 2 - -/* MLX5_TX_DB_NC supported values. */ -#define MLX5_TXDB_CACHED 0 -#define MLX5_TXDB_NCACHED 1 -#define MLX5_TXDB_HEURISTIC 2 +/* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ +#define MLX5_XMETA_MODE_MISS_INFO 3 + +/* Tx accurate scheduling on timestamps parameters. */ +#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ +#define MLX5_TXPP_CLKQ_SIZE 1 +#define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) +#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ + MLX5_TXPP_REARM) * 2) +#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) +/* The minimal size test packet to put into one WQE, padded by HW. */ +#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_ipv4_hdr)) /* Size of the simple hash table for metadata register table. */ -#define MLX5_FLOW_MREG_HTABLE_SZ 4096 +#define MLX5_FLOW_MREG_HTABLE_SZ 64 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" #define MLX5_DEFAULT_COPY_ID UINT32_MAX +/* Size of the simple hash table for header modify table. */ +#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15) + +/* Size of the simple hash table for encap decap table. */ +#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12) + +/* Size of the hash table for tag table. */ +#define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15) + +/* Size fo the hash table for SFT table. */ +#define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096 + /* Hairpin TX/RX queue configuration parameters. */ #define MLX5_HAIRPIN_QUEUE_STRIDE 6 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) -/* Definition of static_assert found in /usr/include/assert.h */ -#ifndef HAVE_STATIC_ASSERT +/* Maximum number of indirect actions supported by rte_flow */ +#define MLX5_MAX_INDIRECT_ACTIONS 3 + +/* + * Linux definition of static_assert is found in /usr/include/assert.h. + * Windows does not require a redefinition. + */ +#if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS) #define static_assert _Static_assert #endif