X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_defs.h;h=d7440fd38ad48676614aa7cc83de83cdc5d49784;hb=fcba820d9b9e34007223590d4c75417ed42563c1;hp=68613043ddfbdcacf7c91f0e8c4ec1e6cb1d6e5f;hpb=a6bd4911ad93f8ab8a378591b3a86f82223695eb;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 68613043dd..d7440fd38a 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -28,7 +28,7 @@ * Request TX completion every time descriptors reach this threshold since * the previous request. Must be a power of two for performance reasons. */ -#define MLX5_TX_COMP_THRESH 32 +#define MLX5_TX_COMP_THRESH 32u /* * Request TX completion every time the total number of WQEBBs used for inlining @@ -37,6 +37,13 @@ */ #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) +/* + * Maximal amount of normal completion CQEs + * processed in one call of tx_burst() routine. + */ +#define MLX5_TX_COMP_MAX_CQE 2u + + /* Size of per-queue MR cache array for linear search. */ #define MLX5_MR_CACHE_N 8 @@ -58,7 +65,25 @@ #define MLX5_MAX_XSTATS 32 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ -#define MLX5_MAX_TSO_HEADER 192 +#define MLX5_MAX_TSO_HEADER (128u + 34u) + +/* Inline data size required by NICs. */ +#define MLX5_INLINE_HSIZE_NONE 0 +#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_tcp_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_udp_hdr) + \ + sizeof(struct rte_vxlan_hdr) + \ + sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ + sizeof(struct rte_tcp_hdr)) /* Threshold of buffer replenishment for vectorized Rx. */ #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \