X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_devx.c;h=84a5c55ee07573c55a3eefc9f25a7121b3d3d28d;hb=07cae8ffabc18f492174b56a60e90e74cc48b313;hp=430ad08dd7f6b93da890d688510830df31322b04;hpb=354cc08a2dbc296f69b53b1c00e1afd39d6d3a27;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 430ad08dd7..84a5c55ee0 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -52,22 +52,37 @@ mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on) * * @param rxq_obj * DevX Rx queue object. + * @param type + * Type of change queue state. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, bool is_start) +mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; memset(&rq_attr, 0, sizeof(rq_attr)); - if (is_start) { + switch (type) { + case MLX5_RXQ_MOD_ERR2RST: + rq_attr.rq_state = MLX5_RQC_STATE_ERR; + rq_attr.state = MLX5_RQC_STATE_RST; + break; + case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; - } else { + break; + case MLX5_RXQ_MOD_RDY2ERR: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_ERR; + break; + case MLX5_RXQ_MOD_RDY2RST: rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; + break; + default: + break; } return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr); } @@ -139,14 +154,14 @@ mlx5_rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl) { struct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->rq_dbrec_page; + if (rxq_ctrl->wq_umem) { + mlx5_os_umem_dereg(rxq_ctrl->wq_umem); + rxq_ctrl->wq_umem = NULL; + } if (rxq_ctrl->rxq.wqes) { mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes); rxq_ctrl->rxq.wqes = NULL; } - if (rxq_ctrl->wq_umem) { - mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem); - rxq_ctrl->wq_umem = NULL; - } if (dbr_page) { claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs, mlx5_os_get_umem_id(dbr_page->umem), @@ -166,14 +181,14 @@ mlx5_rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl) { struct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->cq_dbrec_page; + if (rxq_ctrl->cq_umem) { + mlx5_os_umem_dereg(rxq_ctrl->cq_umem); + rxq_ctrl->cq_umem = NULL; + } if (rxq_ctrl->rxq.cqes) { rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes); rxq_ctrl->rxq.cqes = NULL; } - if (rxq_ctrl->cq_umem) { - mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem); - rxq_ctrl->cq_umem = NULL; - } if (dbr_page) { claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs, mlx5_os_get_umem_id(dbr_page->umem), @@ -193,15 +208,15 @@ mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj) { MLX5_ASSERT(rxq_obj); MLX5_ASSERT(rxq_obj->rq); - if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN) { - mlx5_devx_modify_rq(rxq_obj, false); + if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) { + mlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST); claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq)); } else { MLX5_ASSERT(rxq_obj->devx_cq); claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq)); claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq)); if (rxq_obj->devx_channel) - mlx5_glue->devx_destroy_event_channel + mlx5_os_devx_destroy_event_channel (rxq_obj->devx_channel); mlx5_rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl); mlx5_rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl); @@ -279,7 +294,7 @@ static void mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl, struct mlx5_devx_wq_attr *wq_attr) { - wq_attr->end_padding_mode = priv->config.cqe_pad ? + wq_attr->end_padding_mode = priv->config.hw_padding ? MLX5_WQ_END_PAD_MODE_ALIGN : MLX5_WQ_END_PAD_MODE_NONE; wq_attr->pd = priv->sh->pdn; @@ -360,7 +375,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx) if (!buf) return NULL; rxq_data->wqes = buf; - rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, + rxq_ctrl->wq_umem = mlx5_os_umem_reg(priv->sh->ctx, buf, wq_size, 0); if (!rxq_ctrl->wq_umem) goto error; @@ -422,10 +437,39 @@ mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx) if (priv->config.cqe_comp && !rxq_data->hw_timestamp && !rxq_data->lro) { cq_attr.cqe_comp_en = 1u; - cq_attr.mini_cqe_res_format = - mlx5_rxq_mprq_enabled(rxq_data) ? - MLX5_CQE_RESP_FORMAT_CSUM_STRIDX : + rxq_data->mcqe_format = priv->config.cqe_comp_fmt; + rxq_data->byte_mask = UINT32_MAX; + switch (priv->config.cqe_comp_fmt) { + case MLX5_CQE_RESP_FORMAT_HASH: + /* fallthrough */ + case MLX5_CQE_RESP_FORMAT_CSUM: + /* + * Select CSUM miniCQE format only for non-vectorized + * MPRQ Rx burst, use HASH miniCQE format for others. + */ + if (mlx5_rxq_check_vec_support(rxq_data) < 0 && + mlx5_rxq_mprq_enabled(rxq_data)) + cq_attr.mini_cqe_res_format = + MLX5_CQE_RESP_FORMAT_CSUM_STRIDX; + else + cq_attr.mini_cqe_res_format = MLX5_CQE_RESP_FORMAT_HASH; + rxq_data->mcqe_format = cq_attr.mini_cqe_res_format; + break; + case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX: + rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK; + /* fallthrough */ + case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX: + cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt; + break; + case MLX5_CQE_RESP_FORMAT_L34H_STRIDX: + cq_attr.mini_cqe_res_format = 0; + cq_attr.mini_cqe_res_format_ext = 1; + break; + } + DRV_LOG(DEBUG, + "Port %u Rx CQE compression is enabled, format %d.", + dev->data->port_id, priv->config.cqe_comp_fmt); /* * For vectorized Rx, it must not be doubled in order to * make cq_ci and rq_ci aligned. @@ -453,7 +497,7 @@ mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx) goto error; } rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf; - rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf, + rxq_ctrl->cq_umem = mlx5_os_umem_reg(priv->sh->ctx, buf, cq_size, IBV_ACCESS_LOCAL_WRITE); if (!rxq_ctrl->cq_umem) { @@ -489,7 +533,7 @@ mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx) rxq_data->cqe_n = log_cqe_n; rxq_data->cqn = cq_obj->id; if (rxq_ctrl->obj->devx_channel) { - ret = mlx5_glue->devx_subscribe_devx_event + ret = mlx5_os_devx_subscribe_devx_event (rxq_ctrl->obj->devx_channel, cq_obj->obj, sizeof(event_nums), @@ -535,7 +579,6 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) MLX5_ASSERT(rxq_data); MLX5_ASSERT(tmpl); - tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN; tmpl->rxq_ctrl = rxq_ctrl; attr.hairpin = 1; max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz; @@ -596,13 +639,12 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) MLX5_ASSERT(tmpl); if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) return mlx5_rxq_obj_hairpin_new(dev, idx); - tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_RQ; tmpl->rxq_ctrl = rxq_ctrl; if (rxq_ctrl->irq) { int devx_ev_flag = MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA; - tmpl->devx_channel = mlx5_glue->devx_create_event_channel + tmpl->devx_channel = mlx5_os_devx_create_event_channel (priv->sh->ctx, devx_ev_flag); if (!tmpl->devx_channel) { @@ -628,7 +670,7 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) goto error; } /* Change queue state to ready. */ - ret = mlx5_devx_modify_rq(tmpl, true); + ret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY); if (ret) goto error; rxq_data->cq_arm_sn = 0; @@ -644,7 +686,7 @@ error: if (tmpl->devx_cq) claim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq)); if (tmpl->devx_channel) - mlx5_glue->devx_destroy_event_channel(tmpl->devx_channel); + mlx5_os_devx_destroy_event_channel(tmpl->devx_channel); mlx5_rxq_release_devx_rq_resources(rxq_ctrl); mlx5_rxq_release_devx_cq_resources(rxq_ctrl); rte_errno = ret; /* Restore rte_errno. */ @@ -652,7 +694,7 @@ error: } /** - * Create RQT using DevX API as a filed of indirection table. + * Prepare RQT attribute structure for DevX RQT API. * * @param dev * Pointer to Ethernet device. @@ -662,30 +704,31 @@ error: * DevX indirection table object. * * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. + * The RQT attr object initialized, NULL otherwise and rte_errno is set. */ -static int -mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, - struct mlx5_ind_table_obj *ind_tbl) +static struct mlx5_devx_rqt_attr * +mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev, + const unsigned int log_n, + const uint16_t *queues, + const uint32_t queues_n) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_devx_rqt_attr *rqt_attr = NULL; const unsigned int rqt_n = 1 << log_n; unsigned int i, j; - MLX5_ASSERT(ind_tbl); rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) + rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY); if (!rqt_attr) { DRV_LOG(ERR, "Port %u cannot allocate RQT resources.", dev->data->port_id); rte_errno = ENOMEM; - return -rte_errno; + return NULL; } rqt_attr->rqt_max_size = priv->config.ind_table_max_size; rqt_attr->rqt_actual_size = rqt_n; - for (i = 0; i != ind_tbl->queues_n; ++i) { - struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]]; + for (i = 0; i != queues_n; ++i) { + struct mlx5_rxq_data *rxq = (*priv->rxqs)[queues[i]]; struct mlx5_rxq_ctrl *rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq); @@ -694,6 +737,35 @@ mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, MLX5_ASSERT(i > 0); for (j = 0; i != rqt_n; ++j, ++i) rqt_attr->rq_list[i] = rqt_attr->rq_list[j]; + return rqt_attr; +} + +/** + * Create RQT using DevX API as a filed of indirection table. + * + * @param dev + * Pointer to Ethernet device. + * @param log_n + * Log of number of queues in the array. + * @param ind_tbl + * DevX indirection table object. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, + struct mlx5_ind_table_obj *ind_tbl) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_devx_rqt_attr *rqt_attr = NULL; + + MLX5_ASSERT(ind_tbl); + rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, + ind_tbl->queues, + ind_tbl->queues_n); + if (!rqt_attr) + return -rte_errno; ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx, rqt_attr); mlx5_free(rqt_attr); if (!ind_tbl->rqt) { @@ -705,6 +777,41 @@ mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, return 0; } +/** + * Modify RQT using DevX API as a filed of indirection table. + * + * @param dev + * Pointer to Ethernet device. + * @param log_n + * Log of number of queues in the array. + * @param ind_tbl + * DevX indirection table object. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_devx_ind_table_modify(struct rte_eth_dev *dev, const unsigned int log_n, + const uint16_t *queues, const uint32_t queues_n, + struct mlx5_ind_table_obj *ind_tbl) +{ + int ret = 0; + struct mlx5_devx_rqt_attr *rqt_attr = NULL; + + MLX5_ASSERT(ind_tbl); + rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, + queues, + queues_n); + if (!rqt_attr) + return -rte_errno; + ret = mlx5_devx_cmd_modify_rqt(ind_tbl->rqt, rqt_attr); + mlx5_free(rqt_attr); + if (ret) + DRV_LOG(ERR, "Port %u cannot modify DevX RQT.", + dev->data->port_id); + return ret; +} + /** * Destroy the DevX RQT object. * @@ -718,33 +825,37 @@ mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl) } /** - * Create an Rx Hash queue. + * Set TIR attribute struct with relevant input values. * - * @param dev + * @param[in] dev * Pointer to Ethernet device. - * @param hrxq - * Pointer to Rx Hash queue. - * @param tunnel + * @param[in] rss_key + * RSS key for the Rx hash queue. + * @param[in] hash_fields + * Verbs protocol hash field to make the RSS on. + * @param[in] ind_tbl + * Indirection table for TIR. + * @param[in] tunnel * Tunnel type. + * @param[out] tir_attr + * Parameters structure for TIR creation/modification. * * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. + * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set. */ -static int -mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, - int tunnel __rte_unused) +static void +mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, + uint64_t hash_fields, + const struct mlx5_ind_table_obj *ind_tbl, + int tunnel, struct mlx5_devx_tir_attr *tir_attr) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table; struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]]; struct mlx5_rxq_ctrl *rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); - struct mlx5_devx_tir_attr tir_attr; - const uint8_t *rss_key = hrxq->rss_key; - uint64_t hash_fields = hrxq->hash_fields; + enum mlx5_rxq_type rxq_obj_type = rxq_ctrl->type; bool lro = true; uint32_t i; - int err; /* Enable TIR LRO only if all the queues were configured for. */ for (i = 0; i < ind_tbl->queues_n; ++i) { @@ -753,26 +864,24 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, break; } } - memset(&tir_attr, 0, sizeof(tir_attr)); - tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT; - tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ; - tir_attr.tunneled_offload_en = !!tunnel; + memset(tir_attr, 0, sizeof(*tir_attr)); + tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT; + tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ; + tir_attr->tunneled_offload_en = !!tunnel; /* If needed, translate hash_fields bitmap to PRM format. */ if (hash_fields) { - struct mlx5_rx_hash_field_select *rx_hash_field_select = NULL; + struct mlx5_rx_hash_field_select *rx_hash_field_select = #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT - rx_hash_field_select = hash_fields & IBV_RX_HASH_INNER ? - &tir_attr.rx_hash_field_selector_inner : - &tir_attr.rx_hash_field_selector_outer; -#else - rx_hash_field_select = &tir_attr.rx_hash_field_selector_outer; + hash_fields & IBV_RX_HASH_INNER ? + &tir_attr->rx_hash_field_selector_inner : #endif + &tir_attr->rx_hash_field_selector_outer; /* 1 bit: 0: IPv4, 1: IPv6. */ rx_hash_field_select->l3_prot_type = !!(hash_fields & MLX5_IPV6_IBV_RX_HASH); /* 1 bit: 0: TCP, 1: UDP. */ rx_hash_field_select->l4_prot_type = - !!(hash_fields & MLX5_UDP_IBV_RX_HASH); + !!(hash_fields & MLX5_UDP_IBV_RX_HASH); /* Bitmask which sets which fields to use in RX Hash. */ rx_hash_field_select->selected_fields = ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) << @@ -784,20 +893,47 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT; } - if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) - tir_attr.transport_domain = priv->sh->td->id; + if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN) + tir_attr->transport_domain = priv->sh->td->id; else - tir_attr.transport_domain = priv->sh->tdn; - memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN); - tir_attr.indirect_table = ind_tbl->rqt->id; + tir_attr->transport_domain = priv->sh->tdn; + memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN); + tir_attr->indirect_table = ind_tbl->rqt->id; if (dev->data->dev_conf.lpbk_mode) - tir_attr.self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; + tir_attr->self_lb_block = + MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; if (lro) { - tir_attr.lro_timeout_period_usecs = priv->config.lro.timeout; - tir_attr.lro_max_msg_sz = priv->max_lro_msg_size; - tir_attr.lro_enable_mask = MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | - MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO; + tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout; + tir_attr->lro_max_msg_sz = priv->max_lro_msg_size; + tir_attr->lro_enable_mask = + MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | + MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO; } +} + +/** + * Create an Rx Hash queue. + * + * @param dev + * Pointer to Ethernet device. + * @param hrxq + * Pointer to Rx Hash queue. + * @param tunnel + * Tunnel type. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, + int tunnel __rte_unused) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_devx_tir_attr tir_attr = {0}; + int err; + + mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields, + hrxq->ind_table, tunnel, &tir_attr); hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr); if (!hrxq->tir) { DRV_LOG(ERR, "Port %u cannot create DevX TIR.", @@ -834,6 +970,57 @@ mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq) claim_zero(mlx5_devx_cmd_destroy(hrxq->tir)); } +/** + * Modify an Rx Hash queue configuration. + * + * @param dev + * Pointer to Ethernet device. + * @param hrxq + * Hash Rx queue to modify. + * @param rss_key + * RSS key for the Rx hash queue. + * @param hash_fields + * Verbs protocol hash field to make the RSS on. + * @param[in] ind_tbl + * Indirection table for TIR. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, + const uint8_t *rss_key, + uint64_t hash_fields, + const struct mlx5_ind_table_obj *ind_tbl) +{ + struct mlx5_devx_modify_tir_attr modify_tir = {0}; + + /* + * untested for modification fields: + * - rx_hash_symmetric not set in hrxq_new(), + * - rx_hash_fn set hard-coded in hrxq_new(), + * - lro_xxx not set after rxq setup + */ + if (ind_tbl != hrxq->ind_table) + modify_tir.modify_bitmask |= + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE; + if (hash_fields != hrxq->hash_fields || + memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN)) + modify_tir.modify_bitmask |= + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH; + mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl, + 0, /* N/A - tunnel modification unsupported */ + &modify_tir.tir); + modify_tir.tirn = hrxq->tir->id; + if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) { + DRV_LOG(ERR, "port %u cannot modify DevX TIR", + dev->data->port_id); + rte_errno = errno; + return -rte_errno; + } + return 0; +} + /** * Create a DevX drop action for Rx Hash queue. * @@ -935,17 +1122,25 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) static void mlx5_txq_release_devx_sq_resources(struct mlx5_txq_obj *txq_obj) { - if (txq_obj->sq_devx) + if (txq_obj->sq_devx) { claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx)); - if (txq_obj->sq_umem) - claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->sq_umem)); - if (txq_obj->sq_buf) + txq_obj->sq_devx = NULL; + } + if (txq_obj->sq_umem) { + claim_zero(mlx5_os_umem_dereg(txq_obj->sq_umem)); + txq_obj->sq_umem = NULL; + } + if (txq_obj->sq_buf) { mlx5_free(txq_obj->sq_buf); - if (txq_obj->sq_dbrec_page) + txq_obj->sq_buf = NULL; + } + if (txq_obj->sq_dbrec_page) { claim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs, mlx5_os_get_umem_id (txq_obj->sq_dbrec_page->umem), txq_obj->sq_dbrec_offset)); + txq_obj->sq_dbrec_page = NULL; + } } /** @@ -960,7 +1155,7 @@ mlx5_txq_release_devx_cq_resources(struct mlx5_txq_obj *txq_obj) if (txq_obj->cq_devx) claim_zero(mlx5_devx_cmd_destroy(txq_obj->cq_devx)); if (txq_obj->cq_umem) - claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->cq_umem)); + claim_zero(mlx5_os_umem_dereg(txq_obj->cq_umem)); if (txq_obj->cq_buf) mlx5_free(txq_obj->cq_buf); if (txq_obj->cq_dbrec_page) @@ -979,8 +1174,8 @@ mlx5_txq_release_devx_cq_resources(struct mlx5_txq_obj *txq_obj) static void mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj) { - mlx5_txq_release_devx_cq_resources(txq_obj); mlx5_txq_release_devx_sq_resources(txq_obj); + mlx5_txq_release_devx_cq_resources(txq_obj); } /** @@ -1048,7 +1243,7 @@ mlx5_txq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx) return 0; } /* Register allocated buffer in user space with DevX. */ - txq_obj->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, + txq_obj->cq_umem = mlx5_os_umem_reg(priv->sh->ctx, (void *)txq_obj->cq_buf, cqe_n * sizeof(struct mlx5_cqe), IBV_ACCESS_LOCAL_WRITE); @@ -1147,7 +1342,7 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx) goto error; } /* Register allocated buffer in user space with DevX. */ - txq_obj->sq_umem = mlx5_glue->devx_umem_reg + txq_obj->sq_umem = mlx5_os_umem_reg (priv->sh->ctx, (void *)txq_obj->sq_buf, wqe_n * sizeof(struct mlx5_wqe), @@ -1305,6 +1500,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) txq_ctrl->uar_mmap_offset = mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar); txq_uar_init(txq_ctrl); + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED; return 0; error: ret = rte_errno; /* Save rte_errno before cleanup. */ @@ -1341,9 +1537,11 @@ struct mlx5_obj_ops devx_obj_ops = { .rxq_obj_modify = mlx5_devx_modify_rq, .rxq_obj_release = mlx5_rxq_devx_obj_release, .ind_table_new = mlx5_devx_ind_table_new, + .ind_table_modify = mlx5_devx_ind_table_modify, .ind_table_destroy = mlx5_devx_ind_table_destroy, .hrxq_new = mlx5_devx_hrxq_new, .hrxq_destroy = mlx5_devx_tir_destroy, + .hrxq_modify = mlx5_devx_hrxq_modify, .drop_action_create = mlx5_devx_drop_action_create, .drop_action_destroy = mlx5_devx_drop_action_destroy, .txq_obj_new = mlx5_txq_devx_obj_new,