X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_flow.h;h=1ee5a9eb15bdb7b0edba4cd4d0f3b8e36dc20816;hb=784b83495bc5c40c5aa91d1e4d3966ec22e59e38;hp=58185fb1935db56f105097f775066acc284d6bc7;hpb=81073e1f8ce1250c54e20ea0e6adc06433d022eb;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 58185fb193..1ee5a9eb15 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -5,11 +5,10 @@ #ifndef RTE_PMD_MLX5_FLOW_H_ #define RTE_PMD_MLX5_FLOW_H_ -#include -#include #include #include #include +#include #include #include @@ -80,6 +79,7 @@ enum mlx5_feature_name { MLX5_COPY_MARK, MLX5_MTR_COLOR, MLX5_MTR_SFX, + MLX5_ASO_FLOW_HIT, }; /* Default queue number. */ @@ -137,6 +137,10 @@ enum mlx5_feature_name { #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) +/* Pattern tunnel Layer bits (continued). */ +#define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) +#define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -214,6 +218,7 @@ enum mlx5_feature_name { #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) +#define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) #define MLX5_FLOW_FATE_ACTIONS \ (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ @@ -244,7 +249,8 @@ enum mlx5_feature_name { MLX5_FLOW_ACTION_MARK_EXT | \ MLX5_FLOW_ACTION_SET_META | \ MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ - MLX5_FLOW_ACTION_SET_IPV6_DSCP) + MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ + MLX5_FLOW_ACTION_MODIFY_FIELD) #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ MLX5_FLOW_ACTION_OF_PUSH_VLAN) @@ -265,8 +271,15 @@ enum mlx5_feature_name { /* UDP port numbers for GENEVE. */ #define MLX5_UDP_PORT_GENEVE 6081 -/* Priority reserved for default flows. */ -#define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) +/* Lowest priority indicator. */ +#define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) + +/* + * Max priority for ingress\egress flow groups + * greater than 0 and for any transfer flow group. + * From user configation: 0 - 21843. + */ +#define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) /* * Number of sub priorities. @@ -325,7 +338,7 @@ enum mlx5_feature_name { #define MLX5_GENEVE_VER_VAL(a) \ (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) #define MLX5_GENEVE_OPTLEN_MASK 0x3F -#define MLX5_GENEVE_OPTLEN_SHIFT 7 +#define MLX5_GENEVE_OPTLEN_SHIFT 8 #define MLX5_GENEVE_OPTLEN_VAL(a) \ (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) #define MLX5_GENEVE_OAMF_MASK 0x1 @@ -345,8 +358,16 @@ enum mlx5_feature_name { #define MLX5_GENEVE_OPT_LEN_0 14 #define MLX5_GENEVE_OPT_LEN_1 63 -#define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \ - sizeof(struct rte_flow_item_ipv4)) +#define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_ipv4_hdr)) +/* GTP extension header flag. */ +#define MLX5_GTP_EXT_HEADER_FLAG 4 + +/* GTP extension header max PDU type value. */ +#define MLX5_GTP_EXT_MAX_PDU_TYPE 15 + +/* GTP extension header PDU type shift. */ +#define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ #define MLX5_IPV4_FRAG_OFFSET_MASK \ @@ -373,6 +394,9 @@ enum mlx5_feature_name { #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG #define MLX5_ACT_NUM_SET_DSCP 1 +/* Maximum number of fields to modify in MODIFY_FIELD */ +#define MLX5_ACT_MAX_MOD_FIELDS 5 + enum mlx5_flow_drv_type { MLX5_FLOW_TYPE_MIN, MLX5_FLOW_TYPE_DV, @@ -388,6 +412,7 @@ enum mlx5_flow_fate_type { MLX5_FLOW_FATE_PORT_ID, MLX5_FLOW_FATE_DROP, MLX5_FLOW_FATE_DEFAULT_MISS, + MLX5_FLOW_FATE_SHARED_RSS, MLX5_FLOW_FATE_MAX, }; @@ -412,18 +437,6 @@ struct mlx5_flow_dv_matcher { #define MLX5_ENCAP_MAX_LEN 132 -/* Encap/decap resource key of the hash organization. */ -union mlx5_flow_encap_decap_key { - struct { - uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ - uint32_t refmt_type:8; /**< Header reformat type. */ - uint32_t buf_size:8; /**< Encap buf size. */ - uint32_t table_level:8; /**< Root table or not. */ - uint32_t cksum; /**< Encap buf check sum. */ - }; - uint64_t v64; /**< full 64bits value of key */ -}; - /* Encap/decap resource structure. */ struct mlx5_flow_dv_encap_decap_resource { struct mlx5_hlist_entry entry; @@ -447,6 +460,7 @@ struct mlx5_flow_dv_tag_resource { /**< Tag action object. */ uint32_t refcnt; /**< Reference counter. */ uint32_t idx; /**< Index for the index memory pool. */ + uint32_t tag_id; /**< Tag ID. */ }; /* @@ -519,6 +533,7 @@ struct mlx5_flow_mreg_copy_resource { /* List entry for device flows. */ uint32_t idx; uint32_t rix_flow; /* Built flow for copy. */ + uint32_t mark_id; }; /* Table tunnel parameter. */ @@ -542,9 +557,13 @@ struct mlx5_flow_tbl_data_entry { /**< tunnel offload */ const struct mlx5_flow_tunnel *tunnel; uint32_t group_id; - bool external; - bool tunnel_offload; /* Tunnel offlod table or not. */ - bool is_egress; /**< Egress table. */ + uint32_t external:1; + uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ + uint32_t is_egress:1; /**< Egress table. */ + uint32_t is_transfer:1; /**< Transfer table. */ + uint32_t dummy:1; /**< DR table. */ + uint32_t reserve:27; /**< Reserved to future using. */ + uint32_t table_id; /**< Table ID. */ }; /* Sub rdma-core actions list. */ @@ -556,15 +575,16 @@ struct mlx5_flow_sub_actions_list { void *dr_cnt_action; void *dr_port_id_action; void *dr_encap_action; + void *dr_jump_action; }; /* Sample sub-actions resource list. */ struct mlx5_flow_sub_actions_idx { uint32_t rix_hrxq; /**< Hash Rx queue object index. */ uint32_t rix_tag; /**< Index to the tag action. */ - uint32_t cnt; uint32_t rix_port_id_action; /**< Index to port ID action resource. */ uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ + uint32_t rix_jump; /**< Index to the jump action resource. */ }; /* Sample action resource structure. */ @@ -574,13 +594,13 @@ struct mlx5_flow_dv_sample_resource { void *verbs_action; /**< Verbs sample action object. */ void **sub_actions; /**< Sample sub-action array. */ }; + struct rte_eth_dev *dev; /**< Device registers the action. */ uint32_t idx; /** Sample object index. */ uint8_t ft_type; /** Flow Table Type */ uint32_t ft_id; /** Flow Table Level */ uint32_t ratio; /** Sample Ratio */ uint64_t set_action; /** Restore reg_c0 value */ void *normal_path_tbl; /** Flow Table pointer */ - void *default_miss; /** default_miss dr_action. */ struct mlx5_flow_sub_actions_idx sample_idx; /**< Action index resources. */ struct mlx5_flow_sub_actions_list sample_act; @@ -595,6 +615,7 @@ struct mlx5_flow_dv_dest_array_resource { uint32_t idx; /** Destination array action object index. */ uint8_t ft_type; /** Flow Table Type */ uint8_t num_of_dest; /**< Number of destination actions. */ + struct rte_eth_dev *dev; /**< Device registers the action. */ void *action; /**< Pointer to the rdma core action. */ struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; /**< Action index resources. */ @@ -602,12 +623,6 @@ struct mlx5_flow_dv_dest_array_resource { /**< Action resources. */ }; -/* Verbs specification header. */ -struct ibv_spec_header { - enum ibv_flow_spec_type type; - uint16_t size; -}; - /* PMD flow priority for tunnel */ #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) @@ -651,8 +666,10 @@ struct mlx5_flow_handle { /**< Generic value indicates the fate action. */ uint32_t rix_default_fate; /**< Indicates default miss fate action. */ + uint32_t rix_srss; + /**< Indicates shared RSS fate action. */ }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_flow_handle_dv dvh; #endif } __rte_packed; @@ -662,7 +679,7 @@ struct mlx5_flow_handle { * structure in Verbs. No DV flows attributes will be accessed. * Macro offsetof() could also be used here. */ -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) #define MLX5_FLOW_HANDLE_VERBS_SIZE \ (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) #else @@ -700,6 +717,7 @@ struct mlx5_flow_dv_workspace { /**< Pointer to the destination array resource. */ }; +#ifdef HAVE_INFINIBAND_VERBS_H /* * Maximal Verbs flow specifications & actions size. * Some elements are mutually exclusive, but enough space should be allocated. @@ -756,11 +774,16 @@ struct mlx5_flow_verbs_workspace { uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; /**< Specifications & actions buffer of verbs flow. */ }; +#endif /* HAVE_INFINIBAND_VERBS_H */ + +#define MLX5_SCALE_FLOW_GROUP_BIT 0 +#define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 /** Maximal number of device sub-flows supported. */ #define MLX5_NUM_MAX_DEV_FLOWS 32 /** Device flow structure. */ +__extension__ struct mlx5_flow { struct rte_flow *flow; /**< Pointer to the main flow. */ uint32_t flow_idx; /**< The memory pool index to the main flow. */ @@ -768,12 +791,28 @@ struct mlx5_flow { uint64_t act_flags; /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ bool external; /**< true if the flow is created external to PMD. */ - uint8_t ingress; /**< 1 if the flow is ingress. */ + uint8_t ingress:1; /**< 1 if the flow is ingress. */ + uint8_t skip_scale:2; + /** + * Each Bit be set to 1 if Skip the scale the flow group with factor. + * If bit0 be set to 1, then skip the scale the original flow group; + * If bit1 be set to 1, then skip the scale the jump flow group if + * having jump action. + * 00: Enable scale in a flow, default value. + * 01: Skip scale the flow group with factor, enable scale the group + * of jump action. + * 10: Enable scale the group with factor, skip scale the group of + * jump action. + * 11: Skip scale the table with factor both for flow group and jump + * group. + */ union { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_flow_dv_workspace dv; #endif +#ifdef HAVE_INFINIBAND_VERBS_H struct mlx5_flow_verbs_workspace verbs; +#endif }; struct mlx5_flow_handle *handle; uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ @@ -944,8 +983,12 @@ struct mlx5_flow_tunnel { /** PMD tunnel related context */ struct mlx5_flow_tunnel_hub { + /* Tunnels list + * Access to the list MUST be MT protected + */ LIST_HEAD(, mlx5_flow_tunnel) tunnels; - rte_spinlock_t sl; /* Tunnel list spinlock. */ + /* protect access to the tunnels list */ + rte_spinlock_t sl; struct mlx5_hlist *groups; /** non tunnel groups */ }; @@ -953,6 +996,8 @@ struct mlx5_flow_tunnel_hub { struct tunnel_tbl_entry { struct mlx5_hlist_entry hash; uint32_t flow_table; + uint32_t tunnel_id; + uint32_t group; }; static inline uint32_t @@ -985,8 +1030,13 @@ mlx5_tunnel_hub(struct rte_eth_dev *dev) static inline bool is_tunnel_offload_active(struct rte_eth_dev *dev) { +#ifdef HAVE_IBV_FLOW_DV_SUPPORT struct mlx5_priv *priv = dev->data->dev_private; return !!priv->config.dv_miss_info; +#else + RTE_SET_USED(dev); + return false; +#endif } static inline bool @@ -1024,7 +1074,6 @@ flow_items_to_tunnel(const struct rte_flow_item items[]) /* Flow structure. */ struct rte_flow { ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ - uint32_t shared_rss; /** < Shared RSS action ID. */ uint32_t dev_handles; /**< Device flow handles that are part of the flow. */ uint32_t drv_type:2; /**< Driver type. */ @@ -1035,6 +1084,7 @@ struct rte_flow { uint32_t counter; /**< Holds flow counter. */ uint32_t tunnel_id; /**< Tunnel id */ uint32_t age; /**< Holds ASO age bit index. */ + uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ } __rte_packed; /* @@ -1044,17 +1094,37 @@ struct rte_flow { #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) #define MLX5_RSS_HASH_IPV4_TCP \ (MLX5_RSS_HASH_IPV4 | \ - IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) + IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) #define MLX5_RSS_HASH_IPV4_UDP \ (MLX5_RSS_HASH_IPV4 | \ - IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) + IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) #define MLX5_RSS_HASH_IPV6_TCP \ (MLX5_RSS_HASH_IPV6 | \ - IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP) + IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) #define MLX5_RSS_HASH_IPV6_UDP \ (MLX5_RSS_HASH_IPV6 | \ - IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP) + IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) +#define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 +#define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 +#define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 +#define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 +#define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ + (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) +#define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ + (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) +#define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ + (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) +#define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ + (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) +#define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ + (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) +#define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ + (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) +#define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ + (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) +#define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ + (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) #define MLX5_RSS_HASH_NONE 0ULL /* array of valid combinations of RX Hash fields for RSS */ @@ -1074,11 +1144,11 @@ struct mlx5_shared_action_rss { uint32_t refcnt; /**< Atomically accessed refcnt. */ struct rte_flow_action_rss origin; /**< Original rte RSS action. */ uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ - uint16_t *queue; /**< Queue indices to use. */ + struct mlx5_ind_table_obj *ind_tbl; + /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ - uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN]; - /**< Hash RX queue indexes for tunneled RSS */ + rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ }; struct rte_flow_shared_action { @@ -1087,11 +1157,23 @@ struct rte_flow_shared_action { /* Thread specific flow workspace intermediate data. */ struct mlx5_flow_workspace { + /* If creating another flow in same thread, push new as stack. */ + struct mlx5_flow_workspace *prev; + struct mlx5_flow_workspace *next; + uint32_t inuse; /* can't create new flow with current. */ struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; - struct mlx5_flow_rss_desc rss_desc[2]; - uint32_t rssq_num[2]; /* Allocated queue num in rss_desc. */ - int flow_idx; /* Intermediate device flow index. */ - int flow_nested_idx; /* Intermediate device flow index, nested. */ + struct mlx5_flow_rss_desc rss_desc; + uint32_t rssq_num; /* Allocated queue num in rss_desc. */ + uint32_t flow_idx; /* Intermediate device flow index. */ +}; + +struct mlx5_flow_split_info { + bool external; + /**< True if flow is created by request external to PMD. */ + uint8_t skip_scale; /**< Skip the scale the table with factor. */ + uint32_t flow_idx; /**< This memory pool index to the flow. */ + uint32_t prefix_mark; /**< Prefix subflow mark flag. */ + uint64_t prefix_layers; /**< Prefix subflow layers. */ }; typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, @@ -1211,6 +1293,7 @@ struct flow_grp_info { uint64_t fdb_def_rule:1; /* force standard group translation */ uint64_t std_tbl_fix:1; + uint64_t skip_scale:2; }; static inline bool @@ -1250,14 +1333,19 @@ tunnel_use_standard_attr_group_translate int mlx5_flow_group_to_table(struct rte_eth_dev *dev, const struct mlx5_flow_tunnel *tunnel, uint32_t group, uint32_t *table, - struct flow_grp_info flags, - struct rte_flow_error *error); + const struct flow_grp_info *flags, + struct rte_flow_error *error); uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, int tunnel, uint64_t layer_types, uint64_t hash_fields); int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, uint32_t subpriority); +uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr); +uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + uint32_t subpriority); int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, enum mlx5_feature_name feature, uint32_t id, @@ -1369,6 +1457,11 @@ int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, uint64_t item_flags, struct rte_eth_dev *dev, struct rte_flow_error *error); +int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, + uint64_t last_item, + const struct rte_flow_item *geneve_item, + struct rte_eth_dev *dev, + struct rte_flow_error *error); int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, uint64_t item_flags, uint64_t last_item, @@ -1396,6 +1489,9 @@ int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); /* Hash list callbacks for flow tables: */ struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key, void *entry_ctx); +int flow_dv_tbl_match_cb(struct mlx5_hlist *list, + struct mlx5_hlist_entry *entry, uint64_t key, + void *cb_ctx); void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry); struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, @@ -1405,6 +1501,9 @@ struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *cb_ctx); +int flow_dv_tag_match_cb(struct mlx5_hlist *list, + struct mlx5_hlist_entry *entry, uint64_t key, + void *cb_ctx); void flow_dv_tag_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry); @@ -1418,6 +1517,9 @@ void flow_dv_modify_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx); +int flow_dv_mreg_match_cb(struct mlx5_hlist *list, + struct mlx5_hlist_entry *entry, uint64_t key, + void *cb_ctx); void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry); @@ -1468,4 +1570,15 @@ void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, struct mlx5_cache_entry *entry); struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx); +int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + struct rte_flow_error *error); + +void flow_release_workspace(void *data); +int mlx5_flow_os_init_workspace_once(void); +void *mlx5_flow_os_get_specific_workspace(void); +int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); +void mlx5_flow_os_release_workspace(void); + + #endif /* RTE_PMD_MLX5_FLOW_H_ */