X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_flow.h;h=7559810d0181b0ee13206fb55f06f497e5cd4c58;hb=5fc66630bed5db8b0e2507e7324f1c8f98e0dd9a;hp=3d7fcf706ea80e28913fa8c798a7f95566ab01db;hpb=d53aa89aea9135c41de42e737c25b8cecbcaa944;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 3d7fcf706e..7559810d01 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -21,9 +21,55 @@ #pragma GCC diagnostic error "-Wpedantic" #endif +#include +#include + #include "mlx5.h" #include "mlx5_prm.h" +enum modify_reg { + REG_A, + REG_B, + REG_C_0, + REG_C_1, + REG_C_2, + REG_C_3, + REG_C_4, + REG_C_5, + REG_C_6, + REG_C_7, +}; + +/* Private rte flow items. */ +enum mlx5_rte_flow_item_type { + MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, + MLX5_RTE_FLOW_ITEM_TYPE_TAG, + MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, +}; + +/* Private rte flow actions. */ +enum mlx5_rte_flow_action_type { + MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, + MLX5_RTE_FLOW_ACTION_TYPE_TAG, +}; + +/* Matches on selected register. */ +struct mlx5_rte_flow_item_tag { + uint16_t id; + rte_be32_t data; +}; + +/* Modify selected register. */ +struct mlx5_rte_flow_action_set_tag { + uint16_t id; + rte_be32_t data; +}; + +/* Matches on source queue. */ +struct mlx5_rte_flow_item_tx_queue { + uint32_t queue; +}; + /* Pattern outer Layer bits. */ #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) @@ -45,14 +91,26 @@ #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) #define MLX5_FLOW_LAYER_GRE (1u << 14) #define MLX5_FLOW_LAYER_MPLS (1u << 15) +/* List of tunnel Layer bits continued below. */ /* General pattern items bits. */ #define MLX5_FLOW_ITEM_METADATA (1u << 16) #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) +#define MLX5_FLOW_ITEM_TAG (1u << 18) /* Pattern MISC bits. */ -#define MLX5_FLOW_LAYER_ICMP (1u << 18) -#define MLX5_FLOW_LAYER_ICMP6 (1u << 19) +#define MLX5_FLOW_LAYER_ICMP (1u << 19) +#define MLX5_FLOW_LAYER_ICMP6 (1u << 20) +#define MLX5_FLOW_LAYER_GRE_KEY (1u << 21) + +/* Pattern tunnel Layer bits (continued). */ +#define MLX5_FLOW_LAYER_IPIP (1u << 21) +#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22) +#define MLX5_FLOW_LAYER_NVGRE (1u << 23) +#define MLX5_FLOW_LAYER_GENEVE (1u << 24) + +/* Queue items. */ +#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25) /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ @@ -63,10 +121,18 @@ (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ MLX5_FLOW_LAYER_OUTER_L4) +/* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */ +#define MLX5_FLOW_LAYER_IPV4_LRO \ + (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP) +#define MLX5_FLOW_LAYER_IPV6_LRO \ + (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP) + /* Tunnel Masks. */ #define MLX5_FLOW_LAYER_TUNNEL \ (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ - MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS) + MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ + MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ + MLX5_FLOW_LAYER_GENEVE) /* Inner Masks. */ #define MLX5_FLOW_LAYER_INNER_L3 \ @@ -122,6 +188,7 @@ #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29) #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30) #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31) +#define MLX5_FLOW_ACTION_SET_TAG (1ull << 32) #define MLX5_FLOW_FATE_ACTIONS \ (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ @@ -133,11 +200,13 @@ #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \ MLX5_FLOW_ACTION_NVGRE_ENCAP | \ - MLX5_FLOW_ACTION_RAW_ENCAP) + MLX5_FLOW_ACTION_RAW_ENCAP | \ + MLX5_FLOW_ACTION_OF_PUSH_VLAN) #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \ MLX5_FLOW_ACTION_NVGRE_DECAP | \ - MLX5_FLOW_ACTION_RAW_DECAP) + MLX5_FLOW_ACTION_RAW_DECAP | \ + MLX5_FLOW_ACTION_OF_POP_VLAN) #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ MLX5_FLOW_ACTION_SET_IPV4_DST | \ @@ -152,7 +221,12 @@ MLX5_FLOW_ACTION_INC_TCP_SEQ | \ MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ MLX5_FLOW_ACTION_INC_TCP_ACK | \ - MLX5_FLOW_ACTION_DEC_TCP_ACK) + MLX5_FLOW_ACTION_DEC_TCP_ACK | \ + MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ + MLX5_FLOW_ACTION_SET_TAG) + +#define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ + MLX5_FLOW_ACTION_OF_PUSH_VLAN) #ifndef IPPROTO_MPLS #define IPPROTO_MPLS 137 @@ -165,6 +239,9 @@ #define MLX5_UDP_PORT_VXLAN 4789 #define MLX5_UDP_PORT_VXLAN_GPE 4790 +/* UDP port numbers for GENEVE. */ +#define MLX5_UDP_PORT_GENEVE 6081 + /* Priority reserved for default flows. */ #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1) @@ -197,6 +274,33 @@ /* IBV hash source bits for IPV6. */ #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) + +/* Geneve header first 16Bit */ +#define MLX5_GENEVE_VER_MASK 0x3 +#define MLX5_GENEVE_VER_SHIFT 14 +#define MLX5_GENEVE_VER_VAL(a) \ + (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) +#define MLX5_GENEVE_OPTLEN_MASK 0x3F +#define MLX5_GENEVE_OPTLEN_SHIFT 7 +#define MLX5_GENEVE_OPTLEN_VAL(a) \ + (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) +#define MLX5_GENEVE_OAMF_MASK 0x1 +#define MLX5_GENEVE_OAMF_SHIFT 7 +#define MLX5_GENEVE_OAMF_VAL(a) \ + (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) +#define MLX5_GENEVE_CRITO_MASK 0x1 +#define MLX5_GENEVE_CRITO_SHIFT 6 +#define MLX5_GENEVE_CRITO_VAL(a) \ + (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) +#define MLX5_GENEVE_RSVD_MASK 0x3F +#define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) +/* + * The length of the Geneve options fields, expressed in four byte multiples, + * not including the eight byte fixed tunnel. + */ +#define MLX5_GENEVE_OPT_LEN_0 14 +#define MLX5_GENEVE_OPT_LEN_1 63 + enum mlx5_flow_drv_type { MLX5_FLOW_TYPE_MIN, MLX5_FLOW_TYPE_DV, @@ -289,6 +393,16 @@ struct mlx5_flow_dv_port_id_action_resource { uint32_t port_id; /**< Port ID value. */ }; +/* Push VLAN action resource structure */ +struct mlx5_flow_dv_push_vlan_action_resource { + LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next; + /* Pointer to next element. */ + rte_atomic32_t refcnt; /**< Reference counter. */ + void *action; /**< Direct verbs action object. */ + uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ + rte_be32_t vlan_tag; /**< VLAN tag value. */ +}; + /* * Max number of actions per DV flow. * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED @@ -313,6 +427,10 @@ struct mlx5_flow_dv { /**< Pointer to the jump action resource. */ struct mlx5_flow_dv_port_id_action_resource *port_id_action; /**< Pointer to port ID action resource. */ + struct mlx5_vf_vlan vf_vlan; + /**< Structure for VF VLAN workaround. */ + struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; + /**< Pointer to push VLAN action resource in cache. */ #ifdef HAVE_IBV_FLOW_DV_SUPPORT void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ @@ -338,6 +456,8 @@ struct mlx5_flow_verbs { struct ibv_flow *flow; /**< Verbs flow pointer. */ struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */ uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */ + struct mlx5_vf_vlan vf_vlan; + /**< Structure for VF VLAN workaround. */ }; /** Device flow structure. */ @@ -346,31 +466,15 @@ struct mlx5_flow { struct rte_flow *flow; /**< Pointer to the main flow. */ uint64_t layers; /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ + uint64_t actions; + /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ union { #ifdef HAVE_IBV_FLOW_DV_SUPPORT struct mlx5_flow_dv dv; #endif struct mlx5_flow_verbs verbs; }; -}; - -/* Counters information. */ -struct mlx5_flow_counter { - LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */ - uint32_t shared:1; /**< Share counter ID with other flow rules. */ - uint32_t ref_cnt:31; /**< Reference counter. */ - uint32_t id; /**< Counter ID. */ - union { /**< Holds the counters for the rule. */ -#if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) - struct ibv_counter_set *cs; -#elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) - struct ibv_counters *cs; -#endif - struct mlx5_devx_counter_set *dcs; - }; - uint64_t hits; /**< Number of packets matched by the rule. */ - uint64_t bytes; /**< Number of bytes matched by the rule. */ - void *action; /**< Pointer to the dv action. */ + bool external; /**< true if the flow is created external to PMD. */ }; /* Flow structure. */ @@ -385,18 +489,18 @@ struct rte_flow { uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */ LIST_HEAD(dev_flows, mlx5_flow) dev_flows; /**< Device flows that are part of the flow. */ - uint64_t actions; - /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ uint8_t ingress; /**< 1 if the flow is ingress. */ uint32_t group; /**< The group index. */ uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ + uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */ }; typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_item items[], const struct rte_flow_action actions[], + bool external, struct rte_flow_error *error); typedef struct mlx5_flow *(*mlx5_flow_prepare_t) (const struct rte_flow_attr *attr, const struct rte_flow_item items[], @@ -428,13 +532,29 @@ struct mlx5_flow_driver_ops { mlx5_flow_query_t query; }; +#define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \ + [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) +#define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \ + [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)]) + /* mlx5_flow.c */ +struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void); +void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool); +uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id); +uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, + uint32_t id); +int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, + bool external, uint32_t group, uint32_t *table, + struct rte_flow_error *error); uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel, uint64_t layer_types, uint64_t hash_fields); uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, uint32_t subpriority); +const struct rte_flow_action *mlx5_flow_find_action + (const struct rte_flow_action *actions, + enum rte_flow_action_type action); int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, struct rte_flow_error *error); @@ -474,6 +594,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, struct rte_flow_error *error); +int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error); int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_item_ipv4 *acc_mask, @@ -498,6 +622,7 @@ int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, struct rte_flow_error *error); int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, uint64_t item_flags, + struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, uint64_t item_flags, @@ -514,5 +639,12 @@ int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, uint64_t item_flags, uint8_t target_protocol, struct rte_flow_error *error); - +int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, + uint64_t item_flags, + uint8_t target_protocol, + struct rte_flow_error *error); +int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, + uint64_t item_flags, + struct rte_eth_dev *dev, + struct rte_flow_error *error); #endif /* RTE_PMD_MLX5_FLOW_H_ */