X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_rxtx.h;h=6876c1bc4a5a8a1816eb5c106a733e302a0d3dcd;hb=c4c2bc7e2e49ffe1169b22b537c495354e2c71ea;hp=35a22b6dea742a17fd45bf3d7307f116e025e14e;hpb=9d60f54569fd836cba697661d71935b6305a4d91;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 35a22b6dea..6876c1bc4a 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -143,7 +143,7 @@ struct mlx5_rxq_data { struct mlx5_rxq_stats stats; rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ - void *cq_uar; /* CQ user access region. */ + void *cq_uar; /* Verbs CQ user access region. */ uint32_t cqn; /* CQ number. */ uint8_t cq_arm_sn; /* CQ arm seq number. */ #ifndef RTE_ARCH_64 @@ -155,34 +155,12 @@ struct mlx5_rxq_data { int32_t flow_meta_offset; } __rte_cache_aligned; -enum mlx5_rxq_obj_type { - MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */ - MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */ - MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN, - /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */ -}; - enum mlx5_rxq_type { MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */ MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ MLX5_RXQ_TYPE_UNDEFINED, }; -/* Verbs/DevX Rx queue elements. */ -struct mlx5_rxq_obj { - LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ - struct ibv_cq *cq; /* Completion Queue. */ - enum mlx5_rxq_obj_type type; - RTE_STD_C11 - union { - struct ibv_wq *wq; /* Work Queue. */ - struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */ - }; - struct ibv_comp_channel *channel; -}; - /* RX queue control descriptor. */ struct mlx5_rxq_ctrl { struct mlx5_rxq_data rxq; /* Data path structure. */ @@ -193,54 +171,21 @@ struct mlx5_rxq_ctrl { enum mlx5_rxq_type type; /* Rxq type. */ unsigned int socket; /* CPU socket ID for allocations. */ unsigned int irq:1; /* Whether IRQ is enabled. */ - unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */ uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ uint32_t wqn; /* WQ number. */ uint16_t dump_file_n; /* Number of dump files. */ - uint32_t dbr_umem_id; /* Storing door-bell information, */ - uint64_t dbr_offset; /* needed when freeing door-bell. */ - struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */ + struct mlx5_devx_dbr_page *rq_dbrec_page; + uint64_t rq_dbr_offset; + /* Storing RQ door-bell information, needed when freeing door-bell. */ + struct mlx5_devx_dbr_page *cq_dbrec_page; + uint64_t cq_dbr_offset; + /* Storing CQ door-bell information, needed when freeing door-bell. */ + void *wq_umem; /* WQ buffer registration info. */ + void *cq_umem; /* CQ buffer registration info. */ struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ }; -enum mlx5_ind_tbl_type { - MLX5_IND_TBL_TYPE_IBV, - MLX5_IND_TBL_TYPE_DEVX, -}; - -/* Indirection table. */ -struct mlx5_ind_table_obj { - LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - enum mlx5_ind_tbl_type type; - RTE_STD_C11 - union { - struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */ - struct mlx5_devx_obj *rqt; /* DevX RQT object. */ - }; - uint32_t queues_n; /**< Number of queues in the list. */ - uint16_t queues[]; /**< Queue list. */ -}; - -/* Hash Rx queue. */ -struct mlx5_hrxq { - ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ - RTE_STD_C11 - union { - struct ibv_qp *qp; /* Verbs queue pair. */ - struct mlx5_devx_obj *tir; /* DevX TIR object. */ - }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - void *action; /* DV QP action pointer. */ -#endif - uint64_t hash_fields; /* Verbs Hash fields. */ - uint32_t rss_key_len; /* Hash key length in bytes. */ - uint8_t rss_key[]; /* Hash key. */ -}; - /* TX queue send local data. */ __extension__ struct mlx5_txq_local { @@ -337,8 +282,8 @@ struct mlx5_txq_obj { RTE_STD_C11 union { struct { - struct ibv_cq *cq; /* Completion Queue. */ - struct ibv_qp *qp; /* Queue Pair. */ + void *cq; /* Completion Queue. */ + void *qp; /* Queue Pair. */ }; struct { struct mlx5_devx_obj *sq; @@ -348,12 +293,12 @@ struct mlx5_txq_obj { struct { struct rte_eth_dev *dev; struct mlx5_devx_obj *cq_devx; - struct mlx5dv_devx_umem *cq_umem; + void *cq_umem; void *cq_buf; int64_t cq_dbrec_offset; struct mlx5_devx_dbr_page *cq_dbrec_page; struct mlx5_devx_obj *sq_devx; - struct mlx5dv_devx_umem *sq_umem; + void *sq_umem; void *sq_buf; int64_t sq_dbrec_offset; struct mlx5_devx_dbr_page *sq_dbrec_page; @@ -389,8 +334,13 @@ extern uint8_t rss_hash_default_key[]; int mlx5_check_mprq_support(struct rte_eth_dev *dev); int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); int mlx5_mprq_enabled(struct rte_eth_dev *dev); +unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data); int mlx5_mprq_free_mp(struct rte_eth_dev *dev); int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); +int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, struct rte_mempool *mp); @@ -402,8 +352,6 @@ int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); -struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx, - enum mlx5_rxq_obj_type type); int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, @@ -417,6 +365,11 @@ int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); int mlx5_rxq_verify(struct rte_eth_dev *dev); int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); +struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev, + const uint16_t *queues, + uint32_t queues_n); +int mlx5_ind_table_obj_release(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl); uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev, const uint8_t *rss_key, uint32_t rss_key_len, uint64_t hash_fields, @@ -429,8 +382,8 @@ uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); int mlx5_hrxq_verify(struct rte_eth_dev *dev); enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); -struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev); -void mlx5_hrxq_drop_release(struct rte_eth_dev *dev); +struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); +void mlx5_drop_action_destroy(struct rte_eth_dev *dev); uint64_t mlx5_get_rx_port_offloads(void); uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); @@ -438,6 +391,10 @@ void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); /* mlx5_txq.c */ +int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_txconf *conf); int mlx5_tx_hairpin_queue_setup @@ -670,7 +627,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, uint64_t *dst = MLX5_TX_BFREG(txq); volatile uint64_t *src = ((volatile uint64_t *)wqe); - rte_cio_wmb(); + rte_io_wmb(); *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); /* Ensure ordering between DB record and BF copy. */ rte_wmb();