X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_rxtx.h;h=bcb159510c26c70628e84074ff79a8ada6761d9f;hb=42dcd453d9b63841a5460a6ca3872eb7648d73bd;hp=6d135dd80f20c7dbd4c7effcc6eb4d4d324c42f3;hpb=f6dee900589f55fc147a5cc4baf1adb52e7dc4da;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 6d135dd80f..bcb159510c 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -68,7 +68,7 @@ struct rxq_zip { /* Multi-Packet RQ buffer header. */ struct mlx5_mprq_buf { struct rte_mempool *mp; - rte_atomic16_t refcnt; /* Atomically accessed refcnt. */ + uint16_t refcnt; /* Atomically accessed refcnt. */ uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ struct rte_mbuf_ext_shared_info shinfos[]; /* @@ -151,6 +151,8 @@ struct mlx5_rxq_data { /* CQ (UAR) access lock required for 32bit implementations */ #endif uint32_t tunnel; /* Tunnel information. */ + int timestamp_offset; /* Dynamic mbuf field for timestamp. */ + uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */ uint64_t flow_meta_mask; int32_t flow_meta_offset; } __rte_cache_aligned; @@ -165,7 +167,7 @@ enum mlx5_rxq_type { struct mlx5_rxq_ctrl { struct mlx5_rxq_data rxq; /* Data path structure. */ LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ struct mlx5_priv *priv; /* Back pointer to private data. */ enum mlx5_rxq_type type; /* Rxq type. */ @@ -186,43 +188,6 @@ struct mlx5_rxq_ctrl { struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ }; -enum mlx5_ind_tbl_type { - MLX5_IND_TBL_TYPE_IBV, - MLX5_IND_TBL_TYPE_DEVX, -}; - -/* Indirection table. */ -struct mlx5_ind_table_obj { - LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - enum mlx5_ind_tbl_type type; - RTE_STD_C11 - union { - void *ind_table; /**< Indirection table. */ - struct mlx5_devx_obj *rqt; /* DevX RQT object. */ - }; - uint32_t queues_n; /**< Number of queues in the list. */ - uint16_t queues[]; /**< Queue list. */ -}; - -/* Hash Rx queue. */ -struct mlx5_hrxq { - ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ - RTE_STD_C11 - union { - void *qp; /* Verbs queue pair. */ - struct mlx5_devx_obj *tir; /* DevX TIR object. */ - }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - void *action; /* DV QP action pointer. */ -#endif - uint64_t hash_fields; /* Verbs Hash fields. */ - uint32_t rss_key_len; /* Hash key length in bytes. */ - uint8_t rss_key[]; /* Hash key. */ -}; - /* TX queue send local data. */ __extension__ struct mlx5_txq_local { @@ -298,55 +263,15 @@ struct mlx5_txq_data { /* Storage for queued packets, must be the last field. */ } __rte_cache_aligned; -enum mlx5_txq_obj_type { - MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */ - MLX5_TXQ_OBJ_TYPE_DEVX_SQ, /* mlx5_txq_obj with mlx5_devx_sq. */ - MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN, - /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */ -}; - enum mlx5_txq_type { MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */ MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ }; -/* Verbs/DevX Tx queue elements. */ -struct mlx5_txq_obj { - LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ - enum mlx5_txq_obj_type type; /* The txq object type. */ - RTE_STD_C11 - union { - struct { - void *cq; /* Completion Queue. */ - void *qp; /* Queue Pair. */ - }; - struct { - struct mlx5_devx_obj *sq; - /* DevX object for Sx queue. */ - struct mlx5_devx_obj *tis; /* The TIS object. */ - }; - struct { - struct rte_eth_dev *dev; - struct mlx5_devx_obj *cq_devx; - void *cq_umem; - void *cq_buf; - int64_t cq_dbrec_offset; - struct mlx5_devx_dbr_page *cq_dbrec_page; - struct mlx5_devx_obj *sq_devx; - void *sq_umem; - void *sq_buf; - int64_t sq_dbrec_offset; - struct mlx5_devx_dbr_page *sq_dbrec_page; - }; - }; -}; - /* TX queue control descriptor. */ struct mlx5_txq_ctrl { LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ unsigned int socket; /* CPU socket ID for allocations. */ enum mlx5_txq_type type; /* The txq ctrl type. */ unsigned int max_inline_data; /* Max inline data. */ @@ -371,6 +296,7 @@ extern uint8_t rss_hash_default_key[]; int mlx5_check_mprq_support(struct rte_eth_dev *dev); int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); int mlx5_mprq_enabled(struct rte_eth_dev *dev); +unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data); int mlx5_mprq_free_mp(struct rte_eth_dev *dev); int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); @@ -401,6 +327,11 @@ int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); int mlx5_rxq_verify(struct rte_eth_dev *dev); int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); +struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev, + const uint16_t *queues, + uint32_t queues_n); +int mlx5_ind_table_obj_release(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl); uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev, const uint8_t *rss_key, uint32_t rss_key_len, uint64_t hash_fields, @@ -413,8 +344,8 @@ uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev, int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); int mlx5_hrxq_verify(struct rte_eth_dev *dev); enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx); -struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev); -void mlx5_hrxq_drop_release(struct rte_eth_dev *dev); +struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); +void mlx5_drop_action_destroy(struct rte_eth_dev *dev); uint64_t mlx5_get_rx_port_offloads(void); uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); @@ -432,12 +363,9 @@ int mlx5_tx_hairpin_queue_setup (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, const struct rte_eth_hairpin_conf *hairpin_conf); void mlx5_tx_queue_release(void *dpdk_txq); +void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl); int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev); -struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx, - enum mlx5_txq_obj_type type); -struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx); -int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv); int mlx5_txq_obj_verify(struct rte_eth_dev *dev); struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, @@ -658,7 +586,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, uint64_t *dst = MLX5_TX_BFREG(txq); volatile uint64_t *src = ((volatile uint64_t *)wqe); - rte_cio_wmb(); + rte_io_wmb(); *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); /* Ensure ordering between DB record and BF copy. */ rte_wmb(); @@ -755,4 +683,21 @@ mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts) return ci; } +/** + * Set timestamp in mbuf dynamic field. + * + * @param mbuf + * Structure to write into. + * @param offset + * Dynamic field offset in mbuf structure. + * @param timestamp + * Value to write. + */ +static __rte_always_inline void +mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset, + rte_mbuf_timestamp_t timestamp) +{ + *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp; +} + #endif /* RTE_PMD_MLX5_RXTX_H_ */