X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_rxtx.h;h=d443db4279c3f4a299a6ffc14d973376fc00e666;hb=151cbe3aabf9e1a71e02827e5e1ff0814275019a;hp=3d79c18b606d097bf62da228dc826619b1371c37;hpb=2d77cb615b2c126828c4e98b686523bf0139c1c1;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 3d79c18b60..d443db4279 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -10,45 +10,30 @@ #include #include -/* Verbs header. */ -/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ -#ifdef PEDANTIC -#pragma GCC diagnostic ignored "-Wpedantic" -#endif -#include -#include -#ifdef PEDANTIC -#pragma GCC diagnostic error "-Wpedantic" -#endif - #include #include #include #include -#include #include #include #include +#include +#include +#include +#include +#include +#include + +#include "mlx5_defs.h" #include "mlx5_utils.h" #include "mlx5.h" -#include "mlx5_mr.h" #include "mlx5_autoconf.h" -#include "mlx5_defs.h" -#include "mlx5_prm.h" -#include "mlx5_glue.h" +#include "mlx5_mr.h" -/* Support tunnel matching. */ -#define MLX5_FLOW_TUNNEL 5 -struct mlx5_rxq_stats { -#ifdef MLX5_PMD_SOFT_COUNTERS - uint64_t ipackets; /**< Total of successfully received packets. */ - uint64_t ibytes; /**< Total of successfully received bytes. */ -#endif - uint64_t idropped; /**< Total of packets dropped when RX ring full. */ - uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ -}; +/* Mbuf dynamic flag offset for inline. */ +extern uint64_t rte_net_mlx5_dynf_inline_mask; struct mlx5_txq_stats { #ifdef MLX5_PMD_SOFT_COUNTERS @@ -60,132 +45,19 @@ struct mlx5_txq_stats { struct mlx5_priv; -/* Compressed CQE context. */ -struct rxq_zip { - uint16_t ai; /* Array index. */ - uint16_t ca; /* Current array index. */ - uint16_t na; /* Next array index. */ - uint16_t cq_ci; /* The next CQE. */ - uint32_t cqe_cnt; /* Number of CQEs. */ -}; - -/* Multi-Packet RQ buffer header. */ -struct mlx5_mprq_buf { - struct rte_mempool *mp; - rte_atomic16_t refcnt; /* Atomically accessed refcnt. */ - uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */ -} __rte_cache_aligned; - -/* Get pointer to the first stride. */ -#define mlx5_mprq_buf_addr(ptr) ((ptr) + 1) - -enum mlx5_rxq_err_state { - MLX5_RXQ_ERR_STATE_NO_ERROR = 0, - MLX5_RXQ_ERR_STATE_NEED_RESET, - MLX5_RXQ_ERR_STATE_NEED_READY, -}; - -/* RX queue descriptor. */ -struct mlx5_rxq_data { - unsigned int csum:1; /* Enable checksum offloading. */ - unsigned int hw_timestamp:1; /* Enable HW timestamp. */ - unsigned int vlan_strip:1; /* Enable VLAN stripping. */ - unsigned int crc_present:1; /* CRC must be subtracted. */ - unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */ - unsigned int cqe_n:4; /* Log 2 of CQ elements. */ - unsigned int elts_n:4; /* Log 2 of Mbufs. */ - unsigned int rss_hash:1; /* RSS hash result is enabled. */ - unsigned int mark:1; /* Marked flow available on the queue. */ - unsigned int strd_num_n:5; /* Log 2 of the number of stride. */ - unsigned int strd_sz_n:4; /* Log 2 of stride size. */ - unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ - unsigned int err_state:2; /* enum mlx5_rxq_err_state. */ - unsigned int :4; /* Remaining bits. */ - volatile uint32_t *rq_db; - volatile uint32_t *cq_db; - uint16_t port_id; - uint32_t rq_ci; - uint16_t consumed_strd; /* Number of consumed strides in WQE. */ - uint32_t rq_pi; - uint32_t cq_ci; - uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ - union { - struct rxq_zip zip; /* Compressed context. */ - uint16_t decompressed; - /* Number of ready mbufs decompressed from the CQ. */ - }; - struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ - uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ - volatile void *wqes; - volatile struct mlx5_cqe(*cqes)[]; - RTE_STD_C11 - union { - struct rte_mbuf *(*elts)[]; - struct mlx5_mprq_buf *(*mprq_bufs)[]; - }; - struct rte_mempool *mp; - struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ - struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ - uint16_t idx; /* Queue index. */ - struct mlx5_rxq_stats stats; - uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */ - struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ - void *cq_uar; /* CQ user access region. */ - uint32_t cqn; /* CQ number. */ - uint8_t cq_arm_sn; /* CQ arm seq number. */ -#ifndef RTE_ARCH_64 - rte_spinlock_t *uar_lock_cq; - /* CQ (UAR) access lock required for 32bit implementations */ -#endif - uint32_t tunnel; /* Tunnel information. */ -} __rte_cache_aligned; - -/* Verbs Rx queue elements. */ -struct mlx5_rxq_ibv { - LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ - struct ibv_cq *cq; /* Completion Queue. */ - struct ibv_wq *wq; /* Work Queue. */ - struct ibv_comp_channel *channel; -}; - -/* RX queue control descriptor. */ -struct mlx5_rxq_ctrl { - struct mlx5_rxq_data rxq; /* Data path structure. */ - LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_rxq_ibv *ibv; /* Verbs elements. */ - struct mlx5_priv *priv; /* Back pointer to private data. */ - unsigned int socket; /* CPU socket ID for allocations. */ - unsigned int irq:1; /* Whether IRQ is enabled. */ - uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ - uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ - uint32_t wqn; /* WQ number. */ - uint16_t dump_file_n; /* Number of dump files. */ -}; - -/* Indirection table. */ -struct mlx5_ind_table_ibv { - LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */ - uint32_t queues_n; /**< Number of queues in the list. */ - uint16_t queues[]; /**< Queue list. */ -}; - -/* Hash Rx queue. */ -struct mlx5_hrxq { - LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */ - struct ibv_qp *qp; /* Verbs queue pair. */ -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - void *action; /* DV QP action pointer. */ -#endif - uint64_t hash_fields; /* Verbs Hash fields. */ - uint32_t rss_key_len; /* Hash key length in bytes. */ - uint8_t rss_key[]; /* Hash key. */ +/* TX queue send local data. */ +__extension__ +struct mlx5_txq_local { + struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */ + struct rte_mbuf *mbuf; /* first mbuf to process. */ + uint16_t pkts_copy; /* packets copied to elts. */ + uint16_t pkts_sent; /* packets sent. */ + uint16_t pkts_loop; /* packets sent on loop entry. */ + uint16_t elts_free; /* available elts remain. */ + uint16_t wqe_free; /* available wqe remain. */ + uint16_t mbuf_off; /* data offset in current mbuf. */ + uint16_t mbuf_nseg; /* number of remaining mbuf. */ + uint16_t mbuf_free; /* number of inline mbufs to free. */ }; /* TX queue descriptor. */ @@ -193,132 +65,120 @@ __extension__ struct mlx5_txq_data { uint16_t elts_head; /* Current counter in (*elts)[]. */ uint16_t elts_tail; /* Counter of first element awaiting completion. */ - uint16_t elts_comp; /* Counter since last completion request. */ - uint16_t mpw_comp; /* WQ index since last completion request. */ - uint16_t cq_ci; /* Consumer index for completion queue. */ -#ifndef NDEBUG - uint16_t cq_pi; /* Producer index for completion queue. */ -#endif + uint16_t elts_comp; /* elts index since last completion request. */ + uint16_t elts_s; /* Number of mbuf elements. */ + uint16_t elts_m; /* Mask for mbuf elements indices. */ + /* Fields related to elts mbuf storage. */ uint16_t wqe_ci; /* Consumer index for work queue. */ uint16_t wqe_pi; /* Producer index for work queue. */ - uint16_t elts_n:4; /* (*elts)[] length (in log2). */ + uint16_t wqe_s; /* Number of WQ elements. */ + uint16_t wqe_m; /* Mask Number for WQ elements. */ + uint16_t wqe_comp; /* WQE index since last completion request. */ + uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */ + /* WQ related fields. */ + uint16_t cq_ci; /* Consumer index for completion queue. */ + uint16_t cq_pi; /* Production index for completion queue. */ + uint16_t cqe_s; /* Number of CQ elements. */ + uint16_t cqe_m; /* Mask for CQ indices. */ + /* CQ related fields. */ + uint16_t elts_n:4; /* elts[] length (in log2). */ uint16_t cqe_n:4; /* Number of CQ elements (in log2). */ - uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */ + uint16_t wqe_n:4; /* Number of WQ elements (in log2). */ uint16_t tso_en:1; /* When set hardware TSO is enabled. */ uint16_t tunnel_en:1; /* When set TX offload for tunneled packets are supported. */ uint16_t swp_en:1; /* Whether SW parser is enabled. */ - uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ - uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */ - uint16_t inline_max_packet_sz; /* Max packet size for inlining. */ + uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */ + uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */ + uint16_t db_heu:1; /* Doorbell heuristic write barrier. */ + uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */ + uint16_t inlen_send; /* Ordinary send data inline size. */ + uint16_t inlen_empw; /* eMPW max packet size to inline. */ + uint16_t inlen_mode; /* Minimal data length to inline. */ uint32_t qp_num_8s; /* QP number shifted by 8. */ uint64_t offloads; /* Offloads for Tx Queue. */ struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ - volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */ - volatile void *wqes; /* Work queue (use volatile to write into). */ + struct mlx5_wqe *wqes; /* Work queue. */ + struct mlx5_wqe *wqes_end; /* Work queue array limit. */ +#ifdef RTE_LIBRTE_MLX5_DEBUG + uint32_t *fcqs; /* Free completion queue (debug extended). */ +#else + uint16_t *fcqs; /* Free completion queue. */ +#endif + volatile struct mlx5_cqe *cqes; /* Completion queue. */ volatile uint32_t *qp_db; /* Work queue doorbell. */ volatile uint32_t *cq_db; /* Completion queue doorbell. */ - struct rte_mbuf *(*elts)[]; /* TX elements. */ uint16_t port_id; /* Port ID of device. */ uint16_t idx; /* Queue index. */ + uint64_t ts_mask; /* Timestamp flag dynamic mask. */ + int32_t ts_offset; /* Timestamp field dynamic offset. */ + struct mlx5_dev_ctx_shared *sh; /* Shared context. */ struct mlx5_txq_stats stats; /* TX queue counters. */ #ifndef RTE_ARCH_64 rte_spinlock_t *uar_lock; /* UAR access lock required for 32bit implementations */ #endif + struct rte_mbuf *elts[0]; + /* Storage for queued packets, must be the last field. */ } __rte_cache_aligned; -/* Verbs Rx queue elements. */ -struct mlx5_txq_ibv { - LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ - struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ - struct ibv_cq *cq; /* Completion Queue. */ - struct ibv_qp *qp; /* Queue Pair. */ +enum mlx5_txq_type { + MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */ + MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */ }; /* TX queue control descriptor. */ struct mlx5_txq_ctrl { - struct mlx5_txq_data txq; /* Data path structure. */ LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */ - rte_atomic32_t refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ unsigned int socket; /* CPU socket ID for allocations. */ + enum mlx5_txq_type type; /* The txq ctrl type. */ unsigned int max_inline_data; /* Max inline data. */ unsigned int max_tso_header; /* Max TSO header size. */ - struct mlx5_txq_ibv *ibv; /* Verbs queue object. */ + struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */ struct mlx5_priv *priv; /* Back pointer to private data. */ off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */ void *bf_reg; /* BlueFlame register from Verbs. */ - uint32_t cqn; /* CQ number. */ uint16_t dump_file_n; /* Number of dump files. */ + struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ + uint32_t hairpin_status; /* Hairpin binding status. */ + struct mlx5_txq_data txq; /* Data path structure. */ + /* Must be the last field in the structure, contains elts[]. */ }; #define MLX5_TX_BFREG(txq) \ (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx]) -/* mlx5_rxq.c */ - -extern uint8_t rss_hash_default_key[]; - -int mlx5_check_mprq_support(struct rte_eth_dev *dev); -int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); -int mlx5_mprq_enabled(struct rte_eth_dev *dev); -int mlx5_mprq_free_mp(struct rte_eth_dev *dev); -int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); -int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, - unsigned int socket, const struct rte_eth_rxconf *conf, - struct rte_mempool *mp); -void mlx5_rx_queue_release(void *dpdk_rxq); -int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); -void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); -int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); -int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); -struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx); -int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev); -struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, - uint16_t desc, unsigned int socket, - const struct rte_eth_rxconf *conf, - struct rte_mempool *mp); -struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); -int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); -int mlx5_rxq_verify(struct rte_eth_dev *dev); -int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); -int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev); -struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev, - const uint8_t *rss_key, uint32_t rss_key_len, - uint64_t hash_fields, - const uint16_t *queues, uint32_t queues_n, - int tunnel __rte_unused); -struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev, - const uint8_t *rss_key, uint32_t rss_key_len, - uint64_t hash_fields, - const uint16_t *queues, uint32_t queues_n); -int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq); -int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev); -struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev); -void mlx5_hrxq_drop_release(struct rte_eth_dev *dev); -uint64_t mlx5_get_rx_port_offloads(void); -uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); - /* mlx5_txq.c */ +int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_txconf *conf); +int mlx5_tx_hairpin_queue_setup + (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + const struct rte_eth_hairpin_conf *hairpin_conf); void mlx5_tx_queue_release(void *dpdk_txq); +void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl); int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); -struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx); -struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx); -int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv); -int mlx5_txq_ibv_verify(struct rte_eth_dev *dev); +void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev); +int mlx5_txq_obj_verify(struct rte_eth_dev *dev); struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_txconf *conf); +struct mlx5_txq_ctrl *mlx5_txq_hairpin_new + (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + const struct rte_eth_hairpin_conf *hairpin_conf); struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx); int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx); int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx); int mlx5_txq_verify(struct rte_eth_dev *dev); void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl); +void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl); uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev); +void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev); /* mlx5_rxtx.c */ @@ -329,52 +189,21 @@ extern uint8_t mlx5_swp_types_table[]; void mlx5_set_ptype_table(void); void mlx5_set_cksum_table(void); void mlx5_set_swp_types_table(void); -uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -__rte_noinline uint16_t mlx5_tx_error_cqe_handle(struct mlx5_txq_data *txq, - volatile struct mlx5_err_cqe *err_cqe); -uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); -void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq); -__rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, - uint8_t mbuf_prepare); -void mlx5_mprq_buf_free_cb(void *addr, void *opaque); -void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); -uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, - uint16_t pkts_n); uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n); -uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, - uint16_t pkts_n); -int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset); -uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); void mlx5_dump_debug_information(const char *path, const char *title, const void *buf, unsigned int len); int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev, const struct mlx5_mp_arg_queue_state_modify *sm); - -/* Vectorized version of mlx5_rxtx.c */ -int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev); -int mlx5_check_vec_tx_support(struct rte_eth_dev *dev); -int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); -int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); -uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); -uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, - uint16_t pkts_n); +void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo); +int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, + struct rte_eth_burst_mode *mode); /* mlx5_mr.c */ void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl); -uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr); uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb); uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, struct rte_mempool *mp); @@ -439,160 +268,6 @@ __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock) #endif -/* CQE status. */ -enum mlx5_cqe_status { - MLX5_CQE_STATUS_SW_OWN, - MLX5_CQE_STATUS_HW_OWN, - MLX5_CQE_STATUS_ERR, -}; - -/** - * Check whether CQE is valid. - * - * @param cqe - * Pointer to CQE. - * @param cqes_n - * Size of completion queue. - * @param ci - * Consumer index. - * - * @return - * The CQE status. - */ -static __rte_always_inline enum mlx5_cqe_status -check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, - const uint16_t ci) -{ - const uint16_t idx = ci & cqes_n; - const uint8_t op_own = cqe->op_own; - const uint8_t op_owner = MLX5_CQE_OWNER(op_own); - const uint8_t op_code = MLX5_CQE_OPCODE(op_own); - - if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) - return MLX5_CQE_STATUS_HW_OWN; - rte_cio_rmb(); - if (unlikely(op_code == MLX5_CQE_RESP_ERR || - op_code == MLX5_CQE_REQ_ERR)) - return MLX5_CQE_STATUS_ERR; - return MLX5_CQE_STATUS_SW_OWN; -} - -/** - * Return the address of the WQE. - * - * @param txq - * Pointer to TX queue structure. - * @param wqe_ci - * WQE consumer index. - * - * @return - * WQE address. - */ -static inline uintptr_t * -tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci) -{ - ci &= ((1 << txq->wqe_n) - 1); - return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE); -} - -/** - * Handle the next CQE. - * - * @param txq - * Pointer to TX queue structure. - * - * @return - * The last Tx buffer element to free. - */ -static __rte_always_inline uint16_t -mlx5_tx_cqe_handle(struct mlx5_txq_data *txq) -{ - const unsigned int cqe_n = 1 << txq->cqe_n; - const unsigned int cqe_cnt = cqe_n - 1; - uint16_t last_elts; - union { - volatile struct mlx5_cqe *cqe; - volatile struct mlx5_err_cqe *err_cqe; - } u = { - .cqe = &(*txq->cqes)[txq->cq_ci & cqe_cnt], - }; - int ret = check_cqe(u.cqe, cqe_n, txq->cq_ci); - - if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { - if (unlikely(ret == MLX5_CQE_STATUS_ERR)) - last_elts = mlx5_tx_error_cqe_handle(txq, u.err_cqe); - else - /* Do not release buffers. */ - return txq->elts_tail; - } else { - uint16_t new_wqe_pi = rte_be_to_cpu_16(u.cqe->wqe_counter); - volatile struct mlx5_wqe_ctrl *ctrl = - (volatile struct mlx5_wqe_ctrl *) - tx_mlx5_wqe(txq, new_wqe_pi); - - /* Release completion burst buffers. */ - last_elts = ctrl->ctrl3; - txq->wqe_pi = new_wqe_pi; - txq->cq_ci++; - } - rte_compiler_barrier(); - *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci); - return last_elts; -} - -/** - * Manage TX completions. - * - * When sending a burst, mlx5_tx_burst() posts several WRs. - * - * @param txq - * Pointer to TX queue structure. - */ -static __rte_always_inline void -mlx5_tx_complete(struct mlx5_txq_data *txq) -{ - const uint16_t elts_n = 1 << txq->elts_n; - const uint16_t elts_m = elts_n - 1; - uint16_t elts_free = txq->elts_tail; - uint16_t elts_tail; - struct rte_mbuf *m, *free[elts_n]; - struct rte_mempool *pool = NULL; - unsigned int blk_n = 0; - - elts_tail = mlx5_tx_cqe_handle(txq); - assert((elts_tail & elts_m) < (1 << txq->wqe_n)); - /* Free buffers. */ - while (elts_free != elts_tail) { - m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]); - if (likely(m != NULL)) { - if (likely(m->pool == pool)) { - free[blk_n++] = m; - } else { - if (likely(pool != NULL)) - rte_mempool_put_bulk(pool, - (void *)free, - blk_n); - free[0] = m; - pool = m->pool; - blk_n = 1; - } - } - } - if (blk_n) - rte_mempool_put_bulk(pool, (void *)free, blk_n); -#ifndef NDEBUG - elts_free = txq->elts_tail; - /* Poisoning. */ - while (elts_free != elts_tail) { - memset(&(*txq->elts)[elts_free & elts_m], - 0x66, - sizeof((*txq->elts)[elts_free & elts_m])); - ++elts_free; - } -#endif - txq->elts_tail = elts_tail; -} - /** * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the * cloned mbuf is allocated is returned instead. @@ -611,35 +286,6 @@ mlx5_mb2mp(struct rte_mbuf *buf) return buf->pool; } -/** - * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx - * as mempool is pre-configured and static. - * - * @param rxq - * Pointer to Rx queue structure. - * @param addr - * Address to search. - * - * @return - * Searched LKey on success, UINT32_MAX on no match. - */ -static __rte_always_inline uint32_t -mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) -{ - struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; - uint32_t lkey; - - /* Linear search on MR cache array. */ - lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru, - MLX5_MR_CACHE_N, addr); - if (likely(lkey != UINT32_MAX)) - return lkey; - /* Take slower bottom-half (Binary Search) on miss. */ - return mlx5_rx_addr2mr_bh(rxq, addr); -} - -#define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr)) - /** * Query LKey from a packet buffer for Tx. If not found, add the mempool. * @@ -662,8 +308,8 @@ mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb) if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) mlx5_mr_flush_local_cache(mr_ctrl); /* Linear search on MR cache array. */ - lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru, - MLX5_MR_CACHE_N, addr); + lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, + MLX5_MR_CACHE_N, addr); if (likely(lkey != UINT32_MAX)) return lkey; /* Take slower bottom-half on miss. */ @@ -687,7 +333,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, uint64_t *dst = MLX5_TX_BFREG(txq); volatile uint64_t *src = ((volatile uint64_t *)wqe); - rte_cio_wmb(); + rte_io_wmb(); *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); /* Ensure ordering between DB record and BF copy. */ rte_wmb(); @@ -711,146 +357,60 @@ mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe) } /** - * Convert mbuf to Verb SWP. - * - * @param txq_data - * Pointer to the Tx queue. - * @param buf - * Pointer to the mbuf. - * @param offsets - * Pointer to the SWP header offsets. - * @param swp_types - * Pointer to the SWP header types. - */ -static __rte_always_inline void -txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf, - uint8_t *offsets, uint8_t *swp_types) -{ - const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT; - const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK; - const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG; - const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK; - const uint64_t inner_ip = - buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6); - const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 | - PKT_TX_OUTER_IPV6; - uint16_t idx; - uint16_t off; - - if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP && - tunnel != PKT_TX_TUNNEL_IP))) - return; - /* - * The index should have: - * bit[0:1] = PKT_TX_L4_MASK - * bit[4] = PKT_TX_IPV6 - * bit[8] = PKT_TX_OUTER_IPV6 - * bit[9] = PKT_TX_OUTER_UDP - */ - idx = (buf->ol_flags & ol_flags_mask) >> 52; - if (tunnel == PKT_TX_TUNNEL_UDP) - idx |= 1 << 9; - *swp_types = mlx5_swp_types_table[idx]; - /* - * Set offsets for SW parser. Since ConnectX-5, SW parser just - * complements HW parser. SW parser starts to engage only if HW parser - * can't reach a header. For the older devices, HW parser will not kick - * in if any of SWP offsets is set. Therefore, all of the L3 offsets - * should be set regardless of HW offload. - */ - off = buf->outer_l2_len + (vlan ? sizeof(struct rte_vlan_hdr) : 0); - offsets[1] = off >> 1; /* Outer L3 offset. */ - off += buf->outer_l3_len; - if (tunnel == PKT_TX_TUNNEL_UDP) - offsets[0] = off >> 1; /* Outer L4 offset. */ - if (inner_ip) { - off += buf->l2_len; - offsets[3] = off >> 1; /* Inner L3 offset. */ - if (csum_flags == PKT_TX_TCP_CKSUM || tso || - csum_flags == PKT_TX_UDP_CKSUM) { - off += buf->l3_len; - offsets[2] = off >> 1; /* Inner L4 offset. */ - } - } -} - -/** - * Convert the Checksum offloads to Verbs. - * - * @param buf - * Pointer to the mbuf. + * Convert timestamp from mbuf format to linear counter + * of Clock Queue completions (24 bits) * + * @param sh + * Pointer to the device shared context to fetch Tx + * packet pacing timestamp and parameters. + * @param ts + * Timestamp from mbuf to convert. * @return - * Converted checksum flags. + * positive or zero value - completion ID to wait + * negative value - conversion error */ -static __rte_always_inline uint8_t -txq_ol_cksum_to_cs(struct rte_mbuf *buf) +static __rte_always_inline int32_t +mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts) { - uint32_t idx; - uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK); - const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK | - PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM; - - /* - * The index should have: - * bit[0] = PKT_TX_TCP_SEG - * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM - * bit[4] = PKT_TX_IP_CKSUM - * bit[8] = PKT_TX_OUTER_IP_CKSUM - * bit[9] = tunnel - */ - idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9); - return mlx5_cksum_table[idx]; -} - -/** - * Count the number of contiguous single segment packets. - * - * @param pkts - * Pointer to array of packets. - * @param pkts_n - * Number of packets. - * - * @return - * Number of contiguous single segment packets. - */ -static __rte_always_inline unsigned int -txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n) -{ - unsigned int pos; - - if (!pkts_n) - return 0; - /* Count the number of contiguous single segment packets. */ - for (pos = 0; pos < pkts_n; ++pos) - if (NB_SEGS(pkts[pos]) > 1) + uint64_t ts, ci; + uint32_t tick; + + do { + /* + * Read atomically two uint64_t fields and compare lsb bits. + * It there is no match - the timestamp was updated in + * the service thread, data should be re-read. + */ + rte_compiler_barrier(); + ci = __atomic_load_n(&sh->txpp.ts.ci_ts, __ATOMIC_RELAXED); + ts = __atomic_load_n(&sh->txpp.ts.ts, __ATOMIC_RELAXED); + rte_compiler_barrier(); + if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH))) break; - return pos; -} - -/** - * Count the number of contiguous multi-segment packets. - * - * @param pkts - * Pointer to array of packets. - * @param pkts_n - * Number of packets. - * - * @return - * Number of contiguous multi-segment packets. - */ -static __rte_always_inline unsigned int -txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n) -{ - unsigned int pos; - - if (!pkts_n) - return 0; - /* Count the number of contiguous multi-segment packets. */ - for (pos = 0; pos < pkts_n; ++pos) - if (NB_SEGS(pkts[pos]) == 1) - break; - return pos; + } while (true); + /* Perform the skew correction, positive value to send earlier. */ + mts -= sh->txpp.skew; + mts -= ts; + if (unlikely(mts >= UINT64_MAX / 2)) { + /* We have negative integer, mts is in the past. */ + __atomic_fetch_add(&sh->txpp.err_ts_past, + 1, __ATOMIC_RELAXED); + return -1; + } + tick = sh->txpp.tick; + MLX5_ASSERT(tick); + /* Convert delta to completions, round up. */ + mts = (mts + tick - 1) / tick; + if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) { + /* We have mts is too distant future. */ + __atomic_fetch_add(&sh->txpp.err_ts_future, + 1, __ATOMIC_RELAXED); + return -1; + } + mts <<= 64 - MLX5_CQ_INDEX_WIDTH; + ci += mts; + ci >>= 64 - MLX5_CQ_INDEX_WIDTH; + return ci; } #endif /* RTE_PMD_MLX5_RXTX_H_ */