X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_rxtx.h;h=f3fe2e10c1f7d0dbb169538cec3f1065dc083046;hb=4defbc8cbb6d5b520f13ee7f2396b0a31516d370;hp=5116a15c33ba17359806bbbda65ac08598858bf1;hpb=a2854c4de12970dc351eaefe9fbd3c77d403caf7;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 5116a15c33..f3fe2e10c1 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -10,17 +10,6 @@ #include #include -/* Verbs header. */ -/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ -#ifdef PEDANTIC -#pragma GCC diagnostic ignored "-Wpedantic" -#endif -#include -#include -#ifdef PEDANTIC -#pragma GCC diagnostic error "-Wpedantic" -#endif - #include #include #include @@ -154,7 +143,7 @@ struct mlx5_rxq_data { struct mlx5_rxq_stats stats; rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ - void *cq_uar; /* CQ user access region. */ + void *cq_uar; /* Verbs CQ user access region. */ uint32_t cqn; /* CQ number. */ uint8_t cq_arm_sn; /* CQ arm seq number. */ #ifndef RTE_ARCH_64 @@ -184,14 +173,21 @@ struct mlx5_rxq_obj { LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ rte_atomic32_t refcnt; /* Reference counter. */ struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ - struct ibv_cq *cq; /* Completion Queue. */ enum mlx5_rxq_obj_type type; + int fd; /* File descriptor for event channel */ RTE_STD_C11 union { - struct ibv_wq *wq; /* Work Queue. */ - struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */ + struct { + void *wq; /* Work Queue. */ + void *ibv_cq; /* Completion Queue. */ + void *ibv_channel; + }; + struct { + struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ + struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ + void *devx_channel; + }; }; - struct ibv_comp_channel *channel; }; /* RX queue control descriptor. */ @@ -204,14 +200,20 @@ struct mlx5_rxq_ctrl { enum mlx5_rxq_type type; /* Rxq type. */ unsigned int socket; /* CPU socket ID for allocations. */ unsigned int irq:1; /* Whether IRQ is enabled. */ - unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */ + unsigned int rq_dbr_umem_id_valid:1; + unsigned int cq_dbr_umem_id_valid:1; uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */ uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ uint32_t wqn; /* WQ number. */ uint16_t dump_file_n; /* Number of dump files. */ - uint32_t dbr_umem_id; /* Storing door-bell information, */ - uint64_t dbr_offset; /* needed when freeing door-bell. */ - struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */ + uint32_t rq_dbr_umem_id; + uint64_t rq_dbr_offset; + /* Storing RQ door-bell information, needed when freeing door-bell. */ + uint32_t cq_dbr_umem_id; + uint64_t cq_dbr_offset; + /* Storing CQ door-bell information, needed when freeing door-bell. */ + void *wq_umem; /* WQ buffer registration info. */ + void *cq_umem; /* CQ buffer registration info. */ struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ }; @@ -227,7 +229,7 @@ struct mlx5_ind_table_obj { enum mlx5_ind_tbl_type type; RTE_STD_C11 union { - struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */ + void *ind_table; /**< Indirection table. */ struct mlx5_devx_obj *rqt; /* DevX RQT object. */ }; uint32_t queues_n; /**< Number of queues in the list. */ @@ -241,7 +243,7 @@ struct mlx5_hrxq { struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ RTE_STD_C11 union { - struct ibv_qp *qp; /* Verbs queue pair. */ + void *qp; /* Verbs queue pair. */ struct mlx5_devx_obj *tir; /* DevX TIR object. */ }; #ifdef HAVE_IBV_FLOW_DV_SUPPORT @@ -348,8 +350,8 @@ struct mlx5_txq_obj { RTE_STD_C11 union { struct { - struct ibv_cq *cq; /* Completion Queue. */ - struct ibv_qp *qp; /* Queue Pair. */ + void *cq; /* Completion Queue. */ + void *qp; /* Queue Pair. */ }; struct { struct mlx5_devx_obj *sq; @@ -359,12 +361,12 @@ struct mlx5_txq_obj { struct { struct rte_eth_dev *dev; struct mlx5_devx_obj *cq_devx; - struct mlx5dv_devx_umem *cq_umem; + void *cq_umem; void *cq_buf; int64_t cq_dbrec_offset; struct mlx5_devx_dbr_page *cq_dbrec_page; struct mlx5_devx_obj *sq_devx; - struct mlx5dv_devx_umem *sq_umem; + void *sq_umem; void *sq_buf; int64_t sq_dbrec_offset; struct mlx5_devx_dbr_page *sq_dbrec_page; @@ -402,6 +404,10 @@ int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); int mlx5_mprq_enabled(struct rte_eth_dev *dev); int mlx5_mprq_free_mp(struct rte_eth_dev *dev); int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); +int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, struct rte_mempool *mp); @@ -449,6 +455,10 @@ void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); /* mlx5_txq.c */ +int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); +int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_txconf *conf); int mlx5_tx_hairpin_queue_setup