X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_txpp.c;h=af77e91e4cbbc9ed5176bf0731b0ff61ab2a9b36;hb=985b479267aa;hp=bd679c2814c056fa4f3db7d1d8666567cfb9828d;hpb=a7787bb0b73f0dc83d6cf667af87ff4cc14ee9bc;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index bd679c2814..af77e91e4c 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include #include #include @@ -16,7 +16,8 @@ #include #include "mlx5.h" -#include "mlx5_rxtx.h" +#include "mlx5_rx.h" +#include "mlx5_tx.h" #include "mlx5_common_os.h" static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t), @@ -48,7 +49,7 @@ static int mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh) { MLX5_ASSERT(!sh->txpp.echan); - sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->ctx, + sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->cdev->ctx, MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); if (!sh->txpp.echan) { rte_errno = errno; @@ -103,7 +104,7 @@ mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh) MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode, sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE); sh->txpp.pp = mlx5_glue->dv_alloc_pp - (sh->ctx, sizeof(pp), &pp, + (sh->cdev->ctx, sizeof(pp), &pp, MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX); if (sh->txpp.pp == NULL) { DRV_LOG(ERR, "Failed to allocate packet pacing index."); @@ -129,12 +130,7 @@ mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh) static void mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq) { - if (wq->sq) - claim_zero(mlx5_devx_cmd_destroy(wq->sq)); - if (wq->sq_umem) - claim_zero(mlx5_os_umem_dereg(wq->sq_umem)); - if (wq->sq_buf) - mlx5_free((void *)(uintptr_t)wq->sq_buf); + mlx5_devx_sq_destroy(&wq->sq_obj); mlx5_devx_cq_destroy(&wq->cq_obj); memset(wq, 0, sizeof(*wq)); } @@ -163,32 +159,26 @@ static void mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci) { struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; + struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; union { uint32_t w32[2]; uint64_t w64; } cs; - void *reg_addr; wq->sq_ci = ci + 1; cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32 - (wq->wqes[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8); - cs.w32[1] = wq->wqes[ci & (wq->sq_size - 1)].ctrl[1]; + (wqe[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8); + cs.w32[1] = wqe[ci & (wq->sq_size - 1)].ctrl[1]; /* Update SQ doorbell record with new SQ ci. */ - rte_compiler_barrier(); - *wq->sq_dbrec = rte_cpu_to_be_32(wq->sq_ci); - /* Make sure the doorbell record is updated. */ - rte_wmb(); - /* Write to doorbel register to start processing. */ - reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar); - __mlx5_uar_write64_relaxed(cs.w64, reg_addr, NULL); - rte_wmb(); + mlx5_doorbell_ring(&sh->tx_uar.bf_db, cs.w64, wq->sq_ci, + wq->sq_obj.db_rec, !sh->tx_uar.dbnc); } static void mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh) { struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; - struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes; + struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; uint32_t i; for (i = 0; i < wq->sq_size; i += 2) { @@ -199,7 +189,7 @@ mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh) /* Build SEND_EN request with slave WQE index. */ cs = &wqe[i + 0].cseg; cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0); - cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2); + cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2); cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET); cs->misc = RTE_BE32(0); @@ -207,11 +197,12 @@ mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh) index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) & ((1 << MLX5_WQ_INDEX_WIDTH) - 1); qs->max_index = rte_cpu_to_be_32(index); - qs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.sq->id); + qs->qpn_cqn = + rte_cpu_to_be_32(sh->txpp.clock_queue.sq_obj.sq->id); /* Build WAIT request with slave CQE index. */ cs = &wqe[i + 1].cseg; cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0); - cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2); + cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2); cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR << MLX5_COMP_MODE_OFFSET); cs->misc = RTE_BE32(0); @@ -228,23 +219,28 @@ mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh) static int mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh) { - struct mlx5_devx_create_sq_attr sq_attr = { 0 }; + struct mlx5_devx_create_sq_attr sq_attr = { + .cd_master = 1, + .state = MLX5_SQC_STATE_RST, + .tis_lst_sz = 1, + .tis_num = sh->tis[0]->id, + .wq_attr = (struct mlx5_devx_wq_attr){ + .pd = sh->cdev->pdn, + .uar_page = + mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj), + }, + .ts_format = mlx5_ts_format_conv + (sh->cdev->config.hca_attr.sq_ts_format), + }; struct mlx5_devx_modify_sq_attr msq_attr = { 0 }; struct mlx5_devx_cq_attr cq_attr = { - .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar), + .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj), }; struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; - size_t page_size; - uint32_t umem_size, umem_dbrec; int ret; - page_size = rte_mem_page_size(); - if (page_size == (size_t)-1) { - DRV_LOG(ERR, "Failed to get mem page size"); - return -ENOMEM; - } /* Create completion queue object for Rearm Queue. */ - ret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj, + ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj, log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr, sh->numa_node); if (ret) { @@ -253,63 +249,25 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh) } wq->cq_ci = 0; wq->arm_sn = 0; - /* - * Allocate memory buffer for Send Queue WQEs. - * There should be no WQE leftovers in the cyclic queue. - */ wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE; MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size))); - umem_size = MLX5_WQE_SIZE * wq->sq_size; - umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); - umem_size += MLX5_DBR_SIZE; - wq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, - page_size, sh->numa_node); - if (!wq->sq_buf) { - DRV_LOG(ERR, "Failed to allocate memory for Rearm Queue."); - rte_errno = ENOMEM; - goto error; - } - /* Register allocated buffer in user space with DevX. */ - wq->sq_umem = mlx5_os_umem_reg(sh->ctx, - (void *)(uintptr_t)wq->sq_buf, - umem_size, - IBV_ACCESS_LOCAL_WRITE); - if (!wq->sq_umem) { - rte_errno = errno; - DRV_LOG(ERR, "Failed to register umem for Rearm Queue."); - goto error; - } /* Create send queue object for Rearm Queue. */ - sq_attr.state = MLX5_SQC_STATE_RST; - sq_attr.tis_lst_sz = 1; - sq_attr.tis_num = sh->tis->id; sq_attr.cqn = wq->cq_obj.cq->id; - sq_attr.cd_master = 1; - sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar); - sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC; - sq_attr.wq_attr.pd = sh->pdn; - sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE); - sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size); - sq_attr.wq_attr.dbr_umem_valid = 1; - sq_attr.wq_attr.dbr_addr = umem_dbrec; - sq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem); - sq_attr.wq_attr.wq_umem_valid = 1; - sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem); - sq_attr.wq_attr.wq_umem_offset = 0; - wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr); - if (!wq->sq) { + /* There should be no WQE leftovers in the cyclic queue. */ + ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj, + log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr, + sh->numa_node); + if (ret) { rte_errno = errno; DRV_LOG(ERR, "Failed to create SQ for Rearm Queue."); goto error; } - wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec + - MLX5_SND_DBR * sizeof(uint32_t)); /* Build the WQEs in the Send Queue before goto Ready state. */ mlx5_txpp_fill_wqe_rearm_queue(sh); /* Change queue state to ready. */ msq_attr.sq_state = MLX5_SQC_STATE_RST; msq_attr.state = MLX5_SQC_STATE_RDY; - ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr); + ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr); if (ret) { DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue."); goto error; @@ -326,7 +284,7 @@ static void mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh) { struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; - struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes; + struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; struct mlx5_wqe_cseg *cs = &wqe->cseg; uint32_t wqe_size, opcode, i; uint8_t *dst; @@ -344,7 +302,7 @@ mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh) opcode = MLX5_OPCODE_NOP; } cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */ - cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | + cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | (wqe_size / MLX5_WSEG_SIZE)); cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET); cs->misc = RTE_BE32(0); @@ -370,8 +328,8 @@ mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh) /* Build test packet L2 header (Ethernet). */ dst = (uint8_t *)&es->inline_data; eth_hdr = (struct rte_ether_hdr *)dst; - rte_eth_random_addr(ð_hdr->d_addr.addr_bytes[0]); - rte_eth_random_addr(ð_hdr->s_addr.addr_bytes[0]); + rte_eth_random_addr(ð_hdr->dst_addr.addr_bytes[0]); + rte_eth_random_addr(ð_hdr->src_addr.addr_bytes[0]); eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4); /* Build test packet L3 header (IP v4). */ dst += sizeof(struct rte_ether_hdr); @@ -413,10 +371,11 @@ mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh) } wcopy: /* Duplicate the pattern to the next WQEs. */ - dst = (uint8_t *)(uintptr_t)wq->sq_buf; + dst = (uint8_t *)(uintptr_t)wq->sq_obj.umem_buf; for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) { dst += wqe_size; - rte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size); + rte_memcpy(dst, (void *)(uintptr_t)wq->sq_obj.umem_buf, + wqe_size); } } @@ -429,18 +388,11 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh) struct mlx5_devx_cq_attr cq_attr = { .use_first_only = 1, .overrun_ignore = 1, - .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar), + .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj), }; struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; - size_t page_size; - uint32_t umem_size, umem_dbrec; int ret; - page_size = rte_mem_page_size(); - if (page_size == (size_t)-1) { - DRV_LOG(ERR, "Failed to get mem page size"); - return -ENOMEM; - } sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, MLX5_TXPP_REARM_SQ_SIZE * sizeof(struct mlx5_txpp_ts), @@ -452,7 +404,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh) sh->txpp.ts_p = 0; sh->txpp.ts_n = 0; /* Create completion queue object for Clock Queue. */ - ret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj, + ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj, log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr, sh->numa_node); if (ret) { @@ -473,67 +425,38 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh) } /* There should not be WQE leftovers in the cyclic queue. */ MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size))); - umem_size = MLX5_WQE_SIZE * wq->sq_size; - umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); - umem_size += MLX5_DBR_SIZE; - wq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, - page_size, sh->numa_node); - if (!wq->sq_buf) { - DRV_LOG(ERR, "Failed to allocate memory for Clock Queue."); - rte_errno = ENOMEM; - goto error; - } - /* Register allocated buffer in user space with DevX. */ - wq->sq_umem = mlx5_os_umem_reg(sh->ctx, - (void *)(uintptr_t)wq->sq_buf, - umem_size, - IBV_ACCESS_LOCAL_WRITE); - if (!wq->sq_umem) { - rte_errno = errno; - DRV_LOG(ERR, "Failed to register umem for Clock Queue."); - goto error; - } /* Create send queue object for Clock Queue. */ if (sh->txpp.test) { sq_attr.tis_lst_sz = 1; - sq_attr.tis_num = sh->tis->id; + sq_attr.tis_num = sh->tis[0]->id; sq_attr.non_wire = 0; sq_attr.static_sq_wq = 1; } else { sq_attr.non_wire = 1; sq_attr.static_sq_wq = 1; } - sq_attr.state = MLX5_SQC_STATE_RST; sq_attr.cqn = wq->cq_obj.cq->id; sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id; sq_attr.wq_attr.cd_slave = 1; - sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar); - sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC; - sq_attr.wq_attr.pd = sh->pdn; - sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE); - sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size); - sq_attr.wq_attr.dbr_umem_valid = 1; - sq_attr.wq_attr.dbr_addr = umem_dbrec; - sq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem); - sq_attr.wq_attr.wq_umem_valid = 1; - sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem); - /* umem_offset must be zero for static_sq_wq queue. */ - sq_attr.wq_attr.wq_umem_offset = 0; - wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr); - if (!wq->sq) { + sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj); + sq_attr.wq_attr.pd = sh->cdev->pdn; + sq_attr.ts_format = + mlx5_ts_format_conv(sh->cdev->config.hca_attr.sq_ts_format); + ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj, + log2above(wq->sq_size), + &sq_attr, sh->numa_node); + if (ret) { rte_errno = errno; DRV_LOG(ERR, "Failed to create SQ for Clock Queue."); goto error; } - wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec + - MLX5_SND_DBR * sizeof(uint32_t)); /* Build the WQEs in the Send Queue before goto Ready state. */ mlx5_txpp_fill_wqe_clock_queue(sh); /* Change queue state to ready. */ msq_attr.sq_state = MLX5_SQC_STATE_RST; msq_attr.state = MLX5_SQC_STATE_RDY; wq->sq_ci = 0; - ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr); + ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr); if (ret) { DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue."); goto error; @@ -550,26 +473,14 @@ error: static inline void mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh) { - void *base_addr; - struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue; uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET; uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci; uint64_t db_be = rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq_obj.cq->id); - base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar); - uint32_t *addr = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL); - rte_compiler_barrier(); - aq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(db_hi); - rte_wmb(); -#ifdef RTE_ARCH_64 - *(uint64_t *)addr = db_be; -#else - *(uint32_t *)addr = db_be; - rte_io_wmb(); - *((uint32_t *)addr + 1) = db_be >> 32; -#endif + mlx5_doorbell_ring(&sh->tx_uar.cq_db, db_be, db_hi, + &aq->cq_obj.db_rec[MLX5_CQ_ARM_DB], 0); aq->arm_sn++; } @@ -604,8 +515,8 @@ mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts) { /* * The only CQE of Clock Queue is being continuously - * update by hardware with soecified rate. We have to - * read timestump and WQE completion index atomically. + * updated by hardware with specified rate. We must + * read timestamp and WQE completion index atomically. */ #if defined(RTE_ARCH_X86_64) rte_int128_t src; @@ -666,13 +577,22 @@ mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh) } to; uint64_t ts; uint16_t ci; + uint8_t opcode; mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); - if (to.cts.op_own >> 4) { - DRV_LOG(DEBUG, "Clock Queue error sync lost."); - __atomic_fetch_add(&sh->txpp.err_clock_queue, + opcode = MLX5_CQE_OPCODE(to.cts.op_own); + if (opcode) { + if (opcode != MLX5_CQE_INVALID) { + /* + * Commit the error state if and only if + * we have got at least one actual completion. + */ + DRV_LOG(DEBUG, + "Clock Queue error sync lost (%X).", opcode); + __atomic_fetch_add(&sh->txpp.err_clock_queue, 1, __ATOMIC_RELAXED); - sh->txpp.sync_lost = 1; + sh->txpp.sync_lost = 1; + } return; } ci = rte_be_to_cpu_16(to.cts.wqe_counter); @@ -821,11 +741,11 @@ mlx5_txpp_interrupt_handler(void *cb_arg) static void mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh) { - if (!sh->txpp.intr_handle.fd) + if (!rte_intr_fd_get(sh->txpp.intr_handle)) return; - mlx5_intr_callback_unregister(&sh->txpp.intr_handle, + mlx5_intr_callback_unregister(sh->txpp.intr_handle, mlx5_txpp_interrupt_handler, sh); - sh->txpp.intr_handle.fd = 0; + rte_intr_instance_free(sh->txpp.intr_handle); } /* Attach interrupt handler and fires first request to Rearm Queue. */ @@ -849,13 +769,22 @@ mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh) rte_errno = errno; return -rte_errno; } - memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle)); + sh->txpp.intr_handle = + rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); + if (sh->txpp.intr_handle == NULL) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); + return -ENOMEM; + } fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); - sh->txpp.intr_handle.fd = fd; - sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT; - if (rte_intr_callback_register(&sh->txpp.intr_handle, + if (rte_intr_fd_set(sh->txpp.intr_handle, fd)) + return -rte_errno; + + if (rte_intr_type_set(sh->txpp.intr_handle, RTE_INTR_HANDLE_EXT)) + return -rte_errno; + + if (rte_intr_callback_register(sh->txpp.intr_handle, mlx5_txpp_interrupt_handler, sh)) { - sh->txpp.intr_handle.fd = 0; + rte_intr_fd_set(sh->txpp.intr_handle, 0); DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno); return -rte_errno; } @@ -961,7 +890,6 @@ mlx5_txpp_start(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_dev_ctx_shared *sh = priv->sh; int err = 0; - int ret; if (!priv->config.tx_pp) { /* Packet pacing is not requested for the device. */ @@ -974,14 +902,14 @@ mlx5_txpp_start(struct rte_eth_dev *dev) return 0; } if (priv->config.tx_pp > 0) { - ret = rte_mbuf_dynflag_lookup - (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); - if (ret < 0) + err = rte_mbuf_dynflag_lookup + (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); + /* No flag registered means no service needed. */ + if (err < 0) return 0; + err = 0; } - ret = pthread_mutex_lock(&sh->txpp.mutex); - MLX5_ASSERT(!ret); - RTE_SET_USED(ret); + claim_zero(pthread_mutex_lock(&sh->txpp.mutex)); if (sh->txpp.refcnt) { priv->txpp_en = 1; ++sh->txpp.refcnt; @@ -995,9 +923,7 @@ mlx5_txpp_start(struct rte_eth_dev *dev) rte_errno = -err; } } - ret = pthread_mutex_unlock(&sh->txpp.mutex); - MLX5_ASSERT(!ret); - RTE_SET_USED(ret); + claim_zero(pthread_mutex_unlock(&sh->txpp.mutex)); return err; } @@ -1015,24 +941,21 @@ mlx5_txpp_stop(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_dev_ctx_shared *sh = priv->sh; - int ret; if (!priv->txpp_en) { /* Packet pacing is already disabled for the device. */ return; } priv->txpp_en = 0; - ret = pthread_mutex_lock(&sh->txpp.mutex); - MLX5_ASSERT(!ret); - RTE_SET_USED(ret); + claim_zero(pthread_mutex_lock(&sh->txpp.mutex)); MLX5_ASSERT(sh->txpp.refcnt); - if (!sh->txpp.refcnt || --sh->txpp.refcnt) + if (!sh->txpp.refcnt || --sh->txpp.refcnt) { + claim_zero(pthread_mutex_unlock(&sh->txpp.mutex)); return; + } /* No references any more, do actual destroy. */ mlx5_txpp_destroy(sh); - ret = pthread_mutex_unlock(&sh->txpp.mutex); - MLX5_ASSERT(!ret); - RTE_SET_USED(ret); + claim_zero(pthread_mutex_unlock(&sh->txpp.mutex)); } /*