X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_txq.c;h=0f30a5d529167b87d394c04aac9ff8228437ff81;hb=1be514fbcea9e8964296b46c91dbb56715503ae7;hp=068f36d99d0e08c6d5d298e71e7d61aea5fe8a82;hpb=c44fbc7cc2fb6cf62956d6b5bb2c0206884ad568;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 068f36d99d..0f30a5d529 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -4,34 +4,27 @@ */ #include -#include #include #include #include #include -#include - -/* Verbs header. */ -/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ -#ifdef PEDANTIC -#pragma GCC diagnostic ignored "-Wpedantic" -#endif -#include -#ifdef PEDANTIC -#pragma GCC diagnostic error "-Wpedantic" -#endif +#include #include #include #include #include +#include + +#include +#include +#include -#include "mlx5_utils.h" #include "mlx5_defs.h" +#include "mlx5_utils.h" #include "mlx5.h" #include "mlx5_rxtx.h" #include "mlx5_autoconf.h" -#include "mlx5_glue.h" /** * Allocate TX queue elements. @@ -46,9 +39,9 @@ txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl) unsigned int i; for (i = 0; (i != elts_n); ++i) - (*txq_ctrl->txq.elts)[i] = NULL; + txq_ctrl->txq.elts[i] = NULL; DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs", - PORT_ID(txq_ctrl->priv), txq_ctrl->idx, elts_n); + PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n); txq_ctrl->txq.elts_head = 0; txq_ctrl->txq.elts_tail = 0; txq_ctrl->txq.elts_comp = 0; @@ -60,17 +53,17 @@ txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl) * @param txq_ctrl * Pointer to TX queue structure. */ -static void +void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl) { const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n; const uint16_t elts_m = elts_n - 1; uint16_t elts_head = txq_ctrl->txq.elts_head; uint16_t elts_tail = txq_ctrl->txq.elts_tail; - struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts; + struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts; DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs", - PORT_ID(txq_ctrl->priv), txq_ctrl->idx); + PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx); txq_ctrl->txq.elts_head = 0; txq_ctrl->txq.elts_tail = 0; txq_ctrl->txq.elts_comp = 0; @@ -78,9 +71,9 @@ txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl) while (elts_tail != elts_head) { struct rte_mbuf *elt = (*elts)[elts_tail & elts_m]; - assert(elt != NULL); + MLX5_ASSERT(elt != NULL); rte_pktmbuf_free_seg(elt); -#ifndef NDEBUG +#ifdef RTE_LIBRTE_MLX5_DEBUG /* Poisoning. */ memset(&(*elts)[elts_tail & elts_m], 0x77, @@ -102,7 +95,7 @@ txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl) uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS | DEV_TX_OFFLOAD_VLAN_INSERT); struct mlx5_dev_config *config = &priv->config; @@ -113,62 +106,233 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) DEV_TX_OFFLOAD_TCP_CKSUM); if (config->tso) offloads |= DEV_TX_OFFLOAD_TCP_TSO; - if (config->tunnel_en) { + if (config->tx_pp) + offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP; + if (config->swp) { if (config->hw_csum) offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; if (config->tso) - offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GRE_TNL_TSO); - if (config->swp) offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO | DEV_TX_OFFLOAD_UDP_TNL_TSO); } + if (config->tunnel_en) { + if (config->hw_csum) + offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; + if (config->tso) + offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | + DEV_TX_OFFLOAD_GRE_TNL_TSO | + DEV_TX_OFFLOAD_GENEVE_TNL_TSO); + } return offloads; } +/* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */ +static void +txq_sync_cq(struct mlx5_txq_data *txq) +{ + volatile struct mlx5_cqe *cqe; + int ret, i; + + i = txq->cqe_s; + do { + cqe = &txq->cqes[txq->cq_ci & txq->cqe_m]; + ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci); + if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) { + if (likely(ret != MLX5_CQE_STATUS_ERR)) { + /* No new CQEs in completion queue. */ + MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN); + break; + } + } + ++txq->cq_ci; + } while (--i); + /* Move all CQEs to HW ownership. */ + for (i = 0; i < txq->cqe_s; i++) { + cqe = &txq->cqes[i]; + cqe->op_own = MLX5_CQE_INVALIDATE; + } + /* Resync CQE and WQE (WQ in reset state). */ + rte_io_wmb(); + *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci); + rte_io_wmb(); +} + /** - * DPDK callback to configure a TX queue. + * Tx queue stop. Device queue goes to the idle state, + * all involved mbufs are freed from elts/WQ. * * @param dev * Pointer to Ethernet device structure. * @param idx - * TX queue index. - * @param desc - * Number of descriptors to configure in queue. - * @param socket - * NUMA socket on which memory must be allocated. - * @param[in] conf - * Thresholds parameters. + * Tx queue index. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, - unsigned int socket, const struct rte_eth_txconf *conf) +mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_txq_data *txq = (*priv->txqs)[idx]; struct mlx5_txq_ctrl *txq_ctrl = - container_of(txq, struct mlx5_txq_ctrl, txq); + container_of(txq, struct mlx5_txq_ctrl, txq); + int ret; + + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + /* Move QP to RESET state. */ + ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj, MLX5_TXQ_MOD_RDY2RST, + (uint8_t)priv->dev_port); + if (ret) + return ret; + /* Handle all send completions. */ + txq_sync_cq(txq); + /* Free elts stored in the SQ. */ + txq_free_elts(txq_ctrl); + /* Prevent writing new pkts to SQ by setting no free WQE.*/ + txq->wqe_ci = txq->wqe_s; + txq->wqe_pi = 0; + txq->elts_comp = 0; + /* Set the actual queue state. */ + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED; + return 0; +} + +/** + * Tx queue stop. Device queue goes to the idle state, + * all involved mbufs are freed from elts/WQ. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * Tx queue index. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t idx) +{ + int ret; - if (desc <= MLX5_TX_COMP_THRESH) { + if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) { + DRV_LOG(ERR, "Hairpin queue can't be stopped"); + rte_errno = EINVAL; + return -EINVAL; + } + if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED) + return 0; + if (rte_eal_process_type() == RTE_PROC_SECONDARY) { + ret = mlx5_mp_os_req_queue_control(dev, idx, + MLX5_MP_REQ_QUEUE_TX_STOP); + } else { + ret = mlx5_tx_queue_stop_primary(dev, idx); + } + return ret; +} + +/** + * Rx queue start. Device queue goes to the ready state, + * all required mbufs are allocated and WQ is replenished. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * RX queue index. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq = (*priv->txqs)[idx]; + struct mlx5_txq_ctrl *txq_ctrl = + container_of(txq, struct mlx5_txq_ctrl, txq); + int ret; + + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj, + MLX5_TXQ_MOD_RST2RDY, + (uint8_t)priv->dev_port); + if (ret) + return ret; + txq_ctrl->txq.wqe_ci = 0; + txq_ctrl->txq.wqe_pi = 0; + txq_ctrl->txq.elts_comp = 0; + /* Set the actual queue state. */ + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED; + return 0; +} + +/** + * Rx queue start. Device queue goes to the ready state, + * all required mbufs are allocated and WQ is replenished. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * RX queue index. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t idx) +{ + int ret; + + if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) { + DRV_LOG(ERR, "Hairpin queue can't be started"); + rte_errno = EINVAL; + return -EINVAL; + } + if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED) + return 0; + if (rte_eal_process_type() == RTE_PROC_SECONDARY) { + ret = mlx5_mp_os_req_queue_control(dev, idx, + MLX5_MP_REQ_QUEUE_TX_START); + } else { + ret = mlx5_tx_queue_start_primary(dev, idx); + } + return ret; +} + +/** + * Tx queue presetup checks. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * Tx queue index. + * @param desc + * Number of descriptors to configure in queue. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (*desc <= MLX5_TX_COMP_THRESH) { DRV_LOG(WARNING, "port %u number of descriptors requested for Tx queue" " %u must be higher than MLX5_TX_COMP_THRESH, using %u" - " instead of %u", - dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc); - desc = MLX5_TX_COMP_THRESH + 1; + " instead of %u", dev->data->port_id, idx, + MLX5_TX_COMP_THRESH + 1, *desc); + *desc = MLX5_TX_COMP_THRESH + 1; } - if (!rte_is_power_of_2(desc)) { - desc = 1 << log2above(desc); + if (!rte_is_power_of_2(*desc)) { + *desc = 1 << log2above(*desc); DRV_LOG(WARNING, "port %u increased number of descriptors in Tx queue" " %u to the next power of two (%d)", - dev->data->port_id, idx, desc); + dev->data->port_id, idx, *desc); } DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors", - dev->data->port_id, idx, desc); + dev->data->port_id, idx, *desc); if (idx >= priv->txqs_n) { DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)", dev->data->port_id, idx, priv->txqs_n); @@ -182,6 +346,39 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, return -rte_errno; } mlx5_txq_release(dev, idx); + return 0; +} + +/** + * DPDK callback to configure a TX queue. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * TX queue index. + * @param desc + * Number of descriptors to configure in queue. + * @param socket + * NUMA socket on which memory must be allocated. + * @param[in] conf + * Thresholds parameters. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + unsigned int socket, const struct rte_eth_txconf *conf) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq = (*priv->txqs)[idx]; + struct mlx5_txq_ctrl *txq_ctrl = + container_of(txq, struct mlx5_txq_ctrl, txq); + int res; + + res = mlx5_tx_queue_pre_setup(dev, idx, &desc); + if (res) + return res; txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf); if (!txq_ctrl) { DRV_LOG(ERR, "port %u unable to allocate queue index %u", @@ -191,6 +388,78 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, DRV_LOG(DEBUG, "port %u adding Tx queue %u to list", dev->data->port_id, idx); (*priv->txqs)[idx] = &txq_ctrl->txq; + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED; + return 0; +} + +/** + * DPDK callback to configure a TX hairpin queue. + * + * @param dev + * Pointer to Ethernet device structure. + * @param idx + * TX queue index. + * @param desc + * Number of descriptors to configure in queue. + * @param[in] hairpin_conf + * The hairpin binding configuration. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx, + uint16_t desc, + const struct rte_eth_hairpin_conf *hairpin_conf) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq = (*priv->txqs)[idx]; + struct mlx5_txq_ctrl *txq_ctrl = + container_of(txq, struct mlx5_txq_ctrl, txq); + int res; + + res = mlx5_tx_queue_pre_setup(dev, idx, &desc); + if (res) + return res; + if (hairpin_conf->peer_count != 1) { + rte_errno = EINVAL; + DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue index %u" + " peer count is %u", dev->data->port_id, + idx, hairpin_conf->peer_count); + return -rte_errno; + } + if (hairpin_conf->peers[0].port == dev->data->port_id) { + if (hairpin_conf->peers[0].queue >= priv->rxqs_n) { + rte_errno = EINVAL; + DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue" + " index %u, Rx %u is larger than %u", + dev->data->port_id, idx, + hairpin_conf->peers[0].queue, priv->txqs_n); + return -rte_errno; + } + } else { + if (hairpin_conf->manual_bind == 0 || + hairpin_conf->tx_explicit == 0) { + rte_errno = EINVAL; + DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue" + " index %u peer port %u with attributes %u %u", + dev->data->port_id, idx, + hairpin_conf->peers[0].port, + hairpin_conf->manual_bind, + hairpin_conf->tx_explicit); + return -rte_errno; + } + } + txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf); + if (!txq_ctrl) { + DRV_LOG(ERR, "port %u unable to allocate queue index %u", + dev->data->port_id, idx); + return -rte_errno; + } + DRV_LOG(DEBUG, "port %u adding Tx queue %u to list", + dev->data->port_id, idx); + (*priv->txqs)[idx] = &txq_ctrl->txq; + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN; return 0; } @@ -205,7 +474,7 @@ mlx5_tx_queue_release(void *dpdk_txq) { struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq; struct mlx5_txq_ctrl *txq_ctrl; - struct priv *priv; + struct mlx5_priv *priv; unsigned int i; if (txq == NULL) @@ -214,406 +483,297 @@ mlx5_tx_queue_release(void *dpdk_txq) priv = txq_ctrl->priv; for (i = 0; (i != priv->txqs_n); ++i) if ((*priv->txqs)[i] == txq) { - mlx5_txq_release(ETH_DEV(priv), i); DRV_LOG(DEBUG, "port %u removing Tx queue %u from list", - PORT_ID(priv), txq_ctrl->idx); + PORT_ID(priv), txq->idx); + mlx5_txq_release(ETH_DEV(priv), i); break; } } +/** + * Configure the doorbell register non-cached attribute. + * + * @param txq_ctrl + * Pointer to Tx queue control structure. + * @param page_size + * Systme page size + */ +static void +txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size) +{ + struct mlx5_priv *priv = txq_ctrl->priv; + off_t cmd; + + txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC; + txq_ctrl->txq.db_nc = 0; + /* Check the doorbell register mapping type. */ + cmd = txq_ctrl->uar_mmap_offset / page_size; + cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; + cmd &= MLX5_UAR_MMAP_CMD_MASK; + if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD) + txq_ctrl->txq.db_nc = 1; +} /** - * Mmap TX UAR(HW doorbell) pages into reserved UAR address space. - * Both primary and secondary process do mmap to make UAR address - * aligned. + * Initialize Tx UAR registers for primary process. * - * @param[in] dev - * Pointer to Ethernet device. + * @param txq_ctrl + * Pointer to Tx queue control structure. + */ +void +txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl) +{ + struct mlx5_priv *priv = txq_ctrl->priv; + struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv)); +#ifndef RTE_ARCH_64 + unsigned int lock_idx; +#endif + const size_t page_size = rte_mem_page_size(); + if (page_size == (size_t)-1) { + DRV_LOG(ERR, "Failed to get mem page size"); + rte_errno = ENOMEM; + } + + if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD) + return; + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + MLX5_ASSERT(ppriv); + ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg; + txq_uar_ncattr_init(txq_ctrl, page_size); +#ifndef RTE_ARCH_64 + /* Assign an UAR lock according to UAR page number */ + lock_idx = (txq_ctrl->uar_mmap_offset / page_size) & + MLX5_UAR_PAGE_NUM_MASK; + txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx]; +#endif +} + +/** + * Remap UAR register of a Tx queue for secondary process. + * + * Remapped address is stored at the table in the process private structure of + * the device, indexed by queue index. + * + * @param txq_ctrl + * Pointer to Tx queue control structure. * @param fd * Verbs file descriptor to map UAR pages. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -int -mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd) +static int +txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd) { - struct priv *priv = dev->data->dev_private; - unsigned int i, j; - uintptr_t pages[priv->txqs_n]; - unsigned int pages_n = 0; - uintptr_t uar_va; - uintptr_t off; + struct mlx5_priv *priv = txq_ctrl->priv; + struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv)); + struct mlx5_txq_data *txq = &txq_ctrl->txq; void *addr; - void *ret; - struct mlx5_txq_data *txq; - struct mlx5_txq_ctrl *txq_ctrl; - int already_mapped; - size_t page_size = sysconf(_SC_PAGESIZE); + uintptr_t uar_va; + uintptr_t offset; + const size_t page_size = rte_mem_page_size(); + if (page_size == (size_t)-1) { + DRV_LOG(ERR, "Failed to get mem page size"); + rte_errno = ENOMEM; + return -rte_errno; + } - memset(pages, 0, priv->txqs_n * sizeof(uintptr_t)); + if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD) + return 0; + MLX5_ASSERT(ppriv); /* - * As rdma-core, UARs are mapped in size of OS page size. - * Use aligned address to avoid duplicate mmap. - * Ref to libmlx5 function: mlx5_init_context() + * As rdma-core, UARs are mapped in size of OS page + * size. Ref to libmlx5 function: mlx5_init_context() */ - for (i = 0; i != priv->txqs_n; ++i) { - if (!(*priv->txqs)[i]) - continue; - txq = (*priv->txqs)[i]; - txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); - assert(txq_ctrl->idx == (uint16_t)i); - /* UAR addr form verbs used to find dup and offset in page. */ - uar_va = (uintptr_t)txq_ctrl->bf_reg_orig; - off = uar_va & (page_size - 1); /* offset in page. */ - uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */ - already_mapped = 0; - for (j = 0; j != pages_n; ++j) { - if (pages[j] == uar_va) { - already_mapped = 1; - break; - } - } - /* new address in reserved UAR address space. */ - addr = RTE_PTR_ADD(priv->uar_base, - uar_va & (MLX5_UAR_SIZE - 1)); - if (!already_mapped) { - pages[pages_n++] = uar_va; - /* fixed mmap to specified address in reserved - * address space. - */ - ret = mmap(addr, page_size, - PROT_WRITE, MAP_FIXED | MAP_SHARED, fd, - txq_ctrl->uar_mmap_offset); - if (ret != addr) { - /* fixed mmap have to return same address */ - DRV_LOG(ERR, - "port %u call to mmap failed on UAR" - " for txq %u", - dev->data->port_id, txq_ctrl->idx); - rte_errno = ENXIO; - return -rte_errno; - } - } - if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */ - txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off); - else - assert(txq_ctrl->txq.bf_reg == - RTE_PTR_ADD((void *)addr, off)); + uar_va = (uintptr_t)txq_ctrl->bf_reg; + offset = uar_va & (page_size - 1); /* Offset in page. */ + addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED, + fd, txq_ctrl->uar_mmap_offset); + if (!addr) { + DRV_LOG(ERR, + "port %u mmap failed for BF reg of txq %u", + txq->port_id, txq->idx); + rte_errno = ENXIO; + return -rte_errno; } + addr = RTE_PTR_ADD(addr, offset); + ppriv->uar_table[txq->idx] = addr; + txq_uar_ncattr_init(txq_ctrl, page_size); return 0; } /** - * Check if the burst function is using eMPW. - * - * @param tx_pkt_burst - * Tx burst function pointer. + * Unmap UAR register of a Tx queue for secondary process. * - * @return - * 1 if the burst function is using eMPW, 0 otherwise. + * @param txq_ctrl + * Pointer to Tx queue control structure. */ -static int -is_empw_burst_func(eth_tx_burst_t tx_pkt_burst) +static void +txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl) { - if (tx_pkt_burst == mlx5_tx_burst_raw_vec || - tx_pkt_burst == mlx5_tx_burst_vec || - tx_pkt_burst == mlx5_tx_burst_empw) - return 1; - return 0; + struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv)); + void *addr; + const size_t page_size = rte_mem_page_size(); + if (page_size == (size_t)-1) { + DRV_LOG(ERR, "Failed to get mem page size"); + rte_errno = ENOMEM; + } + + if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD) + return; + addr = ppriv->uar_table[txq_ctrl->txq.idx]; + rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size); } /** - * Create the Tx queue Verbs object. + * Deinitialize Tx UAR registers for secondary process. * * @param dev * Pointer to Ethernet device. - * @param idx - * Queue index in DPDK Rx queue array - * - * @return - * The Verbs object initialised, NULL otherwise and rte_errno is set. */ -struct mlx5_txq_ibv * -mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx) +void +mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev) { - struct priv *priv = dev->data->dev_private; - struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; - struct mlx5_txq_ctrl *txq_ctrl = - container_of(txq_data, struct mlx5_txq_ctrl, txq); - struct mlx5_txq_ibv tmpl; - struct mlx5_txq_ibv *txq_ibv; - union { - struct ibv_qp_init_attr_ex init; - struct ibv_cq_init_attr_ex cq; - struct ibv_qp_attr mod; - struct ibv_cq_ex cq_attr; - } attr; - unsigned int cqe_n; - struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET }; - struct mlx5dv_cq cq_info; - struct mlx5dv_obj obj; - const int desc = 1 << txq_data->elts_n; - eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev); - int ret = 0; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq; + struct mlx5_txq_ctrl *txq_ctrl; + unsigned int i; - assert(txq_data); - priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE; - priv->verbs_alloc_ctx.obj = txq_ctrl; - if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { - DRV_LOG(ERR, - "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set", - dev->data->port_id); - rte_errno = EINVAL; - return NULL; - } - memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv)); - attr.cq = (struct ibv_cq_init_attr_ex){ - .comp_mask = 0, - }; - cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ? - ((desc / MLX5_TX_COMP_THRESH) - 1) : 1; - if (is_empw_burst_func(tx_pkt_burst)) - cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV; - tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0); - if (tmpl.cq == NULL) { - DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure", - dev->data->port_id, idx); - rte_errno = errno; - goto error; - } - attr.init = (struct ibv_qp_init_attr_ex){ - /* CQ to be associated with the send queue. */ - .send_cq = tmpl.cq, - /* CQ to be associated with the receive queue. */ - .recv_cq = tmpl.cq, - .cap = { - /* Max number of outstanding WRs. */ - .max_send_wr = - ((priv->device_attr.orig_attr.max_qp_wr < - desc) ? - priv->device_attr.orig_attr.max_qp_wr : - desc), - /* - * Max number of scatter/gather elements in a WR, - * must be 1 to prevent libmlx5 from trying to affect - * too much memory. TX gather is not impacted by the - * priv->device_attr.max_sge limit and will still work - * properly. - */ - .max_send_sge = 1, - }, - .qp_type = IBV_QPT_RAW_PACKET, - /* - * Do *NOT* enable this, completions events are managed per - * Tx burst. - */ - .sq_sig_all = 0, - .pd = priv->pd, - .comp_mask = IBV_QP_INIT_ATTR_PD, - }; - if (txq_data->max_inline) - attr.init.cap.max_inline_data = txq_ctrl->max_inline_data; - if (txq_data->tso_en) { - attr.init.max_tso_header = txq_ctrl->max_tso_header; - attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER; - } - tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init); - if (tmpl.qp == NULL) { - DRV_LOG(ERR, "port %u Tx queue %u QP creation failure", - dev->data->port_id, idx); - rte_errno = errno; - goto error; - } - attr.mod = (struct ibv_qp_attr){ - /* Move the QP to this state. */ - .qp_state = IBV_QPS_INIT, - /* Primary port number. */ - .port_num = priv->port - }; - ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, - (IBV_QP_STATE | IBV_QP_PORT)); - if (ret) { - DRV_LOG(ERR, - "port %u Tx queue %u QP state to IBV_QPS_INIT failed", - dev->data->port_id, idx); - rte_errno = errno; - goto error; - } - attr.mod = (struct ibv_qp_attr){ - .qp_state = IBV_QPS_RTR - }; - ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); - if (ret) { - DRV_LOG(ERR, - "port %u Tx queue %u QP state to IBV_QPS_RTR failed", - dev->data->port_id, idx); - rte_errno = errno; - goto error; - } - attr.mod.qp_state = IBV_QPS_RTS; - ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE); - if (ret) { - DRV_LOG(ERR, - "port %u Tx queue %u QP state to IBV_QPS_RTS failed", - dev->data->port_id, idx); - rte_errno = errno; - goto error; - } - txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0, - txq_ctrl->socket); - if (!txq_ibv) { - DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory", - dev->data->port_id, idx); - rte_errno = ENOMEM; - goto error; - } - obj.cq.in = tmpl.cq; - obj.cq.out = &cq_info; - obj.qp.in = tmpl.qp; - obj.qp.out = &qp; - ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP); - if (ret != 0) { - rte_errno = errno; - goto error; - } - if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) { - DRV_LOG(ERR, - "port %u wrong MLX5_CQE_SIZE environment variable" - " value: it should be set to %u", - dev->data->port_id, RTE_CACHE_LINE_SIZE); - rte_errno = EINVAL; - goto error; - } - txq_data->cqe_n = log2above(cq_info.cqe_cnt); - txq_data->qp_num_8s = tmpl.qp->qp_num << 8; - txq_data->wqes = qp.sq.buf; - txq_data->wqe_n = log2above(qp.sq.wqe_cnt); - txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR]; - txq_ctrl->bf_reg_orig = qp.bf.reg; - txq_data->cq_db = cq_info.dbrec; - txq_data->cqes = - (volatile struct mlx5_cqe (*)[]) - (uintptr_t)cq_info.buf; - txq_data->cq_ci = 0; -#ifndef NDEBUG - txq_data->cq_pi = 0; -#endif - txq_data->wqe_ci = 0; - txq_data->wqe_pi = 0; - txq_ibv->qp = tmpl.qp; - txq_ibv->cq = tmpl.cq; - rte_atomic32_inc(&txq_ibv->refcnt); - if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) { - txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset; - } else { - DRV_LOG(ERR, - "port %u failed to retrieve UAR info, invalid" - " libmlx5.so", - dev->data->port_id); - rte_errno = EINVAL; - goto error; + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY); + for (i = 0; i != priv->txqs_n; ++i) { + if (!(*priv->txqs)[i]) + continue; + txq = (*priv->txqs)[i]; + txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); + txq_uar_uninit_secondary(txq_ctrl); } - LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next); - txq_ibv->txq_ctrl = txq_ctrl; - priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; - return txq_ibv; -error: - ret = rte_errno; /* Save rte_errno before cleanup. */ - if (tmpl.cq) - claim_zero(mlx5_glue->destroy_cq(tmpl.cq)); - if (tmpl.qp) - claim_zero(mlx5_glue->destroy_qp(tmpl.qp)); - priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE; - rte_errno = ret; /* Restore rte_errno. */ - return NULL; } /** - * Get an Tx queue Verbs object. + * Initialize Tx UAR registers for secondary process. * * @param dev * Pointer to Ethernet device. - * @param idx - * Queue index in DPDK Rx queue array + * @param fd + * Verbs file descriptor to map UAR pages. * * @return - * The Verbs object if it exists. + * 0 on success, a negative errno value otherwise and rte_errno is set. */ -struct mlx5_txq_ibv * -mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx) +int +mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq; struct mlx5_txq_ctrl *txq_ctrl; + unsigned int i; + int ret; - if (idx >= priv->txqs_n) - return NULL; - if (!(*priv->txqs)[idx]) - return NULL; - txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); - if (txq_ctrl->ibv) - rte_atomic32_inc(&txq_ctrl->ibv->refcnt); - return txq_ctrl->ibv; + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY); + for (i = 0; i != priv->txqs_n; ++i) { + if (!(*priv->txqs)[i]) + continue; + txq = (*priv->txqs)[i]; + txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); + if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD) + continue; + MLX5_ASSERT(txq->idx == (uint16_t)i); + ret = txq_uar_init_secondary(txq_ctrl, fd); + if (ret) + goto error; + } + return 0; +error: + /* Rollback. */ + do { + if (!(*priv->txqs)[i]) + continue; + txq = (*priv->txqs)[i]; + txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); + txq_uar_uninit_secondary(txq_ctrl); + } while (i--); + return -rte_errno; } /** - * Release an Tx verbs queue object. + * Verify the Verbs Tx queue list is empty * - * @param txq_ibv - * Verbs Tx queue object. + * @param dev + * Pointer to Ethernet device. * * @return - * 1 while a reference on it exists, 0 when freed. + * The number of object not released. */ int -mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv) +mlx5_txq_obj_verify(struct rte_eth_dev *dev) { - assert(txq_ibv); - if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) { - claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp)); - claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq)); - LIST_REMOVE(txq_ibv, next); - rte_free(txq_ibv); - return 0; + struct mlx5_priv *priv = dev->data->dev_private; + int ret = 0; + struct mlx5_txq_obj *txq_obj; + + LIST_FOREACH(txq_obj, &priv->txqsobj, next) { + DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced", + dev->data->port_id, txq_obj->txq_ctrl->txq.idx); + ++ret; } - return 1; + return ret; } /** - * Return true if a single reference exists on the object. + * Calculate the total number of WQEBB for Tx queue. + * + * Simplified version of calc_sq_size() in rdma-core. * - * @param txq_ibv - * Verbs Tx queue object. + * @param txq_ctrl + * Pointer to Tx queue control structure. + * + * @return + * The number of WQEBB. */ -int -mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv) +static int +txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl) { - assert(txq_ibv); - return (rte_atomic32_read(&txq_ibv->refcnt) == 1); + unsigned int wqe_size; + const unsigned int desc = 1 << txq_ctrl->txq.elts_n; + + wqe_size = MLX5_WQE_CSEG_SIZE + + MLX5_WQE_ESEG_SIZE + + MLX5_WSEG_SIZE - + MLX5_ESEG_MIN_INLINE_SIZE + + txq_ctrl->max_inline_data; + return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE; } /** - * Verify the Verbs Tx queue list is empty + * Calculate the maximal inline data size for Tx queue. * - * @param dev - * Pointer to Ethernet device. + * @param txq_ctrl + * Pointer to Tx queue control structure. * * @return - * The number of object not released. + * The maximal inline data size. */ -int -mlx5_txq_ibv_verify(struct rte_eth_dev *dev) +static unsigned int +txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl) { - struct priv *priv = dev->data->dev_private; - int ret = 0; - struct mlx5_txq_ibv *txq_ibv; + const unsigned int desc = 1 << txq_ctrl->txq.elts_n; + struct mlx5_priv *priv = txq_ctrl->priv; + unsigned int wqe_size; - LIST_FOREACH(txq_ibv, &priv->txqsibv, next) { - DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced", - dev->data->port_id, txq_ibv->txq_ctrl->idx); - ++ret; - } - return ret; + wqe_size = priv->sh->device_attr.max_qp_wr / desc; + if (!wqe_size) + return 0; + /* + * This calculation is derived from tthe source of + * mlx5_calc_send_wqe() in rdma_core library. + */ + wqe_size = wqe_size * MLX5_WQE_SIZE - + MLX5_WQE_CSEG_SIZE - + MLX5_WQE_ESEG_SIZE - + MLX5_WSEG_SIZE - + MLX5_WSEG_SIZE + + MLX5_DSEG_MIN_INLINE_SIZE; + return wqe_size; } /** @@ -625,95 +785,302 @@ mlx5_txq_ibv_verify(struct rte_eth_dev *dev) static void txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) { - struct priv *priv = txq_ctrl->priv; + struct mlx5_priv *priv = txq_ctrl->priv; struct mlx5_dev_config *config = &priv->config; - const unsigned int max_tso_inline = - ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) / - RTE_CACHE_LINE_SIZE); - unsigned int txq_inline; - unsigned int txqs_inline; - unsigned int inline_max_packet_sz; - eth_tx_burst_t tx_pkt_burst = - mlx5_select_tx_function(ETH_DEV(priv)); - int is_empw_func = is_empw_burst_func(tx_pkt_burst); - int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO | - DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GRE_TNL_TSO | - DEV_TX_OFFLOAD_IP_TNL_TSO | - DEV_TX_OFFLOAD_UDP_TNL_TSO)); - - txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ? - 0 : config->txq_inline; - txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ? - 0 : config->txqs_inline; - inline_max_packet_sz = - (config->inline_max_packet_sz == MLX5_ARG_UNSET) ? - 0 : config->inline_max_packet_sz; - if (is_empw_func) { - if (config->txq_inline == MLX5_ARG_UNSET) - txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE; - if (config->txqs_inline == MLX5_ARG_UNSET) - txqs_inline = MLX5_EMPW_MIN_TXQS; - if (config->inline_max_packet_sz == MLX5_ARG_UNSET) - inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN; - txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg; - txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz; - } - if (txq_inline && priv->txqs_n >= txqs_inline) { - unsigned int ds_cnt; - - txq_ctrl->txq.max_inline = - ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) / - RTE_CACHE_LINE_SIZE); - if (is_empw_func) { - /* To minimize the size of data set, avoid requesting - * too large WQ. + unsigned int inlen_send; /* Inline data for ordinary SEND.*/ + unsigned int inlen_empw; /* Inline data for enhanced MPW. */ + unsigned int inlen_mode; /* Minimal required Inline data. */ + unsigned int txqs_inline; /* Min Tx queues to enable inline. */ + uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads; + bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO | + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | + DEV_TX_OFFLOAD_GRE_TNL_TSO | + DEV_TX_OFFLOAD_IP_TNL_TSO | + DEV_TX_OFFLOAD_UDP_TNL_TSO); + bool vlan_inline; + unsigned int temp; + + if (config->txqs_inline == MLX5_ARG_UNSET) + txqs_inline = +#if defined(RTE_ARCH_ARM64) + (priv->pci_dev->id.device_id == + PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ? + MLX5_INLINE_MAX_TXQS_BLUEFIELD : +#endif + MLX5_INLINE_MAX_TXQS; + else + txqs_inline = (unsigned int)config->txqs_inline; + inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ? + MLX5_SEND_DEF_INLINE_LEN : + (unsigned int)config->txq_inline_max; + inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ? + MLX5_EMPW_DEF_INLINE_LEN : + (unsigned int)config->txq_inline_mpw; + inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ? + 0 : (unsigned int)config->txq_inline_min; + if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW) + inlen_empw = 0; + /* + * If there is requested minimal amount of data to inline + * we MUST enable inlining. This is a case for ConnectX-4 + * which usually requires L2 inlined for correct operating + * and ConnectX-4 Lx which requires L2-L4 inlined to + * support E-Switch Flows. + */ + if (inlen_mode) { + if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) { + /* + * Optimize minimal inlining for single + * segment packets to fill one WQEBB + * without gaps. */ - txq_ctrl->max_inline_data = - ((RTE_MIN(txq_inline, - inline_max_packet_sz) + - (RTE_CACHE_LINE_SIZE - 1)) / - RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE; + temp = MLX5_ESEG_MIN_INLINE_SIZE; } else { - txq_ctrl->max_inline_data = - txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE; + temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE; + temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) + + MLX5_ESEG_MIN_INLINE_SIZE; + temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN); + } + if (temp != inlen_mode) { + DRV_LOG(INFO, + "port %u minimal required inline setting" + " aligned from %u to %u", + PORT_ID(priv), inlen_mode, temp); + inlen_mode = temp; + } + } + /* + * If port is configured to support VLAN insertion and device + * does not support this feature by HW (for NICs before ConnectX-5 + * or in case of wqe_vlan_insert flag is not set) we must enable + * data inline on all queues because it is supported by single + * tx_burst routine. + */ + txq_ctrl->txq.vlan_en = config->hw_vlan_insert; + vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) && + !config->hw_vlan_insert; + /* + * If there are few Tx queues it is prioritized + * to save CPU cycles and disable data inlining at all. + */ + if (inlen_send && priv->txqs_n >= txqs_inline) { + /* + * The data sent with ordinal MLX5_OPCODE_SEND + * may be inlined in Ethernet Segment, align the + * length accordingly to fit entire WQEBBs. + */ + temp = RTE_MAX(inlen_send, + MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE); + temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; + temp = RTE_ALIGN(temp, MLX5_WQE_SIZE); + temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; + temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX + + MLX5_ESEG_MIN_INLINE_SIZE - + MLX5_WQE_CSEG_SIZE - + MLX5_WQE_ESEG_SIZE - + MLX5_WQE_DSEG_SIZE * 2); + temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN); + temp = RTE_MAX(temp, inlen_mode); + if (temp != inlen_send) { + DRV_LOG(INFO, + "port %u ordinary send inline setting" + " aligned from %u to %u", + PORT_ID(priv), inlen_send, temp); + inlen_send = temp; } /* - * Check if the inline size is too large in a way which - * can make the WQE DS to overflow. - * Considering in calculation: - * WQE CTRL (1 DS) - * WQE ETH (1 DS) - * Inline part (N DS) + * Not aligned to cache lines, but to WQEs. + * First bytes of data (initial alignment) + * is going to be copied explicitly at the + * beginning of inlining buffer in Ethernet + * Segment. */ - ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE); - if (ds_cnt > MLX5_DSEG_MAX) { - unsigned int max_inline = (MLX5_DSEG_MAX - 2) * - MLX5_WQE_DWORD_SIZE; - - max_inline = max_inline - (max_inline % - RTE_CACHE_LINE_SIZE); - DRV_LOG(WARNING, - "port %u txq inline is too large (%d) setting" - " it to the maximum possible: %d\n", - PORT_ID(priv), txq_inline, max_inline); - txq_ctrl->txq.max_inline = max_inline / - RTE_CACHE_LINE_SIZE; + MLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE); + MLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX + + MLX5_ESEG_MIN_INLINE_SIZE - + MLX5_WQE_CSEG_SIZE - + MLX5_WQE_ESEG_SIZE - + MLX5_WQE_DSEG_SIZE * 2); + } else if (inlen_mode) { + /* + * If minimal inlining is requested we must + * enable inlining in general, despite the + * number of configured queues. Ignore the + * txq_inline_max devarg, this is not + * full-featured inline. + */ + inlen_send = inlen_mode; + inlen_empw = 0; + } else if (vlan_inline) { + /* + * Hardware does not report offload for + * VLAN insertion, we must enable data inline + * to implement feature by software. + */ + inlen_send = MLX5_ESEG_MIN_INLINE_SIZE; + inlen_empw = 0; + } else { + inlen_send = 0; + inlen_empw = 0; + } + txq_ctrl->txq.inlen_send = inlen_send; + txq_ctrl->txq.inlen_mode = inlen_mode; + txq_ctrl->txq.inlen_empw = 0; + if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) { + /* + * The data sent with MLX5_OPCODE_ENHANCED_MPSW + * may be inlined in Data Segment, align the + * length accordingly to fit entire WQEBBs. + */ + temp = RTE_MAX(inlen_empw, + MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE); + temp -= MLX5_DSEG_MIN_INLINE_SIZE; + temp = RTE_ALIGN(temp, MLX5_WQE_SIZE); + temp += MLX5_DSEG_MIN_INLINE_SIZE; + temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX + + MLX5_DSEG_MIN_INLINE_SIZE - + MLX5_WQE_CSEG_SIZE - + MLX5_WQE_ESEG_SIZE - + MLX5_WQE_DSEG_SIZE); + temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN); + if (temp != inlen_empw) { + DRV_LOG(INFO, + "port %u enhanced empw inline setting" + " aligned from %u to %u", + PORT_ID(priv), inlen_empw, temp); + inlen_empw = temp; } + MLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE); + MLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX + + MLX5_DSEG_MIN_INLINE_SIZE - + MLX5_WQE_CSEG_SIZE - + MLX5_WQE_ESEG_SIZE - + MLX5_WQE_DSEG_SIZE); + txq_ctrl->txq.inlen_empw = inlen_empw; } + txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw); if (tso) { - txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE; - txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline, - max_tso_inline); + txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER; + txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data, + MLX5_MAX_TSO_HEADER); txq_ctrl->txq.tso_en = 1; } - txq_ctrl->txq.tunnel_en = config->tunnel_en; + txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp; txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO | DEV_TX_OFFLOAD_UDP_TNL_TSO | DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) & txq_ctrl->txq.offloads) && config->swp; } +/** + * Adjust Tx queue data inline parameters for large queue sizes. + * The data inline feature requires multiple WQEs to fit the packets, + * and if the large amount of Tx descriptors is requested by application + * the total WQE amount may exceed the hardware capabilities. If the + * default inline setting are used we can try to adjust these ones and + * meet the hardware requirements and not exceed the queue size. + * + * @param txq_ctrl + * Pointer to Tx queue control structure. + * + * @return + * Zero on success, otherwise the parameters can not be adjusted. + */ +static int +txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl) +{ + struct mlx5_priv *priv = txq_ctrl->priv; + struct mlx5_dev_config *config = &priv->config; + unsigned int max_inline; + + max_inline = txq_calc_inline_max(txq_ctrl); + if (!txq_ctrl->txq.inlen_send) { + /* + * Inline data feature is not engaged at all. + * There is nothing to adjust. + */ + return 0; + } + if (txq_ctrl->max_inline_data <= max_inline) { + /* + * The requested inline data length does not + * exceed queue capabilities. + */ + return 0; + } + if (txq_ctrl->txq.inlen_mode > max_inline) { + DRV_LOG(ERR, + "minimal data inline requirements (%u) are not" + " satisfied (%u) on port %u, try the smaller" + " Tx queue size (%d)", + txq_ctrl->txq.inlen_mode, max_inline, + priv->dev_data->port_id, + priv->sh->device_attr.max_qp_wr); + goto error; + } + if (txq_ctrl->txq.inlen_send > max_inline && + config->txq_inline_max != MLX5_ARG_UNSET && + config->txq_inline_max > (int)max_inline) { + DRV_LOG(ERR, + "txq_inline_max requirements (%u) are not" + " satisfied (%u) on port %u, try the smaller" + " Tx queue size (%d)", + txq_ctrl->txq.inlen_send, max_inline, + priv->dev_data->port_id, + priv->sh->device_attr.max_qp_wr); + goto error; + } + if (txq_ctrl->txq.inlen_empw > max_inline && + config->txq_inline_mpw != MLX5_ARG_UNSET && + config->txq_inline_mpw > (int)max_inline) { + DRV_LOG(ERR, + "txq_inline_mpw requirements (%u) are not" + " satisfied (%u) on port %u, try the smaller" + " Tx queue size (%d)", + txq_ctrl->txq.inlen_empw, max_inline, + priv->dev_data->port_id, + priv->sh->device_attr.max_qp_wr); + goto error; + } + if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) { + DRV_LOG(ERR, + "tso header inline requirements (%u) are not" + " satisfied (%u) on port %u, try the smaller" + " Tx queue size (%d)", + MLX5_MAX_TSO_HEADER, max_inline, + priv->dev_data->port_id, + priv->sh->device_attr.max_qp_wr); + goto error; + } + if (txq_ctrl->txq.inlen_send > max_inline) { + DRV_LOG(WARNING, + "adjust txq_inline_max (%u->%u)" + " due to large Tx queue on port %u", + txq_ctrl->txq.inlen_send, max_inline, + priv->dev_data->port_id); + txq_ctrl->txq.inlen_send = max_inline; + } + if (txq_ctrl->txq.inlen_empw > max_inline) { + DRV_LOG(WARNING, + "adjust txq_inline_mpw (%u->%u)" + "due to large Tx queue on port %u", + txq_ctrl->txq.inlen_empw, max_inline, + priv->dev_data->port_id); + txq_ctrl->txq.inlen_empw = max_inline; + } + txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send, + txq_ctrl->txq.inlen_empw); + MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline); + MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline); + MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send); + MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw || + !txq_ctrl->txq.inlen_empw); + return 0; +error: + rte_errno = ENOMEM; + return -ENOMEM; +} + /** * Create a DPDK Tx queue. * @@ -735,13 +1102,11 @@ struct mlx5_txq_ctrl * mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_txconf *conf) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_txq_ctrl *tmpl; - tmpl = rte_calloc_socket("TXQ", 1, - sizeof(*tmpl) + - desc * sizeof(struct rte_mbuf *), - 0, socket); + tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) + + desc * sizeof(struct rte_mbuf *), 0, socket); if (!tmpl) { rte_errno = ENOMEM; return NULL; @@ -752,30 +1117,79 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, goto error; } /* Save pointer of global generation number to check memory event. */ - tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->mr.dev_gen; - assert(desc > MLX5_TX_COMP_THRESH); + tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->share_cache.dev_gen; + MLX5_ASSERT(desc > MLX5_TX_COMP_THRESH); tmpl->txq.offloads = conf->offloads | dev->data->dev_conf.txmode.offloads; tmpl->priv = priv; tmpl->socket = socket; tmpl->txq.elts_n = log2above(desc); - tmpl->idx = idx; + tmpl->txq.elts_s = desc; + tmpl->txq.elts_m = desc - 1; + tmpl->txq.port_id = dev->data->port_id; + tmpl->txq.idx = idx; txq_set_params(tmpl); - DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d", - dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr); - DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d", - dev->data->port_id, priv->device_attr.orig_attr.max_sge); - tmpl->txq.elts = - (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1); - tmpl->txq.stats.idx = idx; - rte_atomic32_inc(&tmpl->refcnt); + if (txq_adjust_params(tmpl)) + goto error; + if (txq_calc_wqebb_cnt(tmpl) > + priv->sh->device_attr.max_qp_wr) { + DRV_LOG(ERR, + "port %u Tx WQEBB count (%d) exceeds the limit (%d)," + " try smaller queue size", + dev->data->port_id, txq_calc_wqebb_cnt(tmpl), + priv->sh->device_attr.max_qp_wr); + rte_errno = ENOMEM; + goto error; + } + __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED); + tmpl->type = MLX5_TXQ_TYPE_STANDARD; LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); return tmpl; error: - rte_free(tmpl); + mlx5_free(tmpl); return NULL; } +/** + * Create a DPDK Tx hairpin queue. + * + * @param dev + * Pointer to Ethernet device. + * @param idx + * TX queue index. + * @param desc + * Number of descriptors to configure in queue. + * @param hairpin_conf + * The hairpin configuration. + * + * @return + * A DPDK queue object on success, NULL otherwise and rte_errno is set. + */ +struct mlx5_txq_ctrl * +mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + const struct rte_eth_hairpin_conf *hairpin_conf) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_ctrl *tmpl; + + tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0, + SOCKET_ID_ANY); + if (!tmpl) { + rte_errno = ENOMEM; + return NULL; + } + tmpl->priv = priv; + tmpl->socket = SOCKET_ID_ANY; + tmpl->txq.elts_n = log2above(desc); + tmpl->txq.port_id = dev->data->port_id; + tmpl->txq.idx = idx; + tmpl->hairpin_conf = *hairpin_conf; + tmpl->type = MLX5_TXQ_TYPE_HAIRPIN; + __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED); + LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next); + return tmpl; +} + /** * Get a Tx queue. * @@ -790,14 +1204,13 @@ error: struct mlx5_txq_ctrl * mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; struct mlx5_txq_ctrl *ctrl = NULL; - if ((*priv->txqs)[idx]) { - ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, - txq); - mlx5_txq_ibv_get(dev, idx); - rte_atomic32_inc(&ctrl->refcnt); + if (txq_data) { + ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq); + __atomic_fetch_add(&ctrl->refcnt, 1, __ATOMIC_RELAXED); } return ctrl; } @@ -816,27 +1229,36 @@ mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx) int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx) { - struct priv *priv = dev->data->dev_private; - struct mlx5_txq_ctrl *txq; - size_t page_size = sysconf(_SC_PAGESIZE); + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_ctrl *txq_ctrl; if (!(*priv->txqs)[idx]) return 0; - txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); - if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv)) - txq->ibv = NULL; - if (priv->uar_base) - munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg, - page_size), page_size); - if (rte_atomic32_dec_and_test(&txq->refcnt)) { - txq_free_elts(txq); - mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh); - LIST_REMOVE(txq, next); - rte_free(txq); + txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); + if (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) != 0) + return 1; + if (txq_ctrl->obj) { + priv->obj_ops.txq_obj_release(txq_ctrl->obj); + LIST_REMOVE(txq_ctrl->obj, next); + mlx5_free(txq_ctrl->obj); + txq_ctrl->obj = NULL; + } + if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) { + if (txq_ctrl->txq.fcqs) { + mlx5_free(txq_ctrl->txq.fcqs); + txq_ctrl->txq.fcqs = NULL; + } + txq_free_elts(txq_ctrl); + } + dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED; + if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) { + if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) + mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh); + LIST_REMOVE(txq_ctrl, next); + mlx5_free(txq_ctrl); (*priv->txqs)[idx] = NULL; - return 0; } - return 1; + return 0; } /** @@ -853,13 +1275,13 @@ mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx) int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx) { - struct priv *priv = dev->data->dev_private; + struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_txq_ctrl *txq; if (!(*priv->txqs)[idx]) return -1; txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq); - return (rte_atomic32_read(&txq->refcnt) == 1); + return (__atomic_load_n(&txq->refcnt, __ATOMIC_RELAXED) == 1); } /** @@ -874,14 +1296,46 @@ mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx) int mlx5_txq_verify(struct rte_eth_dev *dev) { - struct priv *priv = dev->data->dev_private; - struct mlx5_txq_ctrl *txq; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_txq_ctrl *txq_ctrl; int ret = 0; - LIST_FOREACH(txq, &priv->txqsctrl, next) { + LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) { DRV_LOG(DEBUG, "port %u Tx queue %u still referenced", - dev->data->port_id, txq->idx); + dev->data->port_id, txq_ctrl->txq.idx); ++ret; } return ret; } + +/** + * Set the Tx queue dynamic timestamp (mask and offset) + * + * @param[in] dev + * Pointer to the Ethernet device structure. + */ +void +mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_txq_data *data; + int off, nbit; + unsigned int i; + uint64_t mask = 0; + + nbit = rte_mbuf_dynflag_lookup + (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); + off = rte_mbuf_dynfield_lookup + (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL); + if (nbit >= 0 && off >= 0 && sh->txpp.refcnt) + mask = 1ULL << nbit; + for (i = 0; i != priv->txqs_n; ++i) { + data = (*priv->txqs)[i]; + if (!data) + continue; + data->sh = sh; + data->ts_mask = mask; + data->ts_offset = off; + } +}