X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_txq.c;h=89b16fda2bd67c3226af06d09ccc58e308cea0af;hb=7b7711bea5f4;hp=fbb263023e6564ae4d02b9d37cca7e3400a8ad08;hpb=50dcb0c521ca996f14e9121c176006cb669b6686;p=dpdk.git

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index fbb263023e..89b16fda2b 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -142,9 +142,6 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 		container_of(txq, struct mlx5_txq_ctrl, txq);
 	int ret = 0;
 
-	if (mlx5_is_secondary())
-		return -E_RTE_SECONDARY;
-
 	priv_lock(priv);
 	if (desc <= MLX5_TX_COMP_THRESH) {
 		WARN("%p: number of descriptors requested for TX queue %u"
@@ -203,9 +200,6 @@ mlx5_tx_queue_release(void *dpdk_txq)
 	struct priv *priv;
 	unsigned int i;
 
-	if (mlx5_is_secondary())
-		return;
-
 	if (txq == NULL)
 		return;
 	txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
@@ -359,7 +353,7 @@ mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
 		.pd = priv->pd,
 		.comp_mask = IBV_QP_INIT_ATTR_PD,
 	};
-	if (txq_data->inline_en)
+	if (txq_data->max_inline)
 		attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
 	if (txq_data->tso_en) {
 		attr.init.max_tso_header = txq_ctrl->max_tso_header;
@@ -424,7 +418,9 @@ mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
 		(volatile struct mlx5_cqe (*)[])
 		(uintptr_t)cq_info.buf;
 	txq_data->cq_ci = 0;
+#ifndef NDEBUG
 	txq_data->cq_pi = 0;
+#endif
 	txq_data->wqe_ci = 0;
 	txq_data->wqe_pi = 0;
 	txq_ibv->qp = tmpl.qp;
@@ -580,6 +576,7 @@ mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
 	assert(desc > MLX5_TX_COMP_THRESH);
 	tmpl->txq.flags = conf->txq_flags;
 	tmpl->priv = priv;
+	tmpl->socket = socket;
 	tmpl->txq.elts_n = log2above(desc);
 	if (priv->mps == MLX5_MPW_ENHANCED)
 		tmpl->txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
@@ -594,7 +591,6 @@ mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
 		tmpl->txq.max_inline =
 			((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
 			 RTE_CACHE_LINE_SIZE);
-		tmpl->txq.inline_en = 1;
 		/* TSO and MPS can't be enabled concurrently. */
 		assert(!priv->tso || !priv->mps);
 		if (priv->mps == MLX5_MPW_ENHANCED) {