X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmrvl%2Fmrvl_ethdev.c;h=e31376860df2c7f23540aec0e69fe66561c906a1;hb=b4d0fff30807adaac6722689eaa72b4460632d80;hp=c44a2bcf9ce448755893626886ac357edfb7da4a;hpb=004afcde781450158ea77ffb5a7d2e87ac802886;p=dpdk.git diff --git a/drivers/net/mrvl/mrvl_ethdev.c b/drivers/net/mrvl/mrvl_ethdev.c index c44a2bcf9c..e31376860d 100644 --- a/drivers/net/mrvl/mrvl_ethdev.c +++ b/drivers/net/mrvl/mrvl_ethdev.c @@ -1,38 +1,10 @@ -/*- - * BSD LICENSE - * - * Copyright(c) 2017 Marvell International Ltd. - * Copyright(c) 2017 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Semihalf nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Marvell International Ltd. + * Copyright(c) 2017 Semihalf. + * All rights reserved. */ -#include +#include #include #include #include @@ -94,6 +66,17 @@ /* Memory size (in bytes) for MUSDK dma buffers */ #define MRVL_MUSDK_DMA_MEMSIZE 41943040 +/** Port Rx offload capabilities */ +#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ + DEV_RX_OFFLOAD_JUMBO_FRAME | \ + DEV_RX_OFFLOAD_CRC_STRIP | \ + DEV_RX_OFFLOAD_CHECKSUM) + +/** Port Tx offloads capabilities */ +#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM) + static const char * const valid_args[] = { MRVL_IFACE_NAME_ARG, MRVL_CFG_ARG, @@ -111,6 +94,11 @@ struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; +struct mrvl_ifnames { + const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; + int idx; +}; + /* * To use buffer harvesting based on loopback port shadow queue structure * was introduced for buffers information bookkeeping. @@ -145,21 +133,17 @@ struct mrvl_txq { int queue_id; int port_id; uint64_t bytes_sent; + struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; }; -/* - * Every tx queue should have dedicated shadow tx queue. - * - * Ports assigned by DPDK might not start at zero or be continuous so - * as a workaround define shadow queues for each possible port so that - * we eventually fit somewhere. - */ -struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE]; - -/** Number of ports configured. */ -int mrvl_ports_nb; static int mrvl_lcore_first; static int mrvl_lcore_last; +static int mrvl_dev_num; + +static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); +static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, + struct pp2_hif *hif, unsigned int core_id, + struct mrvl_shadow_txq *sq, int qid, int force); static inline int mrvl_get_bpool_size(int pp2_id, int pool_id) @@ -186,6 +170,59 @@ mrvl_reserve_bit(int *bitmap, int max) return n; } +static int +mrvl_init_hif(int core_id) +{ + struct pp2_hif_params params; + char match[MRVL_MATCH_LEN]; + int ret; + + ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); + if (ret < 0) { + RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id); + return ret; + } + + snprintf(match, sizeof(match), "hif-%d", ret); + memset(¶ms, 0, sizeof(params)); + params.match = match; + params.out_size = MRVL_PP2_AGGR_TXQD_MAX; + ret = pp2_hif_init(¶ms, &hifs[core_id]); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id); + return ret; + } + + return 0; +} + +static inline struct pp2_hif* +mrvl_get_hif(struct mrvl_priv *priv, int core_id) +{ + int ret; + + if (likely(hifs[core_id] != NULL)) + return hifs[core_id]; + + rte_spinlock_lock(&priv->lock); + + ret = mrvl_init_hif(core_id); + if (ret < 0) { + RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id); + goto out; + } + + if (core_id < mrvl_lcore_first) + mrvl_lcore_first = core_id; + + if (core_id > mrvl_lcore_last) + mrvl_lcore_last = core_id; +out: + rte_spinlock_unlock(&priv->lock); + + return hifs[core_id]; +} + /** * Configure rss based on dpdk rss configuration. * @@ -248,13 +285,13 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (!dev->data->dev_conf.rxmode.hw_strip_crc) { + if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { RTE_LOG(INFO, PMD, "L2 CRC stripping is always enabled in hw\n"); - dev->data->dev_conf.rxmode.hw_strip_crc = 1; + dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP; } - if (dev->data->dev_conf.rxmode.hw_vlan_strip) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { RTE_LOG(INFO, PMD, "VLAN stripping not supported\n"); return -EINVAL; } @@ -264,17 +301,17 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (dev->data->dev_conf.rxmode.enable_scatter) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) { RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n"); return -EINVAL; } - if (dev->data->dev_conf.rxmode.enable_lro) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) { RTE_LOG(INFO, PMD, "LRO not supported\n"); return -EINVAL; } - if (dev->data->dev_conf.rxmode.jumbo_frame) + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - ETHER_HDR_LEN - ETHER_CRC_LEN; @@ -324,6 +361,9 @@ mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) return -EINVAL; + if (!priv->ppio) + return 0; + ret = pp2_ppio_set_mru(priv->ppio, mru); if (ret) return ret; @@ -346,6 +386,9 @@ mrvl_dev_set_link_up(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return -EPERM; + ret = pp2_ppio_enable(priv->ppio); if (ret) return ret; @@ -378,6 +421,9 @@ mrvl_dev_set_link_down(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; + if (!priv->ppio) + return -EPERM; + return pp2_ppio_disable(priv->ppio); } @@ -395,19 +441,12 @@ mrvl_dev_start(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; char match[MRVL_MATCH_LEN]; - int ret; + int ret = 0, def_init_size; snprintf(match, sizeof(match), "ppio-%d:%d", priv->pp_id, priv->ppio_id); priv->ppio_params.match = match; - /* - * Calculate the maximum bpool size for refill feature to 1.5 of the - * configured size. In case the bpool size will exceed this value, - * superfluous buffers will be removed - */ - priv->bpool_max_size = priv->bpool_init_size + - (priv->bpool_init_size >> 1); /* * Calculate the minimum bpool size for refill feature as follows: * 2 default burst sizes multiply by number of rx queues. @@ -416,9 +455,34 @@ mrvl_dev_start(struct rte_eth_dev *dev) */ priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; + /* In case initial bpool size configured in queues setup is + * smaller than minimum size add more buffers + */ + def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; + if (priv->bpool_init_size < def_init_size) { + int buffs_to_add = def_init_size - priv->bpool_init_size; + + priv->bpool_init_size += buffs_to_add; + ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); + if (ret) + RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n"); + } + + /* + * Calculate the maximum bpool size for refill feature as follows: + * maximum number of descriptors in rx queue multiply by number + * of rx queues plus minimum bpool size. + * In case the bpool size will exceed this value, superfluous buffers + * will be removed + */ + priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + + priv->bpool_min_size; + ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); - if (ret) + if (ret) { + RTE_LOG(ERR, PMD, "Failed to init ppio\n"); return ret; + } /* * In case there are some some stale uc/mc mac addresses flush them @@ -453,17 +517,20 @@ mrvl_dev_start(struct rte_eth_dev *dev) if (mrvl_qos_cfg) { ret = mrvl_start_qos_mapping(priv); if (ret) { - pp2_ppio_deinit(priv->ppio); - return ret; + RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n"); + goto out; } } ret = mrvl_dev_set_link_up(dev); - if (ret) + if (ret) { + RTE_LOG(ERR, PMD, "Failed to set link up\n"); goto out; + } return 0; out: + RTE_LOG(ERR, PMD, "Failed to start device\n"); pp2_ppio_deinit(priv->ppio); return ret; } @@ -505,21 +572,32 @@ mrvl_flush_rx_queues(struct rte_eth_dev *dev) static void mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) { - int i; + int i, j; + struct mrvl_txq *txq; RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n"); - for (i = 0; i < RTE_MAX_LCORE; i++) { - struct mrvl_shadow_txq *sq = - &shadow_txqs[dev->data->port_id][i]; + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = (struct mrvl_txq *)dev->data->tx_queues[i]; - while (sq->tail != sq->head) { - uint64_t addr = cookie_addr_high | + for (j = 0; j < RTE_MAX_LCORE; j++) { + struct mrvl_shadow_txq *sq; + + if (!hifs[j]) + continue; + + sq = &txq->shadow_txqs[j]; + mrvl_free_sent_buffers(txq->priv->ppio, + hifs[j], j, sq, txq->queue_id, 1); + while (sq->tail != sq->head) { + uint64_t addr = cookie_addr_high | sq->ent[sq->tail].buff.cookie; - rte_pktmbuf_free((struct rte_mbuf *)addr); - sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK; + rte_pktmbuf_free( + (struct rte_mbuf *)addr); + sq->tail = (sq->tail + 1) & + MRVL_PP2_TX_SHADOWQ_MASK; + } + memset(sq, 0, sizeof(*sq)); } - - memset(sq, 0, sizeof(*sq)); } } @@ -533,8 +611,15 @@ static void mrvl_flush_bpool(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; + struct pp2_hif *hif; uint32_t num; int ret; + unsigned int core_id = rte_lcore_id(); + + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(priv, core_id); ret = pp2_bpool_get_num_buffs(priv->bpool, &num); if (ret) { @@ -546,8 +631,7 @@ mrvl_flush_bpool(struct rte_eth_dev *dev) struct pp2_buff_inf inf; uint64_t addr; - ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool, - &inf); + ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); if (ret) break; @@ -570,9 +654,12 @@ mrvl_dev_stop(struct rte_eth_dev *dev) mrvl_dev_set_link_down(dev); mrvl_flush_rx_queues(dev); mrvl_flush_tx_shadow_queues(dev); - if (priv->qos_tbl) + if (priv->qos_tbl) { pp2_cls_qos_tbl_deinit(priv->qos_tbl); - pp2_ppio_deinit(priv->ppio); + priv->qos_tbl = NULL; + } + if (priv->ppio) + pp2_ppio_deinit(priv->ppio); priv->ppio = NULL; } @@ -624,6 +711,9 @@ mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) struct ifreq req; int ret, fd, link_up; + if (!priv->ppio) + return -EPERM; + edata.cmd = ETHTOOL_GSET; strcpy(req.ifr_name, dev->data->name); @@ -680,6 +770,9 @@ mrvl_promiscuous_enable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_set_promisc(priv->ppio, 1); if (ret) RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n"); @@ -697,6 +790,9 @@ mrvl_allmulticast_enable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); if (ret) RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n"); @@ -714,6 +810,9 @@ mrvl_promiscuous_disable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_set_promisc(priv->ppio, 0); if (ret) RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n"); @@ -731,6 +830,9 @@ mrvl_allmulticast_disable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); if (ret) RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n"); @@ -751,6 +853,9 @@ mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) char buf[ETHER_ADDR_FMT_SIZE]; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_remove_mac_addr(priv->ppio, dev->data->mac_addrs[index].addr_bytes); if (ret) { @@ -787,6 +892,9 @@ mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr, /* For setting index 0, mrvl_mac_addr_set() should be used.*/ return -1; + if (!priv->ppio) + return 0; + /* * Maximum number of uc addresses can be tuned via kernel module mvpp2x * parameter uc_filter_max. Maximum number of mc addresses is then @@ -824,6 +932,9 @@ mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return; + ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); if (ret) { char buf[ETHER_ADDR_FMT_SIZE]; @@ -851,6 +962,9 @@ mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) uint64_t drop_mac = 0; unsigned int i, idx, ret; + if (!priv->ppio) + return -EPERM; + for (i = 0; i < dev->data->nb_rx_queues; i++) { struct mrvl_rxq *rxq = dev->data->rx_queues[i]; struct pp2_ppio_inq_statistics rx_stats; @@ -943,6 +1057,9 @@ mrvl_stats_reset(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int i; + if (!priv->ppio) + return; + for (i = 0; i < dev->data->nb_rx_queues; i++) { struct mrvl_rxq *rxq = dev->data->rx_queues[i]; @@ -991,15 +1108,11 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; - info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_VLAN_FILTER | - DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM; + info->rx_offload_capa = MRVL_RX_OFFLOADS; + info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; - info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM; + info->tx_offload_capa = MRVL_TX_OFFLOADS; + info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; info->flow_type_rss_offloads = ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | @@ -1007,6 +1120,7 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, /* By default packets are dropped if no descriptors are available */ info->default_rxconf.rx_drop_en = 1; + info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP; info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; } @@ -1099,6 +1213,9 @@ mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) { struct mrvl_priv *priv = dev->data->dev_private; + if (!priv->ppio) + return -EPERM; + return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : pp2_ppio_remove_vlan(priv->ppio, vlan_id); } @@ -1120,9 +1237,19 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) struct buff_release_entry entries[MRVL_PP2_TXD_MAX]; struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX]; int i, ret; - unsigned int core_id = rte_lcore_id(); - struct pp2_hif *hif = hifs[core_id]; - struct pp2_bpool *bpool = rxq->priv->bpool; + unsigned int core_id; + struct pp2_hif *hif; + struct pp2_bpool *bpool; + + core_id = rte_lcore_id(); + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(rxq->priv, core_id); + if (!hif) + return -1; + + bpool = rxq->priv->bpool; ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); if (ret) @@ -1161,6 +1288,42 @@ out: return -1; } +/** + * Check whether requested rx queue offloads match port offloads. + * + * @param + * dev Pointer to the device. + * @param + * requested Bitmap of the requested offloads. + * + * @return + * 1 if requested offloads are okay, 0 otherwise. + */ +static int +mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested) +{ + uint64_t mandatory = dev->data->dev_conf.rxmode.offloads; + uint64_t supported = MRVL_RX_OFFLOADS; + uint64_t unsupported = requested & ~supported; + uint64_t missing = mandatory & ~requested; + + if (unsupported) { + RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. " + "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n", + requested, supported); + return 0; + } + + if (missing) { + RTE_LOG(ERR, PMD, "Some Rx offloads are missing. " + "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n", + requested, missing); + return 0; + } + + return 1; +} + /** * DPDK callback to configure the receive queue. * @@ -1173,7 +1336,7 @@ out: * @param socket * NUMA socket on which memory must be allocated. * @param conf - * Thresholds parameters (unused_). + * Thresholds parameters. * @param mp * Memory pool for buffer allocations. * @@ -1183,7 +1346,7 @@ out: static int mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, - const struct rte_eth_rxconf *conf __rte_unused, + const struct rte_eth_rxconf *conf, struct rte_mempool *mp) { struct mrvl_priv *priv = dev->data->dev_private; @@ -1192,6 +1355,9 @@ mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; int ret, tc, inq; + if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads)) + return -ENOTSUP; + if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { /* * Unknown TC mapping, mapping will not have a correct queue. @@ -1223,7 +1389,8 @@ mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rxq->priv = priv; rxq->mp = mp; - rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum; + rxq->cksum_enabled = + dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; rxq->queue_id = idx; rxq->port_id = dev->data->port_id; mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; @@ -1258,8 +1425,15 @@ mrvl_rx_queue_release(void *rxq) struct mrvl_rxq *q = rxq; struct pp2_ppio_tc_params *tc_params; int i, num, tc, inq; + struct pp2_hif *hif; + unsigned int core_id = rte_lcore_id(); - if (!q) + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(q->priv, core_id); + + if (!q || !hif) return; tc = q->priv->rxq_map[q->queue_id].tc; @@ -1270,7 +1444,7 @@ mrvl_rx_queue_release(void *rxq) struct pp2_buff_inf inf; uint64_t addr; - pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf); + pp2_bpool_get_buff(hif, q->priv->bpool, &inf); addr = cookie_addr_high | inf.cookie; rte_pktmbuf_free((struct rte_mbuf *)addr); } @@ -1278,6 +1452,42 @@ mrvl_rx_queue_release(void *rxq) rte_free(q); } +/** + * Check whether requested tx queue offloads match port offloads. + * + * @param + * dev Pointer to the device. + * @param + * requested Bitmap of the requested offloads. + * + * @return + * 1 if requested offloads are okay, 0 otherwise. + */ +static int +mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested) +{ + uint64_t mandatory = dev->data->dev_conf.txmode.offloads; + uint64_t supported = MRVL_TX_OFFLOADS; + uint64_t unsupported = requested & ~supported; + uint64_t missing = mandatory & ~requested; + + if (unsupported) { + RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. " + "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n", + requested, supported); + return 0; + } + + if (missing) { + RTE_LOG(ERR, PMD, "Some Rx offloads are missing. " + "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n", + requested, missing); + return 0; + } + + return 1; +} + /** * DPDK callback to configure the transmit queue. * @@ -1290,7 +1500,7 @@ mrvl_rx_queue_release(void *rxq) * @param socket * NUMA socket on which memory must be allocated. * @param conf - * Thresholds parameters (unused). + * Thresholds parameters. * * @return * 0 on success, negative error value otherwise. @@ -1298,11 +1508,14 @@ mrvl_rx_queue_release(void *rxq) static int mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, - const struct rte_eth_txconf *conf __rte_unused) + const struct rte_eth_txconf *conf) { struct mrvl_priv *priv = dev->data->dev_private; struct mrvl_txq *txq; + if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads)) + return -ENOTSUP; + if (dev->data->tx_queues[idx]) { rte_free(dev->data->tx_queues[idx]); dev->data->tx_queues[idx] = NULL; @@ -1546,9 +1759,12 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) struct pp2_bpool *bpool; int i, ret, rx_done = 0; int num; + struct pp2_hif *hif; unsigned int core_id = rte_lcore_id(); - if (unlikely(!q->priv->ppio)) + hif = mrvl_get_hif(q->priv, core_id); + + if (unlikely(!q->priv->ppio || !hif)) return 0; bpool = q->priv->bpool; @@ -1591,7 +1807,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) .cookie = (pp2_cookie_t)(uint64_t)mbuf, }; - pp2_bpool_put_buff(hifs[core_id], bpool, &binf); + pp2_bpool_put_buff(hif, bpool, &binf); mrvl_port_bpool_size [bpool->pp2_id][bpool->id][core_id]++; q->drop_mac++; @@ -1637,14 +1853,15 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) q->priv->bpool_init_size); for (i = 0; i < pkt_to_remove; i++) { - pp2_bpool_get_buff(hifs[core_id], bpool, &buff); + ret = pp2_bpool_get_buff(hif, bpool, &buff); + if (ret) + break; mbuf = (struct rte_mbuf *) (cookie_addr_high | buff.cookie); rte_pktmbuf_free(mbuf); } mrvl_port_bpool_size - [bpool->pp2_id][bpool->id][core_id] -= - pkt_to_remove; + [bpool->pp2_id][bpool->id][core_id] -= i; } rte_spinlock_unlock(&q->priv->lock); } @@ -1729,11 +1946,12 @@ mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, */ static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, - struct mrvl_shadow_txq *sq, int qid, int force) + unsigned int core_id, struct mrvl_shadow_txq *sq, + int qid, int force) { struct buff_release_entry *entry; uint16_t nb_done = 0, num = 0, skip_bufs = 0; - int i, core_id = rte_lcore_id(); + int i; pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); @@ -1780,6 +1998,7 @@ skip: sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; sq->size -= num; num = 0; + skip_bufs = 0; } if (likely(num)) { @@ -1806,18 +2025,23 @@ static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { struct mrvl_txq *q = txq; - struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()]; - struct pp2_hif *hif = hifs[rte_lcore_id()]; + struct mrvl_shadow_txq *sq; + struct pp2_hif *hif; struct pp2_ppio_desc descs[nb_pkts]; + unsigned int core_id = rte_lcore_id(); int i, ret, bytes_sent = 0; uint16_t num, sq_free_size; uint64_t addr; - if (unlikely(!q->priv->ppio)) + hif = mrvl_get_hif(q->priv, core_id); + sq = &q->shadow_txqs[core_id]; + + if (unlikely(!q->priv->ppio || !hif)) return 0; if (sq->size) - mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0); + mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, + sq, q->queue_id, 0); sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; if (unlikely(nb_pkts > sq_free_size)) { @@ -1845,8 +2069,9 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) sq->ent[sq->head].buff.addr = rte_mbuf_data_iova_default(mbuf); sq->ent[sq->head].bpool = - (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ? - NULL : mrvl_port_to_bpool_lookup[mbuf->port]; + (unlikely(mbuf->port >= RTE_MAX_ETHPORTS || + mbuf->refcnt > 1)) ? NULL : + mrvl_port_to_bpool_lookup[mbuf->port]; sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; sq->size++; @@ -2023,6 +2248,7 @@ mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst; + eth_dev->data->kdrv = RTE_KDRV_NONE; eth_dev->data->dev_private = priv; eth_dev->device = &vdev->device; eth_dev->dev_ops = &mrvl_ops; @@ -2056,6 +2282,7 @@ mrvl_eth_dev_destroy(const char *name) priv = eth_dev->data->dev_private; pp2_bpool_deinit(priv->bpool); + used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); rte_free(priv); rte_free(eth_dev->data->mac_addrs); rte_eth_dev_release_port(eth_dev); @@ -2079,41 +2306,9 @@ static int mrvl_get_ifnames(const char *key __rte_unused, const char *value, void *extra_args) { - const char **ifnames = extra_args; + struct mrvl_ifnames *ifnames = extra_args; - ifnames[mrvl_ports_nb++] = value; - - return 0; -} - -/** - * Initialize per-lcore MUSDK hardware interfaces (hifs). - * - * @return - * 0 on success, negative error value otherwise. - */ -static int -mrvl_init_hifs(void) -{ - struct pp2_hif_params params; - char match[MRVL_MATCH_LEN]; - int i, ret; - - RTE_LCORE_FOREACH(i) { - ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); - if (ret < 0) - return ret; - - snprintf(match, sizeof(match), "hif-%d", ret); - memset(¶ms, 0, sizeof(params)); - params.match = match; - params.out_size = MRVL_PP2_AGGR_TXQD_MAX; - ret = pp2_hif_init(¶ms, &hifs[i]); - if (ret) { - RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i); - return ret; - } - } + ifnames->names[ifnames->idx++] = value; return 0; } @@ -2126,19 +2321,12 @@ mrvl_deinit_hifs(void) { int i; - RTE_LCORE_FOREACH(i) { + for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { if (hifs[i]) pp2_hif_deinit(hifs[i]); } -} - -static void mrvl_set_first_last_cores(int core_id) -{ - if (core_id < mrvl_lcore_first) - mrvl_lcore_first = core_id; - - if (core_id > mrvl_lcore_last) - mrvl_lcore_last = core_id; + used_hifs = MRVL_MUSDK_HIFS_RESERVED; + memset(hifs, 0, sizeof(hifs)); } /** @@ -2154,9 +2342,9 @@ static int rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) { struct rte_kvargs *kvlist; - const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; + struct mrvl_ifnames ifnames; int ret = -EINVAL; - uint32_t i, ifnum, cfgnum, core_id; + uint32_t i, ifnum, cfgnum; const char *params; params = rte_vdev_device_args(vdev); @@ -2168,21 +2356,34 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) return -EINVAL; ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); - if (ifnum > RTE_DIM(ifnames)) + if (ifnum > RTE_DIM(ifnames.names)) goto out_free_kvlist; + ifnames.idx = 0; rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, mrvl_get_ifnames, &ifnames); - cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); - if (cfgnum > 1) { - RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n"); - goto out_free_kvlist; - } else if (cfgnum == 1) { - rte_kvargs_process(kvlist, MRVL_CFG_ARG, - mrvl_get_qoscfg, &mrvl_qos_cfg); + + /* + * The below system initialization should be done only once, + * on the first provided configuration file + */ + if (!mrvl_qos_cfg) { + cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); + RTE_LOG(INFO, PMD, "Parsing config file!\n"); + if (cfgnum > 1) { + RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n"); + goto out_free_kvlist; + } else if (cfgnum == 1) { + rte_kvargs_process(kvlist, MRVL_CFG_ARG, + mrvl_get_qoscfg, &mrvl_qos_cfg); + } } + if (mrvl_dev_num) + goto init_devices; + + RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n"); /* * ret == -EEXIST is correct, it means DMA * has been already initialized (by another PMD). @@ -2202,37 +2403,33 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) goto out_deinit_dma; } - ret = mrvl_init_hifs(); - if (ret) - goto out_deinit_hifs; + memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); + memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); + mrvl_lcore_first = RTE_MAX_LCORE; + mrvl_lcore_last = 0; + +init_devices: for (i = 0; i < ifnum; i++) { - RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]); - ret = mrvl_eth_dev_create(vdev, ifnames[i]); + RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]); + ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); if (ret) goto out_cleanup; } + mrvl_dev_num += ifnum; rte_kvargs_free(kvlist); - memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); - - mrvl_lcore_first = RTE_MAX_LCORE; - mrvl_lcore_last = 0; - - RTE_LCORE_FOREACH(core_id) { - mrvl_set_first_last_cores(core_id); - } - return 0; out_cleanup: for (; i > 0; i--) - mrvl_eth_dev_destroy(ifnames[i]); -out_deinit_hifs: - mrvl_deinit_hifs(); - mrvl_deinit_pp2(); + mrvl_eth_dev_destroy(ifnames.names[i]); + + if (mrvl_dev_num == 0) + mrvl_deinit_pp2(); out_deinit_dma: - mv_sys_dma_mem_destroy(); + if (mrvl_dev_num == 0) + mv_sys_dma_mem_destroy(); out_free_kvlist: rte_kvargs_free(kvlist); @@ -2265,11 +2462,15 @@ rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) rte_eth_dev_get_name_by_port(i, ifname); mrvl_eth_dev_destroy(ifname); + mrvl_dev_num--; } - mrvl_deinit_hifs(); - mrvl_deinit_pp2(); - mv_sys_dma_mem_destroy(); + if (mrvl_dev_num == 0) { + RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n"); + mrvl_deinit_hifs(); + mrvl_deinit_pp2(); + mv_sys_dma_mem_destroy(); + } return 0; }