X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fngbe%2Fngbe_ethdev.c;h=a0b7dd995bfc62fd6d90d8fd5d15864cf281c1a0;hb=b7aad633b345d7c6da5ec0483ec0bc5793afb04b;hp=0e588eeccef8a1ecd0cb541951ef33030d7732a9;hpb=b83372a03045458ecec9bdb6fca463bf326de751;p=dpdk.git diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 0e588eecce..a0b7dd995b 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -13,6 +13,67 @@ #include "ngbe.h" #include "ngbe_ethdev.h" #include "ngbe_rxtx.h" +#include "ngbe_regs_group.h" + +static const struct reg_info ngbe_regs_general[] = { + {NGBE_RST, 1, 1, "NGBE_RST"}, + {NGBE_STAT, 1, 1, "NGBE_STAT"}, + {NGBE_PORTCTL, 1, 1, "NGBE_PORTCTL"}, + {NGBE_GPIODATA, 1, 1, "NGBE_GPIODATA"}, + {NGBE_GPIOCTL, 1, 1, "NGBE_GPIOCTL"}, + {NGBE_LEDCTL, 1, 1, "NGBE_LEDCTL"}, + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_nvm[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_interrupt[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_fctl_others[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_rxdma[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_rx[] = { + {0, 0, 0, ""} +}; + +static struct reg_info ngbe_regs_tx[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_wakeup[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_mac[] = { + {0, 0, 0, ""} +}; + +static const struct reg_info ngbe_regs_diagnostic[] = { + {0, 0, 0, ""}, +}; + +/* PF registers */ +static const struct reg_info *ngbe_regs_others[] = { + ngbe_regs_general, + ngbe_regs_nvm, + ngbe_regs_interrupt, + ngbe_regs_fctl_others, + ngbe_regs_rxdma, + ngbe_regs_rx, + ngbe_regs_tx, + ngbe_regs_wakeup, + ngbe_regs_mac, + ngbe_regs_diagnostic, + NULL}; static int ngbe_dev_close(struct rte_eth_dev *dev); static int ngbe_dev_link_update(struct rte_eth_dev *dev, @@ -254,11 +315,14 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) struct rte_intr_handle *intr_handle = pci_dev->intr_handle; const struct rte_memzone *mz; uint32_t ctrl_ext; - int err; + int err, ret; PMD_INIT_FUNC_TRACE(); eth_dev->dev_ops = &ngbe_eth_dev_ops; + eth_dev->rx_queue_count = ngbe_dev_rx_queue_count; + eth_dev->rx_descriptor_status = ngbe_dev_rx_descriptor_status; + eth_dev->tx_descriptor_status = ngbe_dev_tx_descriptor_status; eth_dev->rx_pkt_burst = &ngbe_recv_pkts; eth_dev->tx_pkt_burst = &ngbe_xmit_pkts; eth_dev->tx_pkt_prepare = &ngbe_prep_pkts; @@ -317,6 +381,14 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) /* Unlock any pending hardware semaphore */ ngbe_swfw_lock_reset(hw); + /* Get Hardware Flow Control setting */ + hw->fc.requested_mode = ngbe_fc_full; + hw->fc.current_mode = ngbe_fc_full; + hw->fc.pause_time = NGBE_FC_PAUSE_TIME; + hw->fc.low_water = NGBE_FC_XON_LOTH; + hw->fc.high_water = NGBE_FC_XOFF_HITH; + hw->fc.send_xon = 1; + err = hw->rom.init_params(hw); if (err != 0) { PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); @@ -374,6 +446,16 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) /* initialize the hw strip bitmap*/ memset(hwstrip, 0, sizeof(*hwstrip)); + /* initialize PF if max_vfs not zero */ + ret = ngbe_pf_host_init(eth_dev); + if (ret) { + rte_free(eth_dev->data->mac_addrs); + eth_dev->data->mac_addrs = NULL; + rte_free(eth_dev->data->hash_mac_addrs); + eth_dev->data->hash_mac_addrs = NULL; + return ret; + } + ctrl_ext = rd32(hw, NGBE_PORTCTL); /* let hardware know driver is loaded */ ctrl_ext |= NGBE_PORTCTL_DRVLOAD; @@ -807,6 +889,9 @@ ngbe_dev_configure(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; + /* set flag to update link status after init */ intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; @@ -874,6 +959,9 @@ ngbe_dev_start(struct rte_eth_dev *dev) hw->mac.start_hw(hw); hw->mac.get_link_status = true; + /* configure PF module if SRIOV enabled */ + ngbe_pf_host_configure(dev); + ngbe_dev_phy_intr_setup(dev); /* check and configure queue intr-vector mapping */ @@ -924,6 +1012,10 @@ ngbe_dev_start(struct rte_eth_dev *dev) goto error; } + /* Skip link setup if loopback mode is enabled. */ + if (hw->is_pf && dev->data->dev_conf.lpbk_mode) + goto skip_link_setup; + err = hw->mac.check_link(hw, &speed, &link_up, 0); if (err != 0) goto error; @@ -967,6 +1059,8 @@ ngbe_dev_start(struct rte_eth_dev *dev) if (err != 0) goto error; +skip_link_setup: + if (rte_intr_allow_others(intr_handle)) { ngbe_dev_misc_interrupt_setup(dev); /* check if lsc interrupt is enabled */ @@ -1025,9 +1119,12 @@ static int ngbe_dev_stop(struct rte_eth_dev *dev) { struct rte_eth_link link; + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_vf_info *vfinfo = *NGBE_DEV_VFDATA(dev); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = pci_dev->intr_handle; + int vf; if (hw->adapter_stopped) return 0; @@ -1050,6 +1147,9 @@ ngbe_dev_stop(struct rte_eth_dev *dev) /* stop adapter */ ngbe_stop_hw(hw); + for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) + vfinfo[vf].clear_to_send = false; + ngbe_dev_clear_queues(dev); /* Clear stored conf */ @@ -1069,6 +1169,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev) rte_intr_efd_disable(intr_handle); rte_intr_vec_list_free(intr_handle); + adapter->rss_reta_updated = 0; + hw->adapter_stopped = true; dev->data->dev_started = 0; @@ -1117,6 +1219,9 @@ ngbe_dev_close(struct rte_eth_dev *dev) rte_delay_ms(100); } while (retries++ < (10 + NGBE_LINK_UP_TIME)); + /* uninitialize PF if max_vfs not zero */ + ngbe_pf_host_uninit(dev); + rte_free(dev->data->mac_addrs); dev->data->mac_addrs = NULL; @@ -1134,6 +1239,15 @@ ngbe_dev_reset(struct rte_eth_dev *dev) { int ret; + /* When a DPDK PMD PF begin to reset PF port, it should notify all + * its VF to make them align with it. The detailed notification + * mechanism is PMD specific. As to ngbe PF, it is rather complex. + * To avoid unexpected behavior in VF, currently reset of PF with + * SR-IOV activation is not supported. It might be supported later. + */ + if (dev->data->sriov.active) + return -ENOTSUP; + ret = eth_ngbe_dev_uninit(dev); if (ret != 0) return ret; @@ -1595,15 +1709,37 @@ ngbe_dev_xstats_reset(struct rte_eth_dev *dev) return 0; } +static int +ngbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + int ret; + + ret = snprintf(fw_version, fw_size, "0x%08x", hw->eeprom_id); + + if (ret < 0) + return -EINVAL; + + ret += 1; /* add the size of '\0' */ + if (fw_size < (size_t)ret) + return ret; + + return 0; +} + static int ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct ngbe_hw *hw = ngbe_dev_hw(dev); dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; dev_info->min_rx_bufsize = 1024; dev_info->max_rx_pktlen = 15872; + dev_info->max_mac_addrs = hw->mac.num_rar_entries; + dev_info->max_hash_mac_addrs = NGBE_VMDQ_NUM_UC_MAC; + dev_info->max_vfs = pci_dev->max_vfs; dev_info->rx_queue_offload_capa = ngbe_get_rx_queue_offloads(dev); dev_info->rx_offload_capa = (ngbe_get_rx_port_offloads(dev) | dev_info->rx_queue_offload_capa); @@ -1634,6 +1770,10 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_desc_lim = rx_desc_lim; dev_info->tx_desc_lim = tx_desc_lim; + dev_info->hash_key_size = NGBE_HKEY_MAX_INDEX * sizeof(uint32_t); + dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128; + dev_info->flow_type_rss_offloads = NGBE_RSS_OFFLOAD_ALL; + dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_10M; @@ -1999,6 +2139,11 @@ ngbe_dev_interrupt_action(struct rte_eth_dev *dev) PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); + if (intr->flags & NGBE_FLAG_MAILBOX) { + ngbe_pf_mbx_process(dev); + intr->flags &= ~NGBE_FLAG_MAILBOX; + } + if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) { struct rte_eth_link link; @@ -2059,6 +2204,8 @@ ngbe_dev_interrupt_delayed_handler(void *param) ngbe_disable_intr(hw); eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC]; + if (eicr & NGBE_ICRMISC_VFMBX) + ngbe_pf_mbx_process(dev); if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) { ngbe_dev_link_update(dev, 0); @@ -2100,6 +2247,236 @@ ngbe_dev_interrupt_handler(void *param) ngbe_dev_interrupt_action(dev); } +static int +ngbe_dev_led_on(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + return hw->mac.led_on(hw, 0) == 0 ? 0 : -ENOTSUP; +} + +static int +ngbe_dev_led_off(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + return hw->mac.led_off(hw, 0) == 0 ? 0 : -ENOTSUP; +} + +static int +ngbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t mflcn_reg; + uint32_t fccfg_reg; + int rx_pause; + int tx_pause; + + fc_conf->pause_time = hw->fc.pause_time; + fc_conf->high_water = hw->fc.high_water; + fc_conf->low_water = hw->fc.low_water; + fc_conf->send_xon = hw->fc.send_xon; + fc_conf->autoneg = !hw->fc.disable_fc_autoneg; + + /* + * Return rx_pause status according to actual setting of + * RXFCCFG register. + */ + mflcn_reg = rd32(hw, NGBE_RXFCCFG); + if (mflcn_reg & NGBE_RXFCCFG_FC) + rx_pause = 1; + else + rx_pause = 0; + + /* + * Return tx_pause status according to actual setting of + * TXFCCFG register. + */ + fccfg_reg = rd32(hw, NGBE_TXFCCFG); + if (fccfg_reg & NGBE_TXFCCFG_FC) + tx_pause = 1; + else + tx_pause = 0; + + if (rx_pause && tx_pause) + fc_conf->mode = RTE_ETH_FC_FULL; + else if (rx_pause) + fc_conf->mode = RTE_ETH_FC_RX_PAUSE; + else if (tx_pause) + fc_conf->mode = RTE_ETH_FC_TX_PAUSE; + else + fc_conf->mode = RTE_ETH_FC_NONE; + + return 0; +} + +static int +ngbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + int err; + uint32_t rx_buf_size; + uint32_t max_high_water; + enum ngbe_fc_mode rte_fcmode_2_ngbe_fcmode[] = { + ngbe_fc_none, + ngbe_fc_rx_pause, + ngbe_fc_tx_pause, + ngbe_fc_full + }; + + PMD_INIT_FUNC_TRACE(); + + rx_buf_size = rd32(hw, NGBE_PBRXSIZE); + PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); + + /* + * At least reserve one Ethernet frame for watermark + * high_water/low_water in kilo bytes for ngbe + */ + max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; + if (fc_conf->high_water > max_high_water || + fc_conf->high_water < fc_conf->low_water) { + PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); + PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); + return -EINVAL; + } + + hw->fc.requested_mode = rte_fcmode_2_ngbe_fcmode[fc_conf->mode]; + hw->fc.pause_time = fc_conf->pause_time; + hw->fc.high_water = fc_conf->high_water; + hw->fc.low_water = fc_conf->low_water; + hw->fc.send_xon = fc_conf->send_xon; + hw->fc.disable_fc_autoneg = !fc_conf->autoneg; + + err = hw->mac.fc_enable(hw); + + /* Not negotiated is not an error case */ + if (err == 0 || err == NGBE_ERR_FC_NOT_NEGOTIATED) { + wr32m(hw, NGBE_MACRXFLT, NGBE_MACRXFLT_CTL_MASK, + (fc_conf->mac_ctrl_frame_fwd + ? NGBE_MACRXFLT_CTL_NOPS : NGBE_MACRXFLT_CTL_DROP)); + ngbe_flush(hw); + + return 0; + } + + PMD_INIT_LOG(ERR, "ngbe_fc_enable = 0x%x", err); + return -EIO; +} + +int +ngbe_dev_rss_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + uint8_t i, j, mask; + uint32_t reta; + uint16_t idx, shift; + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + struct ngbe_hw *hw = ngbe_dev_hw(dev); + + PMD_INIT_FUNC_TRACE(); + + if (!hw->is_pf) { + PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " + "NIC."); + return -ENOTSUP; + } + + if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); + return -EINVAL; + } + + for (i = 0; i < reta_size; i += 4) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); + if (!mask) + continue; + + reta = rd32a(hw, NGBE_REG_RSSTBL, i >> 2); + for (j = 0; j < 4; j++) { + if (RS8(mask, j, 0x1)) { + reta &= ~(MS32(8 * j, 0xFF)); + reta |= LS32(reta_conf[idx].reta[shift + j], + 8 * j, 0xFF); + } + } + wr32a(hw, NGBE_REG_RSSTBL, i >> 2, reta); + } + adapter->rss_reta_updated = 1; + + return 0; +} + +int +ngbe_dev_rss_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint8_t i, j, mask; + uint32_t reta; + uint16_t idx, shift; + + PMD_INIT_FUNC_TRACE(); + + if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); + return -EINVAL; + } + + for (i = 0; i < reta_size; i += 4) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); + if (!mask) + continue; + + reta = rd32a(hw, NGBE_REG_RSSTBL, i >> 2); + for (j = 0; j < 4; j++) { + if (RS8(mask, j, 0x1)) + reta_conf[idx].reta[shift + j] = + (uint16_t)RS32(reta, 8 * j, 0xFF); + } + } + + return 0; +} + +static int +ngbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, + uint32_t index, uint32_t pool) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t enable_addr = 1; + + return ngbe_set_rar(hw, index, mac_addr->addr_bytes, + pool, enable_addr); +} + +static void +ngbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + + ngbe_clear_rar(hw, index); +} + +static int +ngbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + ngbe_remove_rar(dev, 0); + ngbe_add_rar(dev, addr, 0, pci_dev->max_vfs); + + return 0; +} + static int ngbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { @@ -2127,6 +2504,116 @@ ngbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) return 0; } +static uint32_t +ngbe_uta_vector(struct ngbe_hw *hw, struct rte_ether_addr *uc_addr) +{ + uint32_t vector = 0; + + switch (hw->mac.mc_filter_type) { + case 0: /* use bits [47:36] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 4) | + (((uint16_t)uc_addr->addr_bytes[5]) << 4)); + break; + case 1: /* use bits [46:35] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 3) | + (((uint16_t)uc_addr->addr_bytes[5]) << 5)); + break; + case 2: /* use bits [45:34] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 2) | + (((uint16_t)uc_addr->addr_bytes[5]) << 6)); + break; + case 3: /* use bits [43:32] of the address */ + vector = ((uc_addr->addr_bytes[4]) | + (((uint16_t)uc_addr->addr_bytes[5]) << 8)); + break; + default: /* Invalid mc_filter_type */ + break; + } + + /* vector can only be 12-bits or boundary will be exceeded */ + vector &= 0xFFF; + return vector; +} + +static int +ngbe_uc_hash_table_set(struct rte_eth_dev *dev, + struct rte_ether_addr *mac_addr, uint8_t on) +{ + uint32_t vector; + uint32_t uta_idx; + uint32_t reg_val; + uint32_t uta_mask; + uint32_t psrctl; + + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_uta_info *uta_info = NGBE_DEV_UTA_INFO(dev); + + vector = ngbe_uta_vector(hw, mac_addr); + uta_idx = (vector >> 5) & 0x7F; + uta_mask = 0x1UL << (vector & 0x1F); + + if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) + return 0; + + reg_val = rd32(hw, NGBE_UCADDRTBL(uta_idx)); + if (on) { + uta_info->uta_in_use++; + reg_val |= uta_mask; + uta_info->uta_shadow[uta_idx] |= uta_mask; + } else { + uta_info->uta_in_use--; + reg_val &= ~uta_mask; + uta_info->uta_shadow[uta_idx] &= ~uta_mask; + } + + wr32(hw, NGBE_UCADDRTBL(uta_idx), reg_val); + + psrctl = rd32(hw, NGBE_PSRCTL); + if (uta_info->uta_in_use > 0) + psrctl |= NGBE_PSRCTL_UCHFENA; + else + psrctl &= ~NGBE_PSRCTL_UCHFENA; + + psrctl &= ~NGBE_PSRCTL_ADHF12_MASK; + psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); + wr32(hw, NGBE_PSRCTL, psrctl); + + return 0; +} + +static int +ngbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_uta_info *uta_info = NGBE_DEV_UTA_INFO(dev); + uint32_t psrctl; + int i; + + if (on) { + for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { + uta_info->uta_shadow[i] = ~0; + wr32(hw, NGBE_UCADDRTBL(i), ~0); + } + } else { + for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { + uta_info->uta_shadow[i] = 0; + wr32(hw, NGBE_UCADDRTBL(i), 0); + } + } + + psrctl = rd32(hw, NGBE_PSRCTL); + if (on) + psrctl |= NGBE_PSRCTL_UCHFENA; + else + psrctl &= ~NGBE_PSRCTL_UCHFENA; + + psrctl &= ~NGBE_PSRCTL_ADHF12_MASK; + psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); + wr32(hw, NGBE_PSRCTL, psrctl); + + return 0; +} + /** * Set the IVAR registers, mapping interrupt causes to vectors * @param hw @@ -2221,6 +2708,335 @@ ngbe_configure_msix(struct rte_eth_dev *dev) | NGBE_ITR_WRDSA); } +static u8 * +ngbe_dev_addr_list_itr(__rte_unused struct ngbe_hw *hw, + u8 **mc_addr_ptr, u32 *vmdq) +{ + u8 *mc_addr; + + *vmdq = 0; + mc_addr = *mc_addr_ptr; + *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); + return mc_addr; +} + +int +ngbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + u8 *mc_addr_list; + + mc_addr_list = (u8 *)mc_addr_set; + return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, + ngbe_dev_addr_list_itr, TRUE); +} + +static uint64_t +ngbe_read_systime_cyclecounter(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint64_t systime_cycles; + + systime_cycles = (uint64_t)rd32(hw, NGBE_TSTIMEL); + systime_cycles |= (uint64_t)rd32(hw, NGBE_TSTIMEH) << 32; + + return systime_cycles; +} + +static uint64_t +ngbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint64_t rx_tstamp_cycles; + + /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ + rx_tstamp_cycles = (uint64_t)rd32(hw, NGBE_TSRXSTMPL); + rx_tstamp_cycles |= (uint64_t)rd32(hw, NGBE_TSRXSTMPH) << 32; + + return rx_tstamp_cycles; +} + +static uint64_t +ngbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint64_t tx_tstamp_cycles; + + /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ + tx_tstamp_cycles = (uint64_t)rd32(hw, NGBE_TSTXSTMPL); + tx_tstamp_cycles |= (uint64_t)rd32(hw, NGBE_TSTXSTMPH) << 32; + + return tx_tstamp_cycles; +} + +static void +ngbe_start_timecounters(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + uint32_t incval = 0; + uint32_t shift = 0; + + incval = NGBE_INCVAL_1GB; + shift = NGBE_INCVAL_SHIFT_1GB; + + wr32(hw, NGBE_TSTIMEINC, NGBE_TSTIMEINC_IV(incval)); + + memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); + memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); + memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); + + adapter->systime_tc.cc_mask = NGBE_CYCLECOUNTER_MASK; + adapter->systime_tc.cc_shift = shift; + adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; + + adapter->rx_tstamp_tc.cc_mask = NGBE_CYCLECOUNTER_MASK; + adapter->rx_tstamp_tc.cc_shift = shift; + adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; + + adapter->tx_tstamp_tc.cc_mask = NGBE_CYCLECOUNTER_MASK; + adapter->tx_tstamp_tc.cc_shift = shift; + adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; +} + +static int +ngbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) +{ + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + + adapter->systime_tc.nsec += delta; + adapter->rx_tstamp_tc.nsec += delta; + adapter->tx_tstamp_tc.nsec += delta; + + return 0; +} + +static int +ngbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) +{ + uint64_t ns; + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + + ns = rte_timespec_to_ns(ts); + /* Set the timecounters to a new value. */ + adapter->systime_tc.nsec = ns; + adapter->rx_tstamp_tc.nsec = ns; + adapter->tx_tstamp_tc.nsec = ns; + + return 0; +} + +static int +ngbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) +{ + uint64_t ns, systime_cycles; + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + + systime_cycles = ngbe_read_systime_cyclecounter(dev); + ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); + *ts = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ngbe_timesync_enable(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t tsync_ctl; + + /* Stop the timesync system time. */ + wr32(hw, NGBE_TSTIMEINC, 0x0); + /* Reset the timesync system time value. */ + wr32(hw, NGBE_TSTIMEL, 0x0); + wr32(hw, NGBE_TSTIMEH, 0x0); + + ngbe_start_timecounters(dev); + + /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ + wr32(hw, NGBE_ETFLT(NGBE_ETF_ID_1588), + RTE_ETHER_TYPE_1588 | NGBE_ETFLT_ENA | NGBE_ETFLT_1588); + + /* Enable timestamping of received PTP packets. */ + tsync_ctl = rd32(hw, NGBE_TSRXCTL); + tsync_ctl |= NGBE_TSRXCTL_ENA; + wr32(hw, NGBE_TSRXCTL, tsync_ctl); + + /* Enable timestamping of transmitted PTP packets. */ + tsync_ctl = rd32(hw, NGBE_TSTXCTL); + tsync_ctl |= NGBE_TSTXCTL_ENA; + wr32(hw, NGBE_TSTXCTL, tsync_ctl); + + ngbe_flush(hw); + + return 0; +} + +static int +ngbe_timesync_disable(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t tsync_ctl; + + /* Disable timestamping of transmitted PTP packets. */ + tsync_ctl = rd32(hw, NGBE_TSTXCTL); + tsync_ctl &= ~NGBE_TSTXCTL_ENA; + wr32(hw, NGBE_TSTXCTL, tsync_ctl); + + /* Disable timestamping of received PTP packets. */ + tsync_ctl = rd32(hw, NGBE_TSRXCTL); + tsync_ctl &= ~NGBE_TSRXCTL_ENA; + wr32(hw, NGBE_TSRXCTL, tsync_ctl); + + /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ + wr32(hw, NGBE_ETFLT(NGBE_ETF_ID_1588), 0); + + /* Stop incrementating the System Time registers. */ + wr32(hw, NGBE_TSTIMEINC, 0); + + return 0; +} + +static int +ngbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags __rte_unused) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + uint32_t tsync_rxctl; + uint64_t rx_tstamp_cycles; + uint64_t ns; + + tsync_rxctl = rd32(hw, NGBE_TSRXCTL); + if ((tsync_rxctl & NGBE_TSRXCTL_VLD) == 0) + return -EINVAL; + + rx_tstamp_cycles = ngbe_read_rx_tstamp_cyclecounter(dev); + ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); + *timestamp = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ngbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_adapter *adapter = ngbe_dev_adapter(dev); + uint32_t tsync_txctl; + uint64_t tx_tstamp_cycles; + uint64_t ns; + + tsync_txctl = rd32(hw, NGBE_TSTXCTL); + if ((tsync_txctl & NGBE_TSTXCTL_VLD) == 0) + return -EINVAL; + + tx_tstamp_cycles = ngbe_read_tx_tstamp_cyclecounter(dev); + ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); + *timestamp = rte_ns_to_timespec(ns); + + return 0; +} + +static int +ngbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) +{ + int count = 0; + int g_ind = 0; + const struct reg_info *reg_group; + const struct reg_info **reg_set = ngbe_regs_others; + + while ((reg_group = reg_set[g_ind++])) + count += ngbe_regs_group_count(reg_group); + + return count; +} + +static int +ngbe_get_regs(struct rte_eth_dev *dev, + struct rte_dev_reg_info *regs) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t *data = regs->data; + int g_ind = 0; + int count = 0; + const struct reg_info *reg_group; + const struct reg_info **reg_set = ngbe_regs_others; + + if (data == NULL) { + regs->length = ngbe_get_reg_length(dev); + regs->width = sizeof(uint32_t); + return 0; + } + + /* Support only full register dump */ + if (regs->length == 0 || + regs->length == (uint32_t)ngbe_get_reg_length(dev)) { + regs->version = hw->mac.type << 24 | + hw->revision_id << 16 | + hw->device_id; + while ((reg_group = reg_set[g_ind++])) + count += ngbe_read_regs_group(dev, &data[count], + reg_group); + return 0; + } + + return -ENOTSUP; +} + +static int +ngbe_get_eeprom_length(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + + /* Return unit is byte count */ + return hw->rom.word_size * 2; +} + +static int +ngbe_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *in_eeprom) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_rom_info *eeprom = &hw->rom; + uint16_t *data = in_eeprom->data; + int first, length; + + first = in_eeprom->offset >> 1; + length = in_eeprom->length >> 1; + if (first > hw->rom.word_size || + ((first + length) > hw->rom.word_size)) + return -EINVAL; + + in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); + + return eeprom->readw_buffer(hw, first, length, data); +} + +static int +ngbe_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *in_eeprom) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_rom_info *eeprom = &hw->rom; + uint16_t *data = in_eeprom->data; + int first, length; + + first = in_eeprom->offset >> 1; + length = in_eeprom->length >> 1; + if (first > hw->rom.word_size || + ((first + length) > hw->rom.word_size)) + return -EINVAL; + + in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); + + return eeprom->writew_buffer(hw, first, length, data); +} + static const struct eth_dev_ops ngbe_eth_dev_ops = { .dev_configure = ngbe_dev_configure, .dev_infos_get = ngbe_dev_info_get, @@ -2240,6 +3056,7 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = { .xstats_reset = ngbe_dev_xstats_reset, .xstats_get_names = ngbe_dev_xstats_get_names, .xstats_get_names_by_id = ngbe_dev_xstats_get_names_by_id, + .fw_version_get = ngbe_fw_version_get, .dev_supported_ptypes_get = ngbe_dev_supported_ptypes_get, .mtu_set = ngbe_dev_mtu_set, .vlan_filter_set = ngbe_vlan_filter_set, @@ -2254,8 +3071,35 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = { .rx_queue_release = ngbe_dev_rx_queue_release, .tx_queue_setup = ngbe_dev_tx_queue_setup, .tx_queue_release = ngbe_dev_tx_queue_release, + .dev_led_on = ngbe_dev_led_on, + .dev_led_off = ngbe_dev_led_off, + .flow_ctrl_get = ngbe_flow_ctrl_get, + .flow_ctrl_set = ngbe_flow_ctrl_set, + .mac_addr_add = ngbe_add_rar, + .mac_addr_remove = ngbe_remove_rar, + .mac_addr_set = ngbe_set_default_mac_addr, + .uc_hash_table_set = ngbe_uc_hash_table_set, + .uc_all_hash_table_set = ngbe_uc_all_hash_table_set, + .reta_update = ngbe_dev_rss_reta_update, + .reta_query = ngbe_dev_rss_reta_query, + .rss_hash_update = ngbe_dev_rss_hash_update, + .rss_hash_conf_get = ngbe_dev_rss_hash_conf_get, + .set_mc_addr_list = ngbe_dev_set_mc_addr_list, + .rxq_info_get = ngbe_rxq_info_get, + .txq_info_get = ngbe_txq_info_get, .rx_burst_mode_get = ngbe_rx_burst_mode_get, .tx_burst_mode_get = ngbe_tx_burst_mode_get, + .timesync_enable = ngbe_timesync_enable, + .timesync_disable = ngbe_timesync_disable, + .timesync_read_rx_timestamp = ngbe_timesync_read_rx_timestamp, + .timesync_read_tx_timestamp = ngbe_timesync_read_tx_timestamp, + .get_reg = ngbe_get_regs, + .get_eeprom_length = ngbe_get_eeprom_length, + .get_eeprom = ngbe_get_eeprom, + .set_eeprom = ngbe_set_eeprom, + .timesync_adjust_time = ngbe_timesync_adjust_time, + .timesync_read_time = ngbe_timesync_read_time, + .timesync_write_time = ngbe_timesync_write_time, }; RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);