X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_ethdev.c;h=b84128fefb5a2752d0c722e3b67451fc53fbef1a;hb=be14720def9c1104229cfff13968cf73e146fc1f;hp=b018b25b7fe53347d5c1511a34c3bc7a6ee4777b;hpb=ee1e81266e87a38f711bb47bcc3c4b390647c9e5;p=dpdk.git

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index b018b25b7f..b84128fefb 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -3,7 +3,6 @@
  */
 
 #include <inttypes.h>
-#include <math.h>
 
 #include <rte_ethdev_pci.h>
 #include <rte_io.h>
@@ -63,6 +62,7 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
 		req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
 		req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
 	}
+	req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
 
 	rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
 	if (rc)
@@ -267,26 +267,31 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
 	aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
 	aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
 
-	/* TX pause frames enable flowctrl on RX side */
-	if (dev->fc_info.tx_pause) {
-		/* Single bpid is allocated for all rx channels for now */
-		aq->cq.bpid = dev->fc_info.bpid[0];
-		aq->cq.bp = NIX_CQ_BP_LEVEL;
-		aq->cq.bp_ena = 1;
-	}
-
 	/* Many to one reduction */
 	aq->cq.qint_idx = qid % dev->qints;
 	/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
 	aq->cq.cint_idx = qid;
 
 	if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
+		const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
 		uint16_t min_rx_drop;
-		const float rx_cq_skid = 1024 * 256;
 
 		min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
 		aq->cq.drop = min_rx_drop;
 		aq->cq.drop_ena = 1;
+		rxq->cq_drop = min_rx_drop;
+	} else {
+		rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
+		aq->cq.drop = rxq->cq_drop;
+		aq->cq.drop_ena = 1;
+	}
+
+	/* TX pause frames enable flowctrl on RX side */
+	if (dev->fc_info.tx_pause) {
+		/* Single bpid is allocated for all rx channels for now */
+		aq->cq.bpid = dev->fc_info.bpid[0];
+		aq->cq.bp = rxq->cq_drop;
+		aq->cq.bp_ena = 1;
 	}
 
 	rc = otx2_mbox_process(mbox);
@@ -325,8 +330,7 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
 	/* Many to one reduction */
 	aq->rq.qint_idx = qid % dev->qints;
 
-	if (otx2_ethdev_fixup_is_limit_cq_full(dev))
-		aq->rq.xqe_drop_ena = 1;
+	aq->rq.xqe_drop_ena = 1;
 
 	rc = otx2_mbox_process(mbox);
 	if (rc) {
@@ -521,6 +525,20 @@ otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
 
 	eth_dev->data->rx_queues[rq] = rxq;
 	eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
+
+	/* Calculating delta and freq mult between PTP HI clock and tsc.
+	 * These are needed in deriving raw clock value from tsc counter.
+	 * read_clock eth op returns raw clock value.
+	 */
+	if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
+	    otx2_ethdev_is_ptp_en(dev)) {
+		rc = otx2_nix_raw_clock_tsc_conv(dev);
+		if (rc) {
+			otx2_err("Failed to calculate delta and freq mult");
+			goto fail;
+		}
+	}
+
 	return 0;
 
 free_rxq:
@@ -736,7 +754,8 @@ nix_sq_uninit(struct otx2_eth_txq *txq)
 	while (count) {
 		void *next_sqb;
 
-		next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
+		next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
+				      ((sqes_per_sqb - 1) *
 				      nix_sq_max_sqe_sz(txq)));
 		npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
 				    (uint64_t)sqb_buf);
@@ -797,7 +816,7 @@ nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
 
 	nb_sqb_bufs = nb_desc / sqes_per_sqb;
 	/* Clamp up to devarg passed SQB count */
-	nb_sqb_bufs =  RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
+	nb_sqb_bufs =  RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
 			      nb_sqb_bufs + NIX_SQB_LIST_SPACE));
 
 	txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
@@ -874,8 +893,6 @@ otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
 			send_mem = (struct nix_send_mem_s *)(txq->cmd +
 						(send_hdr->w0.sizem1 << 1));
 			send_mem->subdc = NIX_SUBDC_MEM;
-			send_mem->dsz = 0x0;
-			send_mem->wmem = 0x1;
 			send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
 			send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
 		}
@@ -1651,6 +1668,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
 	.vlan_pvid_set		  = otx2_nix_vlan_pvid_set,
 	.rx_queue_intr_enable	  = otx2_nix_rx_queue_intr_enable,
 	.rx_queue_intr_disable	  = otx2_nix_rx_queue_intr_disable,
+	.read_clock		  = otx2_nix_read_clock,
 };
 
 static inline int
@@ -1814,7 +1832,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 	dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
 	dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
 
-	if (otx2_dev_is_Ax(dev)) {
+	if (otx2_dev_is_96xx_A0(dev) ||
+	    otx2_dev_is_95xx_Ax(dev)) {
 		dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
 		dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
 	}