X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_ethdev.c;h=e18435d494bc06409aaa0c718fd40642e0a742fa;hb=75a675d6d2842a2d47c03a55c50e8f7058902658;hp=4a60f9f7421a68e298769c8bb866c8b9aebf9ba0;hpb=e404f39ca9aff7df0373584d58068d5e39872e0c;p=dpdk.git

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index 4a60f9f742..e18435d494 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -12,13 +12,15 @@
 #include <rte_mempool.h>
 
 #include "otx2_ethdev.h"
+#include "otx2_ethdev_sec.h"
 
 static inline uint64_t
 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
 {
 	uint64_t capa = NIX_RX_OFFLOAD_CAPA;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf(dev) ||
+	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
 		capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
 
 	return capa;
@@ -69,6 +71,8 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
 		req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
 	}
 	req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
+	if (dev->rss_tag_as_xor == 0)
+		req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
 
 	rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
 	if (rc)
@@ -86,10 +90,39 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
 	dev->cints = rsp->cints;
 	dev->qints = rsp->qints;
 	dev->npc_flow.channel = dev->rx_chan_base;
+	dev->ptp_en = rsp->hw_rx_tstamp_en;
 
 	return 0;
 }
 
+static int
+nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
+{
+	struct otx2_mbox *mbox = dev->mbox;
+	struct npc_set_pkind *req;
+	struct msg_resp *rsp;
+	int rc;
+
+	if (dev->npc_flow.switch_header_type == 0)
+		return 0;
+
+	/* Notify AF about higig2 config */
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	if (enable == 0)
+		req->mode = OTX2_PRIV_FLAGS_DEFAULT;
+	req->dir = PKIND_RX;
+	rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	if (enable == 0)
+		req->mode = OTX2_PRIV_FLAGS_DEFAULT;
+	req->dir = PKIND_TX;
+	return otx2_mbox_process_msg(mbox, (void *)&rsp);
+}
+
 static int
 nix_lf_free(struct otx2_eth_dev *dev)
 {
@@ -120,7 +153,7 @@ otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
 {
 	struct otx2_mbox *mbox = dev->mbox;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf_or_sdp(dev))
 		return 0;
 
 	otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
@@ -133,7 +166,7 @@ otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
 {
 	struct otx2_mbox *mbox = dev->mbox;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf_or_sdp(dev))
 		return 0;
 
 	otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
@@ -166,7 +199,7 @@ nix_cgx_start_link_event(struct otx2_eth_dev *dev)
 {
 	struct otx2_mbox *mbox = dev->mbox;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf_or_sdp(dev))
 		return 0;
 
 	otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
@@ -179,8 +212,8 @@ cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
 {
 	struct otx2_mbox *mbox = dev->mbox;
 
-	if (otx2_dev_is_vf(dev))
-		return 0;
+	if (en && otx2_dev_is_vf_or_sdp(dev))
+		return -ENOTSUP;
 
 	if (en)
 		otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
@@ -195,7 +228,7 @@ nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
 {
 	struct otx2_mbox *mbox = dev->mbox;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf_or_sdp(dev))
 		return 0;
 
 	otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
@@ -312,6 +345,10 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
 	aq->op = NIX_AQ_INSTOP_INIT;
 
 	aq->rq.sso_ena = 0;
+
+	if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
+		aq->rq.ipsech_ena = 1;
+
 	aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
 	aq->rq.spb_ena = 0;
 	aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
@@ -575,7 +612,8 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	struct rte_eth_rxmode *rxmode = &conf->rxmode;
 	uint16_t flags = 0;
 
-	if (rxmode->mq_mode == ETH_MQ_RX_RSS)
+	if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
+			(dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
 		flags |= NIX_RX_OFFLOAD_RSS_F;
 
 	if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
@@ -596,6 +634,12 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
 		flags |= NIX_RX_OFFLOAD_TSTAMP_F;
 
+	if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
+		flags |= NIX_RX_OFFLOAD_SECURITY_F;
+
+	if (!dev->ptype_disable)
+		flags |= NIX_RX_OFFLOAD_PTYPE_F;
+
 	return flags;
 }
 
@@ -662,6 +706,9 @@ nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
 			  NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
 			  NIX_TX_OFFLOAD_L3_L4_CSUM_F);
 
+	if (conf & DEV_TX_OFFLOAD_SECURITY)
+		flags |= NIX_TX_OFFLOAD_SECURITY_F;
+
 	if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
 		flags |= NIX_TX_OFFLOAD_TSTAMP_F;
 
@@ -1581,8 +1628,10 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 
 	/* Free the resources allocated from the previous configure */
 	if (dev->configured == 1) {
+		otx2_eth_sec_fini(eth_dev);
 		otx2_nix_rxchan_bpid_cfg(eth_dev, false);
 		otx2_nix_vlan_fini(eth_dev);
+		otx2_nix_mc_addr_list_uninstall(eth_dev);
 		otx2_flow_free_all_resources(dev);
 		oxt2_nix_unregister_queue_irqs(eth_dev);
 		if (eth_dev->data->dev_conf.intr_conf.rxq)
@@ -1611,6 +1660,18 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}
 
+	if (dev->ptp_en &&
+	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+		otx2_err("Both PTP and switch header enabled");
+		goto free_nix_lf;
+	}
+
+	rc = nix_lf_switch_header_type_enable(dev, true);
+	if (rc) {
+		otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
+		goto free_nix_lf;
+	}
+
 	rc = nix_setup_lso_formats(dev);
 	if (rc) {
 		otx2_err("failed to setup nix lso format fields, rc=%d", rc);
@@ -1669,13 +1730,24 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 	rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
 	if (rc) {
 		otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
-		goto q_irq_fini;
+		goto cq_fini;
 	}
 
 	rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
 	if (rc) {
 		otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
-		goto q_irq_fini;
+		goto cq_fini;
+	}
+
+	/* Enable security */
+	rc = otx2_eth_sec_init(eth_dev);
+	if (rc)
+		goto cq_fini;
+
+	rc = otx2_nix_mc_addr_list_install(eth_dev);
+	if (rc < 0) {
+		otx2_err("Failed to install mc address list rc=%d", rc);
+		goto sec_fini;
 	}
 
 	/*
@@ -1685,7 +1757,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 	if (dev->configured == 1) {
 		rc = nix_restore_queue_cfg(eth_dev);
 		if (rc)
-			goto cq_fini;
+			goto uninstall_mc_list;
 	}
 
 	/* Update the mac address */
@@ -1709,6 +1781,10 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 	dev->configured_nb_tx_qs = data->nb_tx_queues;
 	return 0;
 
+uninstall_mc_list:
+	otx2_nix_mc_addr_list_uninstall(eth_dev);
+sec_fini:
+	otx2_eth_sec_fini(eth_dev);
 cq_fini:
 	oxt2_nix_unregister_cq_irqs(eth_dev);
 q_irq_fini:
@@ -1831,6 +1907,7 @@ otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
 	struct otx2_eth_rxq *rxq;
 	int count, i, j, rc;
 
+	nix_lf_switch_header_type_enable(dev, false);
 	nix_cgx_stop_link_event(dev);
 	npc_rx_disable(dev);
 
@@ -1860,7 +1937,11 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
 	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
 	int rc, i;
 
-	if (eth_dev->data->nb_rx_queues != 0) {
+	/* MTU recalculate should be avoided here if PTP is enabled by PF, as
+	 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
+	 * call below.
+	 */
+	if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
 		rc = otx2_nix_recalc_mtu(eth_dev);
 		if (rc)
 			return rc;
@@ -1896,6 +1977,12 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
 	else
 		otx2_nix_timesync_disable(eth_dev);
 
+	/* Update VF about data off shifted by 8 bytes if PTP already
+	 * enabled in PF owning this VF
+	 */
+	if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
+		otx2_nix_ptp_enable_vf(eth_dev);
+
 	rc = npc_rx_enable(dev);
 	if (rc) {
 		otx2_err("Failed to enable NPC rx %d", rc);
@@ -1944,6 +2031,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
 	.dev_set_link_up          = otx2_nix_dev_set_link_up,
 	.dev_set_link_down        = otx2_nix_dev_set_link_down,
 	.dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
+	.dev_ptypes_set           = otx2_nix_ptypes_set,
 	.dev_reset                = otx2_nix_dev_reset,
 	.stats_get                = otx2_nix_dev_stats_get,
 	.stats_reset              = otx2_nix_dev_stats_reset,
@@ -1952,6 +2040,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
 	.mac_addr_add             = otx2_nix_mac_addr_add,
 	.mac_addr_remove          = otx2_nix_mac_addr_del,
 	.mac_addr_set             = otx2_nix_mac_addr_set,
+	.set_mc_addr_list         = otx2_nix_set_mc_addr_list,
 	.promiscuous_enable       = otx2_nix_promisc_enable,
 	.promiscuous_disable      = otx2_nix_promisc_disable,
 	.allmulticast_enable      = otx2_nix_allmulticast_enable,
@@ -1968,6 +2057,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
 	.xstats_get_names_by_id   = otx2_nix_xstats_get_names_by_id,
 	.rxq_info_get             = otx2_nix_rxq_info_get,
 	.txq_info_get             = otx2_nix_txq_info_get,
+	.rx_burst_mode_get        = otx2_rx_burst_mode_get,
+	.tx_burst_mode_get        = otx2_tx_burst_mode_get,
 	.rx_queue_count           = otx2_nix_rx_queue_count,
 	.rx_descriptor_done       = otx2_nix_rx_descriptor_done,
 	.rx_descriptor_status     = otx2_nix_rx_descriptor_status,
@@ -2046,6 +2137,15 @@ otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
 	return otx2_mbox_process(mbox);
 }
 
+static bool
+otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
+{
+	if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
+	    pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+		return true;
+	return false;
+}
+
 static int
 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 {
@@ -2089,6 +2189,10 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 			goto error;
 		}
 	}
+	if (otx2_eth_dev_is_sdp(pci_dev))
+		dev->sdp_link = true;
+	else
+		dev->sdp_link = false;
 	/* Device generic callbacks */
 	dev->ops = &otx2_dev_ops;
 	dev->eth_dev = eth_dev;
@@ -2100,6 +2204,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 
 	dev->configured = 0;
 	dev->drv_inited = true;
+	dev->ptype_disable = 0;
 	dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
 	dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
 
@@ -2164,10 +2269,19 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 		dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
 	}
 
+	/* Create security ctx */
+	rc = otx2_eth_sec_ctx_create(eth_dev);
+	if (rc)
+		goto free_mac_addrs;
+	dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
+	dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
+
 	/* Initialize rte-flow */
 	rc = otx2_flow_init(dev);
 	if (rc)
-		goto free_mac_addrs;
+		goto sec_ctx_destroy;
+
+	otx2_nix_mc_filter_init(dev);
 
 	otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
 		     " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
@@ -2176,6 +2290,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 		     dev->rx_offload_capa, dev->tx_offload_capa);
 	return 0;
 
+sec_ctx_destroy:
+	otx2_eth_sec_ctx_destroy(eth_dev);
 free_mac_addrs:
 	rte_free(eth_dev->data->mac_addrs);
 unregister_irq:
@@ -2216,6 +2332,9 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
 	/* Disable other rte_flow entries */
 	otx2_flow_fini(dev);
 
+	/* Free multicast filter list */
+	otx2_nix_mc_filter_fini(dev);
+
 	/* Disable PTP if already enabled */
 	if (otx2_ethdev_is_ptp_en(dev))
 		otx2_nix_timesync_disable(eth_dev);
@@ -2256,6 +2375,12 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
 	if (rc)
 		otx2_err("Failed to cleanup npa lf, rc=%d", rc);
 
+	/* Disable security */
+	otx2_eth_sec_fini(eth_dev);
+
+	/* Destroy security ctx */
+	otx2_eth_sec_ctx_destroy(eth_dev);
+
 	rte_free(eth_dev->data->mac_addrs);
 	eth_dev->data->mac_addrs = NULL;
 	dev->drv_inited = false;
@@ -2371,6 +2496,14 @@ static const struct rte_pci_id pci_nix_map[] = {
 		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
 			       PCI_DEVID_OCTEONTX2_RVU_AF_VF)
 	},
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+			       PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
+	},
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+			       PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+	},
 	{
 		.vendor_id = 0,
 	},