X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_ethdev_irq.c;h=b121488faf1ee97d61f179f293ca31049fb8c2ee;hb=8c9f976f05bb73e2353741137ff4def526b47cb2;hp=9006e5c8bb94c4e340ef6c70ce41ab156313460d;hpb=3398e9baf09a1268a9adec1de16e563e5558f5cb;p=dpdk.git

diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c
index 9006e5c8bb..b121488faf 100644
--- a/drivers/net/octeontx2/otx2_ethdev_irq.c
+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c
@@ -41,11 +41,11 @@ nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
 	/* Enable all dev interrupt except for RQ_DISABLED */
-	otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	otx2_nix_err_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -61,7 +61,7 @@ nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+	otx2_nix_err_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
 }
 
@@ -97,11 +97,11 @@ nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	/* Set used interrupt vectors */
 	rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 	/* Enable dev interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	otx2_nix_ras_intr_enb_dis(eth_dev, true);
 
 	return rc;
 }
@@ -117,7 +117,7 @@ nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
 	vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
 
 	/* Clear err interrupt */
-	otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+	otx2_nix_ras_intr_enb_dis(eth_dev, false);
 	otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
 }
 
@@ -138,7 +138,7 @@ nix_lf_q_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t q,
 
 	qint = reg & 0xff;
 	wdata &= mask;
-	otx2_write64(wdata, dev->base + off);
+	otx2_write64(wdata | qint, dev->base + off);
 
 	return qint;
 }
@@ -466,3 +466,29 @@ otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
 
 	return 0;
 }
+
+void
+otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	/* Enable all nix lf error interrupts except
+	 * RQ_DISABLED and CQ_DISABLED.
+	 */
+	if (enb)
+		otx2_write64(~(BIT_ULL(11) | BIT_ULL(24)),
+			     dev->base + NIX_LF_ERR_INT_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+}
+
+void
+otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+	if (enb)
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+	else
+		otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+}