X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_ethdev_ops.c;h=5a4501208e9e33feb79c681246a30c63ea344c24;hb=c2a42d19d967e24223f06f2fc797eaed8e17c345;hp=26eef6bd2a00cce488d5fb7f43fb09a067e9c4da;hpb=ca041cd44fcc8b22c0e84460254596096e8fe914;p=dpdk.git diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c index 26eef6bd2a..5a4501208e 100644 --- a/drivers/net/octeontx2/otx2_ethdev_ops.c +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c @@ -2,6 +2,7 @@ * Copyright(C) 2019 Marvell International Ltd. */ +#include #include #include "otx2_ethdev.h" @@ -16,6 +17,8 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) struct nix_frs_cfg *req; int rc; + frame_size += NIX_TIMESYNC_RX_OFFSET * otx2_ethdev_is_ptp_en(dev); + /* Check if MTU is within the allowed range */ if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS) return -EINVAL; @@ -36,6 +39,8 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox); req->update_smq = true; + if (otx2_dev_is_sdp(dev)) + req->sdp_link = true; /* FRS HW config should exclude FCS but include NPC VTAG insert size */ req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE; @@ -46,12 +51,14 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) /* Now just update Rx MAXLEN */ req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox); req->maxlen = frame_size - RTE_ETHER_CRC_LEN; + if (otx2_dev_is_sdp(dev)) + req->sdp_link = true; rc = otx2_mbox_process(mbox); if (rc) return rc; - if (frame_size > RTE_ETHER_MAX_LEN) + if (frame_size > NIX_L2_MAX_LEN) dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; else dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; @@ -65,22 +72,15 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev) { - struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); struct rte_eth_dev_data *data = eth_dev->data; - struct rte_pktmbuf_pool_private *mbp_priv; struct otx2_eth_rxq *rxq; - uint32_t buffsz; uint16_t mtu; int rc; - /* Get rx buffer size */ rxq = data->rx_queues[0]; - mbp_priv = rte_mempool_get_priv(rxq->pool); - buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; /* Setup scatter mode if needed by jumbo */ - if (data->dev_conf.rxmode.max_rx_pkt_len > buffsz) - dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER; + otx2_nix_enable_mseg_on_jumbo(rxq); /* Setup MTU based on max_rx_pkt_len */ mtu = data->dev_conf.rxmode.max_rx_pkt_len - NIX_L2_OVERHEAD; @@ -98,7 +98,7 @@ nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en) struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); struct otx2_mbox *mbox = dev->mbox; - if (otx2_dev_is_vf(dev)) + if (otx2_dev_is_vf_or_sdp(dev)) return; if (en) @@ -141,8 +141,10 @@ otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev) int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev) { - otx2_nix_promisc_config(eth_dev, 0); + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + otx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable); nix_cgx_promisc_config(eth_dev, 0); + dev->dmac_filter_enable = false; return 0; } @@ -221,6 +223,104 @@ otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, qinfo->conf.tx_deferred_start = 0; } +int +otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev, + __rte_unused uint16_t queue_id, + struct rte_eth_burst_mode *mode) +{ + ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + const struct burst_info { + uint16_t flags; + const char *output; + } rx_offload_map[] = { + {NIX_RX_OFFLOAD_RSS_F, "RSS,"}, + {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"}, + {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"}, + {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"}, + {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"}, + {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"}, + {NIX_RX_MULTI_SEG_F, " Scattered,"} + }; + static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:", + "Scalar, Rx Offloads:" + }; + uint32_t i; + + /* Update burst mode info */ + rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], + str_size - bytes); + if (rc < 0) + goto done; + + bytes += rc; + + /* Update Rx offload info */ + for (i = 0; i < RTE_DIM(rx_offload_map); i++) { + if (dev->rx_offload_flags & rx_offload_map[i].flags) { + rc = rte_strscpy(mode->info + bytes, + rx_offload_map[i].output, + str_size - bytes); + if (rc < 0) + goto done; + + bytes += rc; + } + } + +done: + return 0; +} + +int +otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev, + __rte_unused uint16_t queue_id, + struct rte_eth_burst_mode *mode) +{ + ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + const struct burst_info { + uint16_t flags; + const char *output; + } tx_offload_map[] = { + {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"}, + {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"}, + {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"}, + {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"}, + {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"}, + {NIX_TX_OFFLOAD_TSO_F, " TSO,"}, + {NIX_TX_MULTI_SEG_F, " Scattered,"} + }; + static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:", + "Scalar, Tx Offloads:" + }; + uint32_t i; + + /* Update burst mode info */ + rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], + str_size - bytes); + if (rc < 0) + goto done; + + bytes += rc; + + /* Update Tx offload info */ + for (i = 0; i < RTE_DIM(tx_offload_map); i++) { + if (dev->tx_offload_flags & tx_offload_map[i].flags) { + rc = rte_strscpy(mode->info + bytes, + tx_offload_map[i].output, + str_size - bytes); + if (rc < 0) + goto done; + + bytes += rc; + } + } + +done: + return 0; +} + static void nix_rx_head_tail_get(struct otx2_eth_dev *dev, uint32_t *head, uint32_t *tail, uint16_t queue_idx) @@ -282,7 +382,7 @@ otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset) struct otx2_eth_rxq *rxq = rx_queue; uint32_t head, tail; - if (rxq->qlen >= offset) + if (rxq->qlen <= offset) return -EINVAL; nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev), @@ -294,6 +394,42 @@ otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset) return RTE_ETH_RX_DESC_AVAIL; } +static void +nix_tx_head_tail_get(struct otx2_eth_dev *dev, + uint32_t *head, uint32_t *tail, uint16_t queue_idx) +{ + uint64_t reg, val; + + if (head == NULL || tail == NULL) + return; + + reg = (((uint64_t)queue_idx) << 32); + val = otx2_atomic64_add_nosync(reg, (int64_t *) + (dev->base + NIX_LF_SQ_OP_STATUS)); + if (val & OP_ERR) + val = 0; + + *tail = (uint32_t)((val >> 28) & 0x3F); + *head = (uint32_t)((val >> 20) & 0x3F); +} + +int +otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + struct otx2_eth_txq *txq = tx_queue; + uint32_t head, tail; + + if (txq->qconf.nb_desc <= offset) + return -EINVAL; + + nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq); + + if (nix_offset_has_packet(head, tail, offset)) + return RTE_ETH_TX_DESC_DONE; + else + return RTE_ETH_TX_DESC_FULL; +} + /* It is a NOP for octeontx2 as HW frees the buffer on xmit */ int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt) @@ -317,7 +453,7 @@ otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc); rc += 1; /* Add the size of '\0' */ - if (fw_size < (uint32_t)rc) + if (fw_size < (size_t)rc) return rc; return 0; @@ -335,24 +471,11 @@ otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool) } int -otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, void *arg) +otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused, + const struct rte_flow_ops **ops) { - RTE_SET_USED(eth_dev); - - if (filter_type != RTE_ETH_FILTER_GENERIC) { - otx2_err("Unsupported filter type %d", filter_type); - return -ENOTSUP; - } - - if (filter_op == RTE_ETH_FILTER_GET) { - *(const void **)arg = &otx2_flow_ops; - return 0; - } - - otx2_err("Invalid filter_op %d", filter_op); - return -EINVAL; + *ops = &otx2_flow_ops; + return 0; } static struct cgx_fw_data * @@ -397,8 +520,7 @@ otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); struct cgx_fw_data *rsp; - if (!info->data || !info->length || - (info->offset + info->length > SFP_EEPROM_SIZE)) + if (info->offset + info->length > SFP_EEPROM_SIZE) return -EINVAL; rsp = nix_get_fwdata(dev); @@ -469,9 +591,17 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) /* Auto negotiation disabled */ devinfo->speed_capa = ETH_LINK_SPEED_FIXED; - devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | - ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G | - ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G; + if (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) { + devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | + ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G; + + /* 50G and 100G to be supported for board version C0 + * and above. + */ + if (!otx2_dev_is_Ax(dev)) + devinfo->speed_capa |= ETH_LINK_SPEED_50G | + ETH_LINK_SPEED_100G; + } devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;