X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_flow.c;h=6df0732189eb9ffc60681e2d1cef66b1a535c09a;hb=c2a42d19d967e24223f06f2fc797eaed8e17c345;hp=24bde623d193b88363f7d15532eb985770d0a586;hpb=e4a635a65415e22d853233930a4706a684385b3d;p=dpdk.git diff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c index 24bde623d1..6df0732189 100644 --- a/drivers/net/octeontx2/otx2_flow.c +++ b/drivers/net/octeontx2/otx2_flow.c @@ -3,8 +3,11 @@ */ #include "otx2_ethdev.h" +#include "otx2_ethdev_sec.h" #include "otx2_flow.h" +enum flow_vtag_cfg_dir { VTAG_TX, VTAG_RX }; + int otx2_flow_free_all_resources(struct otx2_eth_dev *hw) { @@ -269,6 +272,8 @@ flow_program_rss_action(struct rte_eth_dev *eth_dev, if (rc) return rc; + flow->npc_action &= (~(0xfULL)); + flow->npc_action |= NIX_RX_ACTIONOP_RSS; flow->npc_action |= ((uint64_t)(alg_idx & NIX_RSS_ACT_ALG_MASK) << NIX_RSS_ACT_ALG_OFFSET) | @@ -299,6 +304,21 @@ flow_free_rss_action(struct rte_eth_dev *eth_dev, return 0; } +static int +flow_update_sec_tt(struct rte_eth_dev *eth_dev, + const struct rte_flow_action actions[]) +{ + int rc = 0; + + for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { + if (actions->type == RTE_FLOW_ACTION_TYPE_SECURITY) { + rc = otx2_eth_sec_update_tag_type(eth_dev); + break; + } + } + + return rc; +} static int flow_parse_meta_items(__rte_unused struct otx2_parse_state *pst) @@ -325,6 +345,7 @@ flow_parse_pattern(struct rte_eth_dev *dev, { flow_parse_stage_func_t parse_stage_funcs[] = { flow_parse_meta_items, + otx2_flow_parse_higig2_hdr, otx2_flow_parse_la, otx2_flow_parse_lb, otx2_flow_parse_lc, @@ -443,6 +464,109 @@ otx2_flow_validate(struct rte_eth_dev *dev, &parse_state); } +static int +flow_program_vtag_action(struct rte_eth_dev *eth_dev, + const struct rte_flow_action actions[], + struct rte_flow *flow) +{ + uint16_t vlan_id = 0, vlan_ethtype = RTE_ETHER_TYPE_VLAN; + struct otx2_eth_dev *dev = eth_dev->data->dev_private; + union { + uint64_t reg; + struct nix_tx_vtag_action_s act; + } tx_vtag_action; + struct otx2_mbox *mbox = dev->mbox; + struct nix_vtag_config *vtag_cfg; + struct nix_vtag_config_rsp *rsp; + bool vlan_insert_action = false; + uint64_t rx_vtag_action = 0; + uint8_t vlan_pcp = 0; + int rc; + + for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { + if (actions->type == RTE_FLOW_ACTION_TYPE_OF_POP_VLAN) { + if (dev->npc_flow.vtag_actions == 1) { + vtag_cfg = + otx2_mbox_alloc_msg_nix_vtag_cfg(mbox); + vtag_cfg->cfg_type = VTAG_RX; + vtag_cfg->rx.strip_vtag = 1; + /* Always capture */ + vtag_cfg->rx.capture_vtag = 1; + vtag_cfg->vtag_size = NIX_VTAGSIZE_T4; + vtag_cfg->rx.vtag_type = 0; + + rc = otx2_mbox_process(mbox); + if (rc) + return rc; + } + + rx_vtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 15); + rx_vtag_action |= (NPC_LID_LB << 8); + rx_vtag_action |= NIX_RX_VTAGACTION_VTAG0_RELPTR; + flow->vtag_action = rx_vtag_action; + } else if (actions->type == + RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) { + const struct rte_flow_action_of_set_vlan_vid *vtag = + (const struct rte_flow_action_of_set_vlan_vid *) + actions->conf; + vlan_id = rte_be_to_cpu_16(vtag->vlan_vid); + if (vlan_id > 0xfff) { + otx2_err("Invalid vlan_id for set vlan action"); + return -EINVAL; + } + vlan_insert_action = true; + } else if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) { + const struct rte_flow_action_of_push_vlan *ethtype = + (const struct rte_flow_action_of_push_vlan *) + actions->conf; + vlan_ethtype = rte_be_to_cpu_16(ethtype->ethertype); + if (vlan_ethtype != RTE_ETHER_TYPE_VLAN && + vlan_ethtype != RTE_ETHER_TYPE_QINQ) { + otx2_err("Invalid ethtype specified for push" + " vlan action"); + return -EINVAL; + } + vlan_insert_action = true; + } else if (actions->type == + RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) { + const struct rte_flow_action_of_set_vlan_pcp *pcp = + (const struct rte_flow_action_of_set_vlan_pcp *) + actions->conf; + vlan_pcp = pcp->vlan_pcp; + if (vlan_pcp > 0x7) { + otx2_err("Invalid PCP value for pcp action"); + return -EINVAL; + } + vlan_insert_action = true; + } + } + + if (vlan_insert_action) { + vtag_cfg = otx2_mbox_alloc_msg_nix_vtag_cfg(mbox); + vtag_cfg->cfg_type = VTAG_TX; + vtag_cfg->vtag_size = NIX_VTAGSIZE_T4; + vtag_cfg->tx.vtag0 = + ((vlan_ethtype << 16) | (vlan_pcp << 13) | vlan_id); + vtag_cfg->tx.cfg_vtag0 = 1; + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + tx_vtag_action.reg = 0; + tx_vtag_action.act.vtag0_def = rsp->vtag0_idx; + if (tx_vtag_action.act.vtag0_def < 0) { + otx2_err("Failed to config TX VTAG action"); + return -EINVAL; + } + tx_vtag_action.act.vtag0_lid = NPC_LID_LA; + tx_vtag_action.act.vtag0_op = NIX_TX_VTAGOP_INSERT; + tx_vtag_action.act.vtag0_relptr = + NIX_TX_VTAGACTION_VTAG0_RELPTR; + flow->vtag_action = tx_vtag_action.reg; + } + return 0; +} + static struct rte_flow * otx2_flow_create(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -472,6 +596,17 @@ otx2_flow_create(struct rte_eth_dev *dev, if (rc != 0) goto err_exit; + rc = flow_program_vtag_action(dev, actions, flow); + if (rc != 0) { + rte_flow_error_set(error, EIO, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Failed to program vlan action"); + goto err_exit; + } + + parse_state.is_vf = otx2_dev_is_vf(hw); + rc = flow_program_npc(&parse_state, mbox, &hw->npc_flow); if (rc != 0) { rte_flow_error_set(error, EIO, @@ -490,6 +625,16 @@ otx2_flow_create(struct rte_eth_dev *dev, goto err_exit; } + if (hw->rx_offloads & DEV_RX_OFFLOAD_SECURITY) { + rc = flow_update_sec_tt(dev, actions); + if (rc != 0) { + rte_flow_error_set(error, EIO, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Failed to update tt with sec act"); + goto err_exit; + } + } list = &hw->npc_flow.flow_list[flow->priority]; /* List in ascending order of mcam entries */ @@ -528,8 +673,21 @@ otx2_flow_destroy(struct rte_eth_dev *dev, return -EINVAL; /* Clear mark offload flag if there are no more mark actions */ - if (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) + if (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) { hw->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F; + otx2_eth_set_rx_function(dev); + } + } + + if (flow->nix_intf == OTX2_INTF_RX && flow->vtag_action) { + npc->vtag_actions--; + if (npc->vtag_actions == 0) { + if (hw->vlan_info.strip_on == 0) { + hw->rx_offload_flags &= + ~NIX_RX_OFFLOAD_VLAN_STRIP_F; + otx2_eth_set_rx_function(dev); + } + } } rc = flow_free_rss_action(dev, flow); @@ -647,6 +805,45 @@ err_exit: return -rte_errno; } +static int +otx2_flow_dev_dump(struct rte_eth_dev *dev, + struct rte_flow *flow, FILE *file, + struct rte_flow_error *error) +{ + struct otx2_eth_dev *hw = dev->data->dev_private; + struct otx2_flow_list *list; + struct rte_flow *flow_iter; + uint32_t max_prio, i; + + if (file == NULL) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Invalid file"); + return -EINVAL; + } + if (flow != NULL) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, + NULL, + "Invalid argument"); + return -EINVAL; + } + + max_prio = hw->npc_flow.flow_max_priority; + + for (i = 0; i < max_prio; i++) { + list = &hw->npc_flow.flow_list[i]; + + /* List in ascending order of mcam entries */ + TAILQ_FOREACH(flow_iter, list, next) { + otx2_flow_dump(file, hw, flow_iter); + } + } + + return 0; +} + const struct rte_flow_ops otx2_flow_ops = { .validate = otx2_flow_validate, .create = otx2_flow_create, @@ -654,4 +851,339 @@ const struct rte_flow_ops otx2_flow_ops = { .flush = otx2_flow_flush, .query = otx2_flow_query, .isolate = otx2_flow_isolate, + .dev_dump = otx2_flow_dev_dump, }; + +static int +flow_supp_key_len(uint32_t supp_mask) +{ + int nib_count = 0; + while (supp_mask) { + nib_count++; + supp_mask &= (supp_mask - 1); + } + return nib_count * 4; +} + +/* Refer HRM register: + * NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG + * and + * NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG + **/ +#define BYTESM1_SHIFT 16 +#define HDR_OFF_SHIFT 8 +static void +flow_update_kex_info(struct npc_xtract_info *xtract_info, + uint64_t val) +{ + xtract_info->len = ((val >> BYTESM1_SHIFT) & 0xf) + 1; + xtract_info->hdr_off = (val >> HDR_OFF_SHIFT) & 0xff; + xtract_info->key_off = val & 0x3f; + xtract_info->enable = ((val >> 7) & 0x1); + xtract_info->flags_enable = ((val >> 6) & 0x1); +} + +static void +flow_process_mkex_cfg(struct otx2_npc_flow_info *npc, + struct npc_get_kex_cfg_rsp *kex_rsp) +{ + volatile uint64_t (*q)[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT] + [NPC_MAX_LD]; + struct npc_xtract_info *x_info = NULL; + int lid, lt, ld, fl, ix; + otx2_dxcfg_t *p; + uint64_t keyw; + uint64_t val; + + npc->keyx_supp_nmask[NPC_MCAM_RX] = + kex_rsp->rx_keyx_cfg & 0x7fffffffULL; + npc->keyx_supp_nmask[NPC_MCAM_TX] = + kex_rsp->tx_keyx_cfg & 0x7fffffffULL; + npc->keyx_len[NPC_MCAM_RX] = + flow_supp_key_len(npc->keyx_supp_nmask[NPC_MCAM_RX]); + npc->keyx_len[NPC_MCAM_TX] = + flow_supp_key_len(npc->keyx_supp_nmask[NPC_MCAM_TX]); + + keyw = (kex_rsp->rx_keyx_cfg >> 32) & 0x7ULL; + npc->keyw[NPC_MCAM_RX] = keyw; + keyw = (kex_rsp->tx_keyx_cfg >> 32) & 0x7ULL; + npc->keyw[NPC_MCAM_TX] = keyw; + + /* Update KEX_LD_FLAG */ + for (ix = 0; ix < NPC_MAX_INTF; ix++) { + for (ld = 0; ld < NPC_MAX_LD; ld++) { + for (fl = 0; fl < NPC_MAX_LFL; fl++) { + x_info = + &npc->prx_fxcfg[ix][ld][fl].xtract[0]; + val = kex_rsp->intf_ld_flags[ix][ld][fl]; + flow_update_kex_info(x_info, val); + } + } + } + + /* Update LID, LT and LDATA cfg */ + p = &npc->prx_dxcfg; + q = (volatile uint64_t (*)[][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]) + (&kex_rsp->intf_lid_lt_ld); + for (ix = 0; ix < NPC_MAX_INTF; ix++) { + for (lid = 0; lid < NPC_MAX_LID; lid++) { + for (lt = 0; lt < NPC_MAX_LT; lt++) { + for (ld = 0; ld < NPC_MAX_LD; ld++) { + x_info = &(*p)[ix][lid][lt].xtract[ld]; + val = (*q)[ix][lid][lt][ld]; + flow_update_kex_info(x_info, val); + } + } + } + } + /* Update LDATA Flags cfg */ + npc->prx_lfcfg[0].i = kex_rsp->kex_ld_flags[0]; + npc->prx_lfcfg[1].i = kex_rsp->kex_ld_flags[1]; +} + +static struct otx2_idev_kex_cfg * +flow_intra_dev_kex_cfg(void) +{ + static const char name[] = "octeontx2_intra_device_kex_conf"; + struct otx2_idev_kex_cfg *idev; + const struct rte_memzone *mz; + + mz = rte_memzone_lookup(name); + if (mz) + return mz->addr; + + /* Request for the first time */ + mz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_kex_cfg), + SOCKET_ID_ANY, 0, OTX2_ALIGN); + if (mz) { + idev = mz->addr; + rte_atomic16_set(&idev->kex_refcnt, 0); + return idev; + } + return NULL; +} + +static int +flow_fetch_kex_cfg(struct otx2_eth_dev *dev) +{ + struct otx2_npc_flow_info *npc = &dev->npc_flow; + struct npc_get_kex_cfg_rsp *kex_rsp; + struct otx2_mbox *mbox = dev->mbox; + char mkex_pfl_name[MKEX_NAME_LEN]; + struct otx2_idev_kex_cfg *idev; + int rc = 0; + + idev = flow_intra_dev_kex_cfg(); + if (!idev) + return -ENOMEM; + + /* Is kex_cfg read by any another driver? */ + if (rte_atomic16_add_return(&idev->kex_refcnt, 1) == 1) { + /* Call mailbox to get key & data size */ + (void)otx2_mbox_alloc_msg_npc_get_kex_cfg(mbox); + otx2_mbox_msg_send(mbox, 0); + rc = otx2_mbox_get_rsp(mbox, 0, (void *)&kex_rsp); + if (rc) { + otx2_err("Failed to fetch NPC keyx config"); + goto done; + } + memcpy(&idev->kex_cfg, kex_rsp, + sizeof(struct npc_get_kex_cfg_rsp)); + } + + otx2_mbox_memcpy(mkex_pfl_name, + idev->kex_cfg.mkex_pfl_name, MKEX_NAME_LEN); + + strlcpy((char *)dev->mkex_pfl_name, + mkex_pfl_name, sizeof(dev->mkex_pfl_name)); + + flow_process_mkex_cfg(npc, &idev->kex_cfg); + +done: + return rc; +} + +#define OTX2_MCAM_TOT_ENTRIES_96XX (4096) +#define OTX2_MCAM_TOT_ENTRIES_98XX (16384) + +static int otx2_mcam_tot_entries(struct otx2_eth_dev *dev) +{ + if (otx2_dev_is_98xx(dev)) + return OTX2_MCAM_TOT_ENTRIES_98XX; + else + return OTX2_MCAM_TOT_ENTRIES_96XX; +} + +int +otx2_flow_init(struct otx2_eth_dev *hw) +{ + uint8_t *mem = NULL, *nix_mem = NULL, *npc_mem = NULL; + struct otx2_npc_flow_info *npc = &hw->npc_flow; + uint32_t bmap_sz, tot_mcam_entries = 0; + int rc = 0, idx; + + rc = flow_fetch_kex_cfg(hw); + if (rc) { + otx2_err("Failed to fetch NPC keyx config from idev"); + return rc; + } + + rte_atomic32_init(&npc->mark_actions); + npc->vtag_actions = 0; + + tot_mcam_entries = otx2_mcam_tot_entries(hw); + npc->mcam_entries = tot_mcam_entries >> npc->keyw[NPC_MCAM_RX]; + /* Free, free_rev, live and live_rev entries */ + bmap_sz = rte_bitmap_get_memory_footprint(npc->mcam_entries); + mem = rte_zmalloc(NULL, 4 * bmap_sz * npc->flow_max_priority, + RTE_CACHE_LINE_SIZE); + if (mem == NULL) { + otx2_err("Bmap alloc failed"); + rc = -ENOMEM; + return rc; + } + + npc->flow_entry_info = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct otx2_mcam_ents_info), + 0); + if (npc->flow_entry_info == NULL) { + otx2_err("flow_entry_info alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->free_entries = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct rte_bitmap *), + 0); + if (npc->free_entries == NULL) { + otx2_err("free_entries alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->free_entries_rev = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct rte_bitmap *), + 0); + if (npc->free_entries_rev == NULL) { + otx2_err("free_entries_rev alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->live_entries = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct rte_bitmap *), + 0); + if (npc->live_entries == NULL) { + otx2_err("live_entries alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->live_entries_rev = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct rte_bitmap *), + 0); + if (npc->live_entries_rev == NULL) { + otx2_err("live_entries_rev alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->flow_list = rte_zmalloc(NULL, npc->flow_max_priority + * sizeof(struct otx2_flow_list), + 0); + if (npc->flow_list == NULL) { + otx2_err("flow_list alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc_mem = mem; + for (idx = 0; idx < npc->flow_max_priority; idx++) { + TAILQ_INIT(&npc->flow_list[idx]); + + npc->free_entries[idx] = + rte_bitmap_init(npc->mcam_entries, mem, bmap_sz); + mem += bmap_sz; + + npc->free_entries_rev[idx] = + rte_bitmap_init(npc->mcam_entries, mem, bmap_sz); + mem += bmap_sz; + + npc->live_entries[idx] = + rte_bitmap_init(npc->mcam_entries, mem, bmap_sz); + mem += bmap_sz; + + npc->live_entries_rev[idx] = + rte_bitmap_init(npc->mcam_entries, mem, bmap_sz); + mem += bmap_sz; + + npc->flow_entry_info[idx].free_ent = 0; + npc->flow_entry_info[idx].live_ent = 0; + npc->flow_entry_info[idx].max_id = 0; + npc->flow_entry_info[idx].min_id = ~(0); + } + + npc->rss_grps = NIX_RSS_GRPS; + + bmap_sz = rte_bitmap_get_memory_footprint(npc->rss_grps); + nix_mem = rte_zmalloc(NULL, bmap_sz, RTE_CACHE_LINE_SIZE); + if (nix_mem == NULL) { + otx2_err("Bmap alloc failed"); + rc = -ENOMEM; + goto err; + } + + npc->rss_grp_entries = rte_bitmap_init(npc->rss_grps, nix_mem, bmap_sz); + + /* Group 0 will be used for RSS, + * 1 -7 will be used for rte_flow RSS action + */ + rte_bitmap_set(npc->rss_grp_entries, 0); + + return 0; + +err: + if (npc->flow_list) + rte_free(npc->flow_list); + if (npc->live_entries_rev) + rte_free(npc->live_entries_rev); + if (npc->live_entries) + rte_free(npc->live_entries); + if (npc->free_entries_rev) + rte_free(npc->free_entries_rev); + if (npc->free_entries) + rte_free(npc->free_entries); + if (npc->flow_entry_info) + rte_free(npc->flow_entry_info); + if (npc_mem) + rte_free(npc_mem); + return rc; +} + +int +otx2_flow_fini(struct otx2_eth_dev *hw) +{ + struct otx2_npc_flow_info *npc = &hw->npc_flow; + int rc; + + rc = otx2_flow_free_all_resources(hw); + if (rc) { + otx2_err("Error when deleting NPC MCAM entries, counters"); + return rc; + } + + if (npc->flow_list) + rte_free(npc->flow_list); + if (npc->live_entries_rev) + rte_free(npc->live_entries_rev); + if (npc->live_entries) + rte_free(npc->live_entries); + if (npc->free_entries_rev) + rte_free(npc->free_entries_rev); + if (npc->free_entries) + rte_free(npc->free_entries); + if (npc->flow_entry_info) + rte_free(npc->flow_entry_info); + + return 0; +}