X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Focteontx2%2Fotx2_flow_ctrl.c;h=76bf48100183ec53051683a078f97165b4a4280f;hb=397b4b3c509574a55c58ae161f5a01cc8a4da56a;hp=0392086d8952a3ae44687842eec4e979671521fb;hpb=609945f1ce903b8bb77e709c81df458f30374584;p=dpdk.git

diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c
index 0392086d89..76bf481001 100644
--- a/drivers/net/octeontx2/otx2_flow_ctrl.c
+++ b/drivers/net/octeontx2/otx2_flow_ctrl.c
@@ -14,7 +14,7 @@ otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb)
 	struct nix_bp_cfg_rsp *rsp;
 	int rc;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_sdp(dev))
 		return 0;
 
 	if (enb) {
@@ -53,8 +53,10 @@ otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 	struct otx2_mbox *mbox = dev->mbox;
 	int rc;
 
-	if (otx2_dev_is_vf(dev))
-		return -ENOTSUP;
+	if (otx2_dev_is_lbk(dev)) {
+		fc_conf->mode = RTE_FC_NONE;
+		return 0;
+	}
 
 	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox);
 	req->set = 0;
@@ -110,7 +112,7 @@ otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, bool enb)
 		if (enb) {
 			aq->cq.bpid = fc->bpid[0];
 			aq->cq_mask.bpid = ~(aq->cq_mask.bpid);
-			aq->cq.bp = NIX_CQ_BP_LEVEL;
+			aq->cq.bp = rxq->cq_drop;
 			aq->cq_mask.bp = ~(aq->cq_mask.bp);
 		}
 
@@ -143,8 +145,10 @@ otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 	uint8_t tx_pause, rx_pause;
 	int rc = 0;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_lbk(dev)) {
+		otx2_info("No flow control support for LBK bound ethports");
 		return -ENOTSUP;
+	}
 
 	if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||
 	    fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {
@@ -162,8 +166,8 @@ otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 
 	/* Check if TX pause frame is already enabled or not */
 	if (fc->tx_pause ^ tx_pause) {
-		if (otx2_dev_is_A0(dev) && eth_dev->data->dev_started) {
-			/* on A0, CQ should be in disabled state
+		if (otx2_dev_is_Ax(dev) && eth_dev->data->dev_started) {
+			/* on Ax, CQ should be in disabled state
 			 * while setting flow control configuration.
 			 */
 			otx2_info("Stop the port=%d for setting flow control\n",
@@ -196,19 +200,18 @@ int
 otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)
 {
 	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+	struct otx2_fc_info *fc = &dev->fc_info;
 	struct rte_eth_fc_conf fc_conf;
 
-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev))
 		return 0;
 
 	memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
-	/* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
-	 * by AF driver, update those info in PMD structure.
-	 */
-	otx2_nix_flow_ctrl_get(eth_dev, &fc_conf);
+	fc_conf.mode = fc->mode;
 
-	/* To avoid Link credit deadlock on A0, disable Tx FC if it's enabled */
-	if (otx2_dev_is_A0(dev) &&
+	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+	if (otx2_dev_is_Ax(dev) &&
+	    (dev->npc_flow.switch_header_type != OTX2_PRIV_FLAGS_HIGIG) &&
 	    (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) {
 		fc_conf.mode =
 				(fc_conf.mode == RTE_FC_FULL ||
@@ -218,3 +221,32 @@ otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)
 
 	return otx2_nix_flow_ctrl_set(eth_dev, &fc_conf);
 }
+
+int
+otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev)
+{
+	struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+	struct otx2_fc_info *fc = &dev->fc_info;
+	struct rte_eth_fc_conf fc_conf;
+	int rc;
+
+	if (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev))
+		return 0;
+
+	memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
+	/* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
+	 * by AF driver, update those info in PMD structure.
+	 */
+	rc = otx2_nix_flow_ctrl_get(eth_dev, &fc_conf);
+	if (rc)
+		goto exit;
+
+	fc->mode = fc_conf.mode;
+	fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
+			(fc_conf.mode == RTE_FC_RX_PAUSE);
+	fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
+			(fc_conf.mode == RTE_FC_TX_PAUSE);
+
+exit:
+	return rc;
+}