X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fbcm_osal.c;h=e3a2cb452f1aca45690d06988d5f2348d0eebbf6;hb=cbc12b0a96f5;hp=ae5a8bcec828efdb926f4228adde202e0d951219;hpb=2c577ba41798947c6c869a8faebc54bfbdc4d069;p=dpdk.git diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index ae5a8bcec8..e3a2cb452f 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -6,8 +6,6 @@ * See LICENSE.qede_pmd for copyright and licensing details. */ -#include - #include #include @@ -15,6 +13,13 @@ #include "ecore.h" #include "ecore_hw.h" #include "ecore_iov_api.h" +#include "ecore_mcp_api.h" +#include "ecore_l2_api.h" + +/* Array of memzone pointers */ +static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE]; +/* Counter to track current memzone allocated */ +uint16_t ecore_mz_count; unsigned long qede_log2_align(unsigned long n) { @@ -62,6 +67,27 @@ inline bool qede_test_bit(u32 nr, unsigned long *addr) return res; } +static inline u32 qede_ffb(unsigned long word) +{ + unsigned long first_bit; + + first_bit = __builtin_ffsl(word); + return first_bit ? (first_bit - 1) : OSAL_BITS_PER_UL; +} + +inline u32 qede_find_first_bit(unsigned long *addr, u32 limit) +{ + u32 i; + u32 nwords = 0; + OSAL_BUILD_BUG_ON(!limit); + nwords = (limit - 1) / OSAL_BITS_PER_UL + 1; + for (i = 0; i < nwords; i++) + if (addr[i] != 0) + break; + + return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffb(addr[i]); +} + static inline u32 qede_ffz(unsigned long word) { unsigned long first_zero; @@ -76,9 +102,7 @@ inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit) u32 nwords = 0; OSAL_BUILD_BUG_ON(!limit); nwords = (limit - 1) / OSAL_BITS_PER_UL + 1; - for (i = 0; i < nwords; i++) - if (~(addr[i] != 0)) - break; + for (i = 0; i < nwords && ~(addr[i]) == 0; i++); return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffz(addr[i]); } @@ -98,6 +122,13 @@ void *osal_dma_alloc_coherent(struct ecore_dev *p_dev, uint32_t core_id = rte_lcore_id(); unsigned int socket_id; + if (ecore_mz_count >= RTE_MAX_MEMZONE) { + DP_ERR(p_dev, "Memzone allocation count exceeds %u\n", + RTE_MAX_MEMZONE); + *phys = 0; + return OSAL_NULL; + } + OSAL_MEM_ZERO(mz_name, sizeof(*mz_name)); snprintf(mz_name, sizeof(mz_name) - 1, "%lx", (unsigned long)rte_get_timer_cycles()); @@ -114,9 +145,11 @@ void *osal_dma_alloc_coherent(struct ecore_dev *p_dev, return OSAL_NULL; } *phys = mz->phys_addr; - DP_VERBOSE(p_dev, ECORE_MSG_PROBE, - "size=%zu phys=0x%" PRIx64 " virt=%p on socket=%u\n", - mz->len, mz->phys_addr, mz->addr, socket_id); + ecore_mz_mapping[ecore_mz_count++] = mz; + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Allocated dma memory size=%zu phys=0x%lx" + " virt=%p core=%d\n", + mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id); return mz->addr; } @@ -128,6 +161,13 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev, uint32_t core_id = rte_lcore_id(); unsigned int socket_id; + if (ecore_mz_count >= RTE_MAX_MEMZONE) { + DP_ERR(p_dev, "Memzone allocation count exceeds %u\n", + RTE_MAX_MEMZONE); + *phys = 0; + return OSAL_NULL; + } + OSAL_MEM_ZERO(mz_name, sizeof(*mz_name)); snprintf(mz_name, sizeof(mz_name) - 1, "%lx", (unsigned long)rte_get_timer_cycles()); @@ -143,12 +183,31 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev, return OSAL_NULL; } *phys = mz->phys_addr; - DP_VERBOSE(p_dev, ECORE_MSG_PROBE, - "aligned memory size=%zu phys=0x%" PRIx64 " virt=%p core=%d\n", - mz->len, mz->phys_addr, mz->addr, core_id); + ecore_mz_mapping[ecore_mz_count++] = mz; + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Allocated aligned dma memory size=%zu phys=0x%lx" + " virt=%p core=%d\n", + mz->len, (unsigned long)mz->phys_addr, mz->addr, core_id); return mz->addr; } +void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys) +{ + uint16_t j; + + for (j = 0 ; j < ecore_mz_count; j++) { + if (phys == ecore_mz_mapping[j]->phys_addr) { + DP_VERBOSE(p_dev, ECORE_MSG_SP, + "Free memzone %s\n", ecore_mz_mapping[j]->name); + rte_memzone_free(ecore_mz_mapping[j]); + return; + } + } + + DP_ERR(p_dev, "Unexpected memory free request\n"); +} + +#ifdef CONFIG_ECORE_ZIPPED_FW u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len, u8 *input_buf, u32 max_size, u8 *unzip_buf) { @@ -179,3 +238,69 @@ u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len, return p_hwfn->stream->total_out / 4; } +#endif + +void +qede_get_mcp_proto_stats(struct ecore_dev *edev, + enum ecore_mcp_protocol_type type, + union ecore_mcp_protocol_stats *stats) +{ + struct ecore_eth_stats lan_stats; + + if (type == ECORE_MCP_LAN_STATS) { + ecore_get_vport_stats(edev, &lan_stats); + + /* @DPDK */ + stats->lan_stats.ucast_rx_pkts = lan_stats.common.rx_ucast_pkts; + stats->lan_stats.ucast_tx_pkts = lan_stats.common.tx_ucast_pkts; + + stats->lan_stats.fcs_err = -1; + } else { + DP_INFO(edev, "Statistics request type %d not supported\n", + type); + } +} + +void +qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type) +{ + char err_str[64]; + + switch (err_type) { + case ECORE_HW_ERR_FAN_FAIL: + strcpy(err_str, "Fan Failure"); + break; + case ECORE_HW_ERR_MFW_RESP_FAIL: + strcpy(err_str, "MFW Response Failure"); + break; + case ECORE_HW_ERR_HW_ATTN: + strcpy(err_str, "HW Attention"); + break; + case ECORE_HW_ERR_DMAE_FAIL: + strcpy(err_str, "DMAE Failure"); + break; + case ECORE_HW_ERR_RAMROD_FAIL: + strcpy(err_str, "Ramrod Failure"); + break; + case ECORE_HW_ERR_FW_ASSERT: + strcpy(err_str, "FW Assertion"); + break; + default: + strcpy(err_str, "Unknown"); + } + + DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str); + ecore_int_attn_clr_enable(p_hwfn->p_dev, true); +} + +u32 qede_crc32(u32 crc, u8 *ptr, u32 length) +{ + int i; + + while (length--) { + crc ^= *ptr++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); + } + return crc; +}