X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fbcm_osal.h;h=8b2faec5b6ff1651985d4462f44be3d3313ab852;hb=1e8d75d8059701fd15876416be06064735ec5e87;hp=74e5188216c5c662a8561599939a49c701bc1816;hpb=70f1a93d7b184d27566bb6cfa979a19f72f91e40;p=dpdk.git

diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index 74e5188216..8b2faec5b6 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -1,14 +1,13 @@
-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 #ifndef __BCM_OSAL_H
 #define __BCM_OSAL_H
 
+#include <stdbool.h>
 #include <rte_byteorder.h>
 #include <rte_spinlock.h>
 #include <rte_malloc.h>
@@ -30,7 +29,7 @@ enum ecore_mcp_protocol_type;
 union ecore_mcp_protocol_stats;
 enum ecore_hw_err_type;
 
-void qed_link_update(struct ecore_hwfn *hwfn, struct ecore_ptt *ptt);
+void qed_link_update(struct ecore_hwfn *hwfn);
 
 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 #undef __BIG_ENDIAN
@@ -63,7 +62,7 @@ typedef u32 OSAL_BE32;
 
 #define osal_uintptr_t uintptr_t
 
-typedef phys_addr_t dma_addr_t;
+typedef rte_iova_t dma_addr_t;
 
 typedef rte_spinlock_t osal_spinlock_t;
 
@@ -73,10 +72,6 @@ typedef size_t osal_size_t;
 
 typedef intptr_t osal_int_ptr_t;
 
-typedef int bool;
-#define true 1
-#define false 0
-
 #define nothing do {} while (0)
 
 /* Delays */
@@ -150,8 +145,8 @@ void osal_dma_free_mem(struct ecore_dev *edev, dma_addr_t phys);
 			      ((u8 *)(uintptr_t)(_p_hwfn->doorbells) +	\
 			      (_db_addr)), (u32)_val)
 
-#define DIRECT_REG_WR64(hwfn, addr, value) nothing
-#define DIRECT_REG_RD64(hwfn, addr) 0
+#define DIRECT_REG_RD64(hwfn, addr) rte_read64(addr)
+#define DIRECT_REG_WR64(hwfn, addr, value) rte_write64((value), (addr))
 
 /* Mutexes */
 
@@ -334,11 +329,13 @@ u32 qede_find_first_zero_bit(unsigned long *, u32);
 	qede_find_first_zero_bit(bitmap, length)
 
 #define OSAL_BUILD_BUG_ON(cond)		nothing
-#define ETH_ALEN			ETHER_ADDR_LEN
+#define ETH_ALEN			RTE_ETHER_ADDR_LEN
+#define ETHER_TYPE_VLAN			RTE_ETHER_TYPE_VLAN
+#define ETHER_TYPE_QINQ			RTE_ETHER_TYPE_QINQ
 
 #define OSAL_BITMAP_WEIGHT(bitmap, count) 0
 
-#define OSAL_LINK_UPDATE(hwfn, ptt) qed_link_update(hwfn, ptt)
+#define OSAL_LINK_UPDATE(hwfn) qed_link_update(hwfn)
 #define OSAL_TRANSCEIVER_UPDATE(hwfn) nothing
 #define OSAL_DCBX_AEN(hwfn, mib_type) nothing
 
@@ -429,7 +426,7 @@ u32 qede_osal_log2(u32);
 #define OSAL_PAGE_SIZE 4096
 #define OSAL_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE
 #define OSAL_IOMEM volatile
-#define OSAL_UNUSED    __attribute__((unused))
+#define OSAL_UNUSED    __rte_unused
 #define OSAL_UNLIKELY(x)  __builtin_expect(!!(x), 0)
 #define OSAL_MIN_T(type, __min1, __min2)	\
 	((type)(__min1) < (type)(__min2) ? (type)(__min1) : (type)(__min2))
@@ -449,10 +446,14 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length);
 #define OSAL_CRC8(table, pdata, nbytes, crc) 0
 #define OSAL_MFW_TLV_REQ(p_hwfn) nothing
 #define OSAL_MFW_FILL_TLV_DATA(type, buf, data) (0)
+#define OSAL_HW_INFO_CHANGE(p_hwfn, change) nothing
 #define OSAL_MFW_CMD_PREEMPT(p_hwfn) nothing
 #define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, mask, b_update, tunn) 0
 
 #define OSAL_DIV_S64(a, b)	((a) / (b))
 #define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing
+#define OSAL_GET_EPOCH(p_hwfn)	0
+#define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0)
+#define OSAL_DB_REC_OCCURRED(p_hwfn) nothing
 
 #endif /* __BCM_OSAL_H */