X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fecore.h;h=b2077bc46ecc8f1c5ce0c6d33167f0212bba9482;hb=f97b56f9f12eef610f4274bd5fb1c68b604bbb3b;hp=2d2f6f3182f9597c94d1c031dbf8c153a3871a2b;hpb=cb051eb251e2d71f30819093038843851af90ff3;p=dpdk.git diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index 2d2f6f3182..b2077bc46e 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -1,9 +1,7 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ #ifndef __ECORE_H @@ -21,6 +19,7 @@ #include #endif +#include "ecore_status.h" #include "ecore_hsi_common.h" #include "ecore_hsi_debug_tools.h" #include "ecore_hsi_init_func.h" @@ -29,9 +28,9 @@ #include "mcp_public.h" #define ECORE_MAJOR_VERSION 8 -#define ECORE_MINOR_VERSION 18 -#define ECORE_REVISION_VERSION 7 -#define ECORE_ENGINEERING_VERSION 1 +#define ECORE_MINOR_VERSION 40 +#define ECORE_REVISION_VERSION 26 +#define ECORE_ENGINEERING_VERSION 0 #define ECORE_VERSION \ ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ @@ -41,6 +40,9 @@ ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) +#define IS_ECORE_PACING(p_hwfn) \ + (!!(p_hwfn->b_en_pacing)) + #define MAX_HWFNS_PER_DEVICE 2 #define NAME_SIZE 128 /* @DPDK */ #define ECORE_WFQ_UNIT 100 @@ -50,6 +52,7 @@ #define FCOE_BDQ_ID(_port_id) (_port_id + 2) /* Constants */ #define ECORE_WID_SIZE (1024) +#define ECORE_MIN_WIDS (4) /* Configurable */ #define ECORE_PF_DEMS_SIZE (4) @@ -205,6 +208,7 @@ struct ecore_l2_info; struct ecore_igu_info; struct ecore_mcp_info; struct ecore_dcbx_info; +struct ecore_llh_info; struct ecore_rt_data { u32 *init_val; @@ -351,22 +355,32 @@ enum ecore_hw_err_type { }; #endif +enum ecore_db_rec_exec { + DB_REC_DRY_RUN, + DB_REC_REAL_DEAL, + DB_REC_ONCE, +}; + struct ecore_hw_info { /* PCI personality */ enum ecore_pci_personality personality; -#define ECORE_IS_RDMA_PERSONALITY(dev) \ - ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ +#define ECORE_IS_RDMA_PERSONALITY(dev) \ + ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) -#define ECORE_IS_ROCE_PERSONALITY(dev) \ +#define ECORE_IS_ROCE_PERSONALITY(dev) \ ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) -#define ECORE_IS_IWARP_PERSONALITY(dev) \ +#define ECORE_IS_IWARP_PERSONALITY(dev) \ ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) -#define ECORE_IS_L2_PERSONALITY(dev) \ +#define ECORE_IS_L2_PERSONALITY(dev) \ ((dev)->hw_info.personality == ECORE_PCI_ETH || \ ECORE_IS_RDMA_PERSONALITY(dev)) +#define ECORE_IS_FCOE_PERSONALITY(dev) \ + ((dev)->hw_info.personality == ECORE_PCI_FCOE) +#define ECORE_IS_ISCSI_PERSONALITY(dev) \ + ((dev)->hw_info.personality == ECORE_PCI_ISCSI) /* Resource Allocation scheme results */ u32 resc_start[ECORE_MAX_RESC]; @@ -421,8 +435,10 @@ struct ecore_hw_info { #define DMAE_MAX_RW_SIZE 0x2000 struct ecore_dmae_info { - /* Mutex for synchronizing access to functions */ - osal_mutex_t mutex; + /* Spinlock for synchronizing access to functions */ + osal_spinlock_t lock; + + bool b_mem_ready; u8 channel; @@ -451,6 +467,8 @@ struct ecore_wfq_data { bool configured; }; +#define OFLD_GRP_SIZE 4 + struct ecore_qm_info { struct init_qm_pq_params *qm_pq_params; struct init_qm_vport_params *qm_vport_params; @@ -479,6 +497,12 @@ struct ecore_qm_info { u8 num_pf_rls; }; +struct ecore_db_recovery_info { + osal_list_t list; + osal_spinlock_t lock; + u32 db_recovery_counter; +}; + struct storm_stats { u32 address; u32 len; @@ -491,17 +515,74 @@ struct ecore_fw_data { const u8 *modes_tree_buf; union init_op *init_ops; const u32 *arr_data; + const u32 *fw_overlays; + u32 fw_overlays_len; u32 init_ops_size; }; +enum ecore_mf_mode_bit { + /* Supports PF-classification based on tag */ + ECORE_MF_OVLAN_CLSS, + + /* Supports PF-classification based on MAC */ + ECORE_MF_LLH_MAC_CLSS, + + /* Supports PF-classification based on protocol type */ + ECORE_MF_LLH_PROTO_CLSS, + + /* Requires a default PF to be set */ + ECORE_MF_NEED_DEF_PF, + + /* Allow LL2 to multicast/broadcast */ + ECORE_MF_LL2_NON_UNICAST, + + /* Allow Cross-PF [& child VFs] Tx-switching */ + ECORE_MF_INTER_PF_SWITCH, + + /* TODO - if we ever re-utilize any of this logic, we can rename */ + ECORE_MF_UFP_SPECIFIC, + + ECORE_MF_DISABLE_ARFS, + + /* Use vlan for steering */ + ECORE_MF_8021Q_TAGGING, + + /* Use stag for steering */ + ECORE_MF_8021AD_TAGGING, + + /* Allow FIP discovery fallback */ + ECORE_MF_FIP_SPECIAL, +}; + +enum ecore_ufp_mode { + ECORE_UFP_MODE_ETS, + ECORE_UFP_MODE_VNIC_BW, +}; + +enum ecore_ufp_pri_type { + ECORE_UFP_PRI_OS, + ECORE_UFP_PRI_VNIC +}; + +struct ecore_ufp_info { + enum ecore_ufp_pri_type pri_type; + enum ecore_ufp_mode mode; + u8 tc; +}; + +enum BAR_ID { + BAR_ID_0, /* used for GRC */ + BAR_ID_1 /* Used for doorbells */ +}; + struct ecore_hwfn { struct ecore_dev *p_dev; u8 my_id; /* ID inside the PF */ #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) u8 rel_pf_id; /* Relative to engine*/ u8 abs_pf_id; - #define ECORE_PATH_ID(_p_hwfn) \ - (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) +#define ECORE_PATH_ID(_p_hwfn) \ + (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0) u8 port_id; bool b_active; @@ -515,6 +596,7 @@ struct ecore_hwfn { u8 num_funcs_on_engine; u8 enabled_func_idx; + u8 num_funcs_on_port; /* BAR access */ void OSAL_IOMEM *regview; @@ -575,6 +657,7 @@ struct ecore_hwfn { struct ecore_pf_iov *pf_iov_info; struct ecore_mcp_info *mcp_info; struct ecore_dcbx_info *p_dcbx_info; + struct ecore_ufp_info ufp_info; struct ecore_dmae_info dmae_info; @@ -587,6 +670,7 @@ struct ecore_hwfn { #endif struct dbg_tools_data dbg_info; + void *dbg_user_info; struct z_stream_s *stream; @@ -605,17 +689,28 @@ struct ecore_hwfn { /* L2-related */ struct ecore_l2_info *p_l2_info; + /* Mechanism for recovering from doorbell drop */ + struct ecore_db_recovery_info db_recovery_info; + + /* Enable/disable pacing, if request to enable then + * IOV and mcos configuration will be skipped. + * this actually reflects the value requested in + * struct ecore_hw_prepare_params by ecore client. + */ + bool b_en_pacing; + + struct phys_mem_desc *fw_overlay_mem; + /* @DPDK */ struct ecore_ptt *p_arfs_ptt; }; -#ifndef __EXTRACT__LINUX__ enum ecore_mf_mode { ECORE_MF_DEFAULT, ECORE_MF_OVLAN, ECORE_MF_NPAR, + ECORE_MF_UFP, }; -#endif /* @DPDK */ struct ecore_dbg_feature { @@ -665,58 +760,61 @@ struct ecore_dev { #define ECORE_DEV_ID_MASK_AH 0x8000 u16 chip_num; - #define CHIP_NUM_MASK 0xffff - #define CHIP_NUM_SHIFT 16 +#define CHIP_NUM_MASK 0xffff +#define CHIP_NUM_SHIFT 0 - u16 chip_rev; - #define CHIP_REV_MASK 0xf - #define CHIP_REV_SHIFT 12 + u8 chip_rev; +#define CHIP_REV_MASK 0xf +#define CHIP_REV_SHIFT 0 #ifndef ASIC_ONLY - #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) - #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) - #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) - #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ - CHIP_REV_IS_EMUL_B0(_p_dev)) - #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) - #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) - #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ - CHIP_REV_IS_FPGA_B0(_p_dev)) - #define CHIP_REV_IS_SLOW(_p_dev) \ - (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) - #define CHIP_REV_IS_A0(_p_dev) \ - (CHIP_REV_IS_EMUL_A0(_p_dev) || \ - CHIP_REV_IS_FPGA_A0(_p_dev) || \ - !(_p_dev)->chip_rev) - #define CHIP_REV_IS_B0(_p_dev) \ - (CHIP_REV_IS_EMUL_B0(_p_dev) || \ - CHIP_REV_IS_FPGA_B0(_p_dev) || \ - (_p_dev)->chip_rev == 1) - #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) +#define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) +#define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) +#define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) +#define CHIP_REV_IS_EMUL(_p_dev) \ + (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) +#define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) +#define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) +#define CHIP_REV_IS_FPGA(_p_dev) \ + (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) +#define CHIP_REV_IS_SLOW(_p_dev) \ + (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) +#define CHIP_REV_IS_A0(_p_dev) \ + (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ + (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) +#define CHIP_REV_IS_B0(_p_dev) \ + (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ + ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) +#define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) #else - #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) - #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) +#define CHIP_REV_IS_A0(_p_dev) \ + (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) +#define CHIP_REV_IS_B0(_p_dev) \ + ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) #endif - u16 chip_metal; - #define CHIP_METAL_MASK 0xff - #define CHIP_METAL_SHIFT 4 + u8 chip_metal; +#define CHIP_METAL_MASK 0xff +#define CHIP_METAL_SHIFT 0 - u16 chip_bond_id; - #define CHIP_BOND_ID_MASK 0xf - #define CHIP_BOND_ID_SHIFT 0 + u8 chip_bond_id; +#define CHIP_BOND_ID_MASK 0xff +#define CHIP_BOND_ID_SHIFT 0 u8 num_engines; - u8 num_ports_in_engines; + u8 num_ports; + u8 num_ports_in_engine; u8 num_funcs_in_port; u8 path_id; + + unsigned long mf_bits; enum ecore_mf_mode mf_mode; - #define IS_MF_DEFAULT(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) - #define IS_MF_SI(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) - #define IS_MF_SD(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) +#define IS_MF_DEFAULT(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) +#define IS_MF_SI(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) +#define IS_MF_SD(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) int pcie_width; int pcie_speed; @@ -742,12 +840,31 @@ struct ecore_dev { u8 cache_shift; /* Init */ - const struct iro *iro_arr; - #define IRO (p_hwfn->p_dev->iro_arr) + const u32 *iro_arr; +#define IRO ((const struct iro *)p_hwfn->p_dev->iro_arr) /* HW functions */ u8 num_hwfns; struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; +#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) +#define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1) + + /* Engine affinity */ + u8 l2_affin_hint; + u8 fir_affin; + u8 iwarp_affin; + /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */ +#define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin]) + /* Macro for getting the engine-affinitized hwfn for iWARP */ +#define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin]) + /* Generic macro for getting the engine-affinitized hwfn */ +#define ECORE_AFFIN_HWFN(dev) \ + (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \ + ECORE_IWARP_AFFIN_HWFN(dev) : \ + ECORE_FIR_AFFIN_HWFN(dev)) + /* Macro for getting the index (0/1) of the engine-affinitized hwfn */ +#define ECORE_AFFIN_HWFN_IDX(dev) \ + (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1) /* SRIOV */ struct ecore_hw_sriov_info *p_iov_info; @@ -782,7 +899,14 @@ struct ecore_dev { #ifndef ASIC_ONLY bool b_is_emul_full; + bool b_is_emul_mac; #endif + /* LLH info */ + u8 ppfid_bitmap; + struct ecore_llh_info *p_llh_info; + + /* Indicates whether this PF serves a storage target */ + bool b_is_target; #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */ void *firmware; @@ -794,16 +918,54 @@ struct ecore_dev { u8 engine_for_debug; }; -#define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ - : MAX_NUM_VFS_K2) -#define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ - : MAX_NUM_L2_QUEUES_K2) -#define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ - : MAX_NUM_PORTS_K2) -#define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ - : MAX_SB_PER_PATH_K2) -#define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ - : MAX_NUM_PFS_K2) +enum ecore_hsi_def_type { + ECORE_HSI_DEF_MAX_NUM_VFS, + ECORE_HSI_DEF_MAX_NUM_L2_QUEUES, + ECORE_HSI_DEF_MAX_NUM_PORTS, + ECORE_HSI_DEF_MAX_SB_PER_PATH, + ECORE_HSI_DEF_MAX_NUM_PFS, + ECORE_HSI_DEF_MAX_NUM_VPORTS, + ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE, + ECORE_HSI_DEF_MAX_QM_TX_QUEUES, + ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS, + ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS, + ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS, + ECORE_HSI_DEF_MAX_PBF_CMD_LINES, + ECORE_HSI_DEF_MAX_BTB_BLOCKS, + ECORE_NUM_HSI_DEFS +}; + +u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev, + enum ecore_hsi_def_type type); + +#define NUM_OF_VFS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS) +#define NUM_OF_L2_QUEUES(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES) +#define NUM_OF_PORTS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS) +#define NUM_OF_SBS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH) +#define NUM_OF_ENG_PFS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS) +#define NUM_OF_VPORTS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS) +#define NUM_OF_RSS_ENGINES(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE) +#define NUM_OF_QM_TX_QUEUES(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES) +#define NUM_OF_PXP_ILT_RECORDS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS) +#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS) +#define NUM_OF_QM_GLOBAL_RLS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS) +#define NUM_OF_PBF_CMD_LINES(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES) +#define NUM_OF_BTB_BLOCKS(dev) \ + ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS) + +#define CRC8_TABLE_SIZE 256 /** * @brief ecore_concrete_to_sw_fid - get the sw function id from @@ -813,8 +975,7 @@ struct ecore_dev { * * @return OSAL_INLINE u8 */ -static OSAL_INLINE u8 -ecore_concrete_to_sw_fid(__rte_unused struct ecore_dev *p_dev, u32 concrete_fid) +static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) { u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); @@ -829,7 +990,6 @@ ecore_concrete_to_sw_fid(__rte_unused struct ecore_dev *p_dev, u32 concrete_fid) return sw_fid; } -#define PURE_LB_TC 8 #define PKT_LB_TC 9 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); @@ -853,12 +1013,25 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, #define PQ_FLAGS_ACK (1 << 4) #define PQ_FLAGS_OFLD (1 << 5) #define PQ_FLAGS_VFS (1 << 6) +#define PQ_FLAGS_LLT (1 << 7) /* physical queue index for cm context intialization */ u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); -u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); +u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); + +/* qm vport for rate limit configuration */ +u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); + +const char *ecore_hw_get_resc_name(enum ecore_resources res_id); + +/* doorbell recovery mechanism */ +void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); +void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, + enum ecore_db_rec_exec); + +bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn); /* amount of resources used in qm init */ u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); @@ -867,8 +1040,34 @@ u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); -#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) +#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ + ecore_device_num_ports((_p_hwfn)->p_dev)) -const char *ecore_hw_get_resc_name(enum ecore_resources res_id); +/* The PFID<->PPFID calculation is based on the relative index of a PF on its + * port. In BB there is a bug in the LLH in which the PPFID is actually engine + * based, and thus it equals the PFID. + */ +#define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \ + (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ + (abs_ppfid) : \ + (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \ + MFW_PORT(_p_hwfn)) +#define ECORE_PPFID_BY_PFID(_p_hwfn) \ + (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ + (_p_hwfn)->rel_pf_id : \ + (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine) + +enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u32 addr, + u32 val); + +/* Utility functions for dumping the content of the NIG LLH filters */ +enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid); +enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev); + +#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A + +#define MSTORM_QZONE_START(dev) \ + (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev))) #endif /* __ECORE_H */