X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fecore_init_fw_funcs.c;h=fa1e89a86de31b2fc84d7446cf4be3e3abfcfc1f;hb=3b307c55f2ac;hp=004ab351a327e6c7f7826074cd17f0b8a7cb5369;hpb=53437002903f647d10dc6f7d4ed0049bbcf040ec;p=dpdk.git diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index 004ab351a3..fa1e89a86d 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -1,9 +1,7 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ #include "bcm_osal.h" @@ -11,31 +9,29 @@ #include "ecore_init_ops.h" #include "reg_addr.h" #include "ecore_rt_defs.h" -#include "ecore_hsi_common.h" #include "ecore_hsi_init_func.h" -#include "ecore_hsi_eth.h" #include "ecore_hsi_init_tool.h" #include "ecore_iro.h" #include "ecore_init_fw_funcs.h" - -#define CDU_VALIDATION_DEFAULT_CFG 61 - -static u16 con_region_offsets[3][E4_NUM_OF_CONNECTION_TYPES] = { - { 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */ - { 528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */ - { 608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */ +static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = { + { 400, 336, 352, 368, 304, 384, 416, 352}, /* region 3 offsets */ + { 528, 496, 416, 512, 448, 512, 544, 480}, /* region 4 offsets */ + { 608, 544, 496, 576, 576, 592, 624, 560} /* region 5 offsets */ }; -static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { +static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = { { 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */ }; /* General constants */ -#define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \ - QM_PQ_ELEMENT_SIZE, 0x1000) : 0) -#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : \ - 0) +#define QM_PQ_MEM_4KB(pq_size) \ + (pq_size ? DIV_ROUND_UP((pq_size + 1) * QM_PQ_ELEMENT_SIZE, 0x1000) : 0) +#define QM_PQ_SIZE_256B(pq_size) \ + (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : 0) #define QM_INVALID_PQ_ID 0xffff +/* Max link speed (in Mbps) */ +#define QM_MAX_LINK_SPEED 100000 + /* Feature enable */ #define QM_BYPASS_EN 1 #define QM_BYTE_CRD_EN 1 @@ -43,6 +39,10 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { /* Other PQ constants */ #define QM_OTHER_PQS_PER_PF 4 +/* VOQ constants */ +#define MAX_NUM_VOQS (MAX_NUM_PORTS_K2 * NUM_TCS_4PORT_K2) +#define VOQS_BIT_MASK ((1 << MAX_NUM_VOQS) - 1) + /* WFQ constants: */ /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */ @@ -57,23 +57,17 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { /* 0x9000 = 4*9*1024 */ #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000) -/* 0.7 * upper bound (62500000) */ -#define QM_WFQ_MAX_INC_VAL 43750000 +/* Max WFQ increment value is 0.7 * upper bound */ +#define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10) /* RL constants: */ -/* Upper bound is set to 10 * burst size of 1ms in 50Gbps */ -#define QM_RL_UPPER_BOUND 62500000 - /* Period in us */ #define QM_RL_PERIOD 5 /* Period in 25MHz cycles */ #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD) -/* 0.7 * upper bound (62500000) */ -#define QM_RL_MAX_INC_VAL 43750000 - /* RL increment value - rate is specified in mbps. the factor of 1.01 was * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC * 2544 test. In this scenario the PF RL was reducing the line rate to 99% @@ -81,8 +75,25 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { * correct packet sizes. The reason for the inaccuracy of the RL is unknown at * this point. */ -#define QM_RL_INC_VAL(rate) OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * \ - QM_RL_PERIOD * 101) / (8 * 100)), 1) +#define QM_RL_INC_VAL(rate) \ + OSAL_MAX_T(u32, (u32)(((rate ? rate : 100000) * QM_RL_PERIOD * 101) / \ + (8 * 100)), 1) + +/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */ +#define QM_PF_RL_UPPER_BOUND 62500000 + +/* Max PF RL increment value is 0.7 * upper bound */ +#define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10) + +/* Vport RL Upper bound, link speed is in Mpbs */ +#define QM_VP_RL_UPPER_BOUND(speed) \ + ((u32)OSAL_MAX_T(u32, QM_RL_INC_VAL(speed), 9700 + 1000)) + +/* Max Vport RL increment value is the Vport RL upper bound */ +#define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed) + +/* Vport RL credit threshold in case of QM bypass */ +#define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1) /* AFullOprtnstcCrdMask constants */ #define QM_OPPOR_LINE_VOQ_DEF 1 @@ -94,13 +105,15 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { /* Pure LB CmdQ lines (+spare) */ #define PBF_CMDQ_PURE_LB_LINES 150 -#define PBF_CMDQ_LINES_RT_OFFSET(voq) \ - (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \ +#define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \ + (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \ + ext_voq * \ (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \ PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET)) -#define PBF_BTB_GUARANTEED_RT_OFFSET(voq) \ - (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \ +#define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \ + (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \ + ext_voq * \ (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \ PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET)) @@ -140,14 +153,29 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = { #define QM_CMD_SET_FIELD(var, cmd, field, value) \ SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value) -/* QM: VOQ macros */ -#define PHYS_VOQ(port, tc, max_phys_tcs_per_port) \ - ((port) * (max_phys_tcs_per_port) + (tc)) -#define LB_VOQ(port) (MAX_PHYS_VOQS + (port)) -#define VOQ(port, tc, max_phys_tcs_per_port) \ - ((tc) < LB_TC ? PHYS_VOQ(port, tc, max_phys_tcs_per_port) : \ - LB_VOQ(port)) - +#define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, \ + rl_valid, rl_id, voq, wrr) \ + do { \ + OSAL_MEMSET(&(map), 0, sizeof(map)); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_PQ_VALID, 1); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_RL_ID, rl_id); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_VP_PQ_ID, vp_pq_id); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_VOQ, voq); \ + SET_FIELD(map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, wrr); \ + STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \ + *((u32 *)&(map))); \ + } while (0) + +#define WRITE_PQ_INFO_TO_RAM 1 + +#define PQ_INFO_ELEMENT(vp_pq_id, pf, tc, port, rl_valid, rl_id) \ + (((vp_pq_id) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \ + ((rl_valid ? 1 : 0) << 22) | (((rl_id) & 255) << 24) | \ + (((rl_id) >> 8) << 9)) + +#define PQ_INFO_RAM_GRC_ADDRESS(pq_id) (XSEM_REG_FAST_MEMORY + \ + SEM_FAST_REG_INT_RAM + XSTORM_PQ_INFO_OFFSET(pq_id)) /******************** INTERNAL IMPLEMENTATION *********************/ @@ -158,7 +186,7 @@ static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en) if (pf_rl_en) { /* Enable RLs for all VOQs */ STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET, - (1 << MAX_NUM_VOQS) - 1); + VOQS_BIT_MASK); /* Write RL period */ STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET, @@ -169,7 +197,7 @@ static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en) /* Set credit threshold for QM bypass flow */ if (QM_BYPASS_EN) STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET, - QM_RL_UPPER_BOUND); + QM_PF_RL_UPPER_BOUND); } } @@ -184,12 +212,13 @@ static void ecore_enable_pf_wfq(struct ecore_hwfn *p_hwfn, bool pf_wfq_en) QM_WFQ_UPPER_BOUND); } -/* Prepare VPORT RL enable/disable runtime init values */ -static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn, bool vport_rl_en) +/* Prepare global RL enable/disable runtime init values */ +static void ecore_enable_global_rl(struct ecore_hwfn *p_hwfn, + bool global_rl_en) { STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, - vport_rl_en ? 1 : 0); - if (vport_rl_en) { + global_rl_en ? 1 : 0); + if (global_rl_en) { /* Write RL period (use timer 0 only) */ STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M); @@ -200,7 +229,7 @@ static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn, bool vport_rl_en) if (QM_BYPASS_EN) STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET, - QM_RL_UPPER_BOUND); + QM_VP_RL_BYPASS_THRESH_SPEED); } } @@ -220,11 +249,10 @@ static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn, bool vport_wfq_en) * the specified VOQ */ static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn, - u8 voq, u16 cmdq_lines) + u8 voq, + u16 cmdq_lines) { - u32 qm_line_crd; - - qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines); + u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines); OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), (u32)cmdq_lines); @@ -242,7 +270,7 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn, { u8 tc, voq, port_id, num_tcs_in_port; - /* Clear PBF lines for all VOQs */ + /* Clear PBF lines of all VOQs */ for (voq = 0; voq < MAX_NUM_VOQS; voq++) STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0); @@ -252,31 +280,32 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn, if (!port_params[port_id].active) continue; - /* Find #lines to divide between the active physical TCs */ - phys_lines = port_params[port_id].num_pbf_cmd_lines - - PBF_CMDQ_PURE_LB_LINES; + /* Find number of command queue lines to divide between the + * active physical TCs. + */ + phys_lines = port_params[port_id].num_pbf_cmd_lines; + phys_lines -= PBF_CMDQ_PURE_LB_LINES; /* Find #lines per active physical TC */ num_tcs_in_port = 0; - for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) + for (tc = 0; tc < max_phys_tcs_per_port; tc++) if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) num_tcs_in_port++; phys_lines_per_tc = phys_lines / num_tcs_in_port; /* Init registers per active TC */ - for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) { - if (((port_params[port_id].active_phys_tcs >> tc) & - 0x1) == 1) { - voq = PHYS_VOQ(port_id, tc, - max_phys_tcs_per_port); + for (tc = 0; tc < max_phys_tcs_per_port; tc++) { + voq = VOQ(port_id, tc, max_phys_tcs_per_port); + if (((port_params[port_id].active_phys_tcs >> + tc) & 0x1) == 1) ecore_cmdq_lines_voq_rt_init(p_hwfn, voq, phys_lines_per_tc); - } } /* Init registers for pure LB TC */ - ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id), + voq = VOQ(port_id, PURE_LB_TC, max_phys_tcs_per_port); + ecore_cmdq_lines_voq_rt_init(p_hwfn, voq, PBF_CMDQ_PURE_LB_LINES); } } @@ -339,35 +368,69 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn, /* Init physical TCs */ for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) { if (((port_params[port_id].active_phys_tcs >> tc) & - 0x1) == 1) { - voq = PHYS_VOQ(port_id, tc, - max_phys_tcs_per_port); + 0x1) == 1) { + voq = VOQ(port_id, tc, max_phys_tcs_per_port); STORE_RT_REG(p_hwfn, - PBF_BTB_GUARANTEED_RT_OFFSET(voq), - phys_blocks); + PBF_BTB_GUARANTEED_RT_OFFSET(voq), + phys_blocks); } } /* Init pure LB TC */ - STORE_RT_REG(p_hwfn, - PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ(port_id)), + voq = VOQ(port_id, PURE_LB_TC, max_phys_tcs_per_port); + STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq), pure_lb_blocks); } } +/* Prepare runtime init values for the specified RL. + * If global_rl_params is OSAL_NULL, max link speed (100Gbps) is used instead. + * Return -1 on error. + */ +static int ecore_global_rl_rt_init(struct ecore_hwfn *p_hwfn, + struct init_qm_global_rl_params + global_rl_params[COMMON_MAX_QM_GLOBAL_RLS]) +{ + u32 upper_bound = QM_VP_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) | + (u32)QM_RL_CRD_REG_SIGN_BIT; + u32 inc_val; + u16 rl_id; + + /* Go over all global RLs */ + for (rl_id = 0; rl_id < MAX_QM_GLOBAL_RLS; rl_id++) { + u32 rate_limit = global_rl_params ? + global_rl_params[rl_id].rate_limit : 0; + + inc_val = QM_RL_INC_VAL(rate_limit ? + rate_limit : QM_MAX_LINK_SPEED); + if (inc_val > QM_VP_RL_MAX_INC_VAL(QM_MAX_LINK_SPEED)) { + DP_NOTICE(p_hwfn, true, "Invalid rate limit configuration.\n"); + return -1; + } + + STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + rl_id, + (u32)QM_RL_CRD_REG_SIGN_BIT); + STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id, + upper_bound); + STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id, + inc_val); + } + + return 0; +} + /* Prepare Tx PQ mapping runtime init values for the specified PF */ -static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, +static int ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u8 port_id, u8 pf_id, u8 max_phys_tcs_per_port, - bool is_first_pf, + bool is_pf_loading, u32 num_pf_cids, u32 num_vf_cids, u16 start_pq, u16 num_pf_pqs, u16 num_vf_pqs, - u8 start_vport, + u16 start_vport, u32 base_mem_addr_4kb, struct init_qm_pq_params *pq_params, struct init_qm_vport_params *vport_params) @@ -375,8 +438,11 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, /* A bit per Tx PQ indicating if the PQ is associated with a VF */ u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 }; u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE; - u16 num_pqs, first_pq_group, last_pq_group, i, pq_id, pq_group; + u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group; u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb; + #if (WRITE_PQ_INFO_TO_RAM != 0) + u32 pq_info = 0; + #endif num_pqs = num_pf_pqs + num_vf_pqs; @@ -400,60 +466,59 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, /* Go over all Tx PQs */ for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) { - u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS; + u16 first_tx_pq_id, vport_id_in_pf; struct qm_rf_pq_map tx_pq_map; - bool is_vf_pq, rl_valid; - u8 voq, vport_id_in_pf; - u16 first_tx_pq_id; + bool is_vf_pq; + u8 voq; - voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port); + voq = VOQ(pq_params[i].port_id, pq_params[i].tc_id, + max_phys_tcs_per_port); is_vf_pq = (i >= num_pf_pqs); - rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id < - max_qm_global_rls; /* Update first Tx PQ of VPORT/TC */ vport_id_in_pf = pq_params[i].vport_id - start_vport; first_tx_pq_id = vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id]; if (first_tx_pq_id == QM_INVALID_PQ_ID) { + u32 map_val = (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | + (pf_id << QM_WFQ_VP_PQ_PF_SHIFT); + /* Create new VP PQ */ vport_params[vport_id_in_pf]. first_tx_pq_id[pq_params[i].tc_id] = pq_id; first_tx_pq_id = pq_id; /* Map VP PQ to VOQ and PF */ - STORE_RT_REG(p_hwfn, - QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id, - (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id << - QM_WFQ_VP_PQ_PF_SHIFT)); + STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET + + first_tx_pq_id, map_val); } - /* Check RL ID */ - if (pq_params[i].rl_valid && pq_params[i].vport_id >= - max_qm_global_rls) - DP_NOTICE(p_hwfn, true, - "Invalid VPORT ID for rate limiter config\n"); - - /* Fill PQ map entry */ - OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map)); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID, - rl_valid ? 1 : 0); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID, - rl_valid ? pq_params[i].vport_id : 0); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq); - SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, - pq_params[i].wrr_group); - - /* Write PQ map entry to CAM */ - STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, - *((u32 *)&tx_pq_map)); - - /* Set base address */ + /* Prepare PQ map entry */ + QM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, pq_id, first_tx_pq_id, + pq_params[i].rl_valid, pq_params[i].rl_id, + voq, pq_params[i].wrr_group); + + /* Set PQ base address */ STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, mem_addr_4kb); + /* Clear PQ pointer table entry (64 bit) */ + if (is_pf_loading) + for (j = 0; j < 2; j++) + STORE_RT_REG(p_hwfn, QM_REG_PTRTBLTX_RT_OFFSET + + (pq_id * 2) + j, 0); + + /* Write PQ info to RAM */ +#if (WRITE_PQ_INFO_TO_RAM != 0) + pq_info = PQ_INFO_ELEMENT(first_tx_pq_id, pf_id, + pq_params[i].tc_id, + pq_params[i].port_id, + pq_params[i].rl_valid, + pq_params[i].rl_id); + ecore_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id), + pq_info); +#endif + /* If VF PQ, add indication to PQ VF mask */ if (is_vf_pq) { tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |= @@ -469,17 +534,20 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, if (tx_pq_vf_mask[i]) STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, tx_pq_vf_mask[i]); + + return 0; } /* Prepare Other PQ mapping runtime init values for the specified PF */ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, - u8 port_id, u8 pf_id, + bool is_pf_loading, u32 num_pf_cids, - u32 num_tids, u32 base_mem_addr_4kb) + u32 num_tids, + u32 base_mem_addr_4kb) { u32 pq_size, pq_mem_4kb, mem_addr_4kb; - u16 i, pq_id, pq_group; + u16 i, j, pq_id, pq_group; /* A single other PQ group is used in each PF, where PQ group i is used * in PF i. @@ -497,11 +565,19 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, QM_PQ_SIZE_256B(pq_size)); - /* Set base address */ for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; i < QM_OTHER_PQS_PER_PF; i++, pq_id++) { + /* Set PQ base address */ STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, mem_addr_4kb); + + /* Clear PQ pointer table entry */ + if (is_pf_loading) + for (j = 0; j < 2; j++) + STORE_RT_REG(p_hwfn, + QM_REG_PTRTBLOTHER_RT_OFFSET + + (pq_id * 2) + j, 0); + mem_addr_4kb += pq_mem_4kb; } } @@ -510,7 +586,6 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, * Return -1 on error. */ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, - u8 port_id, u8 pf_id, u16 pf_wfq, u8 max_phys_tcs_per_port, @@ -521,10 +596,6 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, u8 voq; u16 i; - crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET : - QM_REG_WFQPFCRD_MSB_RT_OFFSET) + - (pf_id % MAX_NUM_PFS_BB); - inc_val = QM_WFQ_INC_VAL(pf_wfq); if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) { DP_NOTICE(p_hwfn, true, @@ -533,14 +604,21 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, } for (i = 0; i < num_tx_pqs; i++) { - voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port); - OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB, + voq = VOQ(pq_params[i].port_id, pq_params[i].tc_id, + max_phys_tcs_per_port); + crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? + QM_REG_WFQPFCRD_RT_OFFSET : + QM_REG_WFQPFCRD_MSB_RT_OFFSET) + + voq * MAX_NUM_PFS_BB + + (pf_id % MAX_NUM_PFS_BB); + OVERWRITE_RT_REG(p_hwfn, crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT); } - STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, - QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT); + STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT); STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val); + return 0; } @@ -552,7 +630,7 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl) u32 inc_val; inc_val = QM_RL_INC_VAL(pf_rl); - if (inc_val > QM_RL_MAX_INC_VAL) { + if (inc_val > QM_PF_RL_MAX_INC_VAL) { DP_NOTICE(p_hwfn, true, "Invalid PF rate limit configuration\n"); return -1; @@ -561,7 +639,7 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl) STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id, (u32)QM_RL_CRD_REG_SIGN_BIT); STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, - QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT); + QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT); STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val); return 0; @@ -571,19 +649,19 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl) * Return -1 on error. */ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn, - u8 num_vports, + u16 num_vports, struct init_qm_vport_params *vport_params) { - u16 vport_pq_id; + u16 vp_pq_id, vport_id; u32 inc_val; - u8 tc, i; + u8 tc; /* Go over all PF VPORTs */ - for (i = 0; i < num_vports; i++) { - if (!vport_params[i].vport_wfq) + for (vport_id = 0; vport_id < num_vports; vport_id++) { + if (!vport_params[vport_id].wfq) continue; - inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq); + inc_val = QM_WFQ_INC_VAL(vport_params[vport_id].wfq); if (inc_val > QM_WFQ_MAX_INC_VAL) { DP_NOTICE(p_hwfn, true, "Invalid VPORT WFQ weight configuration\n"); @@ -592,53 +670,15 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn, /* Each VPORT can have several VPORT PQ IDs for various TCs */ for (tc = 0; tc < NUM_OF_TCS; tc++) { - vport_pq_id = vport_params[i].first_tx_pq_id[tc]; - if (vport_pq_id != QM_INVALID_PQ_ID) { - STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET + - vport_pq_id, - (u32)QM_WFQ_CRD_REG_SIGN_BIT); - STORE_RT_REG(p_hwfn, - QM_REG_WFQVPWEIGHT_RT_OFFSET + - vport_pq_id, inc_val); - } - } - } - return 0; -} - -/* Prepare VPORT RL runtime init values for the specified VPORTs. - * Return -1 on error. - */ -static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn, - u8 start_vport, - u8 num_vports, - struct init_qm_vport_params *vport_params) -{ - u8 i, vport_id; - u32 inc_val; - - if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) { - DP_NOTICE(p_hwfn, true, - "Invalid VPORT ID for rate limiter configuration\n"); - return -1; - } - - /* Go over all PF VPORTs */ - for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) { - u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl); - if (inc_val > QM_RL_MAX_INC_VAL) { - DP_NOTICE(p_hwfn, true, - "Invalid VPORT rate-limit configuration\n"); - return -1; + vp_pq_id = vport_params[vport_id].first_tx_pq_id[tc]; + if (vp_pq_id == QM_INVALID_PQ_ID) + continue; + + STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET + + vp_pq_id, (u32)QM_WFQ_CRD_REG_SIGN_BIT); + STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET + + vp_pq_id, inc_val); } - - STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id, - (u32)QM_RL_CRD_REG_SIGN_BIT); - STORE_RT_REG(p_hwfn, - QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id, - QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT); - STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id, - inc_val); } return 0; @@ -667,7 +707,9 @@ static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn, static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb) + u32 cmd_addr, + u32 cmd_data_lsb, + u32 cmd_data_msb) { if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt)) return false; @@ -681,13 +723,14 @@ static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn, return ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt); } - /******************** INTERFACE IMPLEMENTATION *********************/ -u32 ecore_qm_pf_mem_size(u8 pf_id, +u32 ecore_qm_pf_mem_size(struct ecore_hwfn *p_hwfn, u32 num_pf_cids, - u32 num_vf_cids, - u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs) + u32 num_vf_cids, + u32 num_tids, + u16 num_pf_pqs, + u16 num_vf_pqs) { return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs + QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs + @@ -699,25 +742,26 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, u8 max_phys_tcs_per_port, bool pf_rl_en, bool pf_wfq_en, - bool vport_rl_en, + bool global_rl_en, bool vport_wfq_en, struct init_qm_port_params - port_params[MAX_NUM_PORTS]) + port_params[MAX_NUM_PORTS], + struct init_qm_global_rl_params + global_rl_params[COMMON_MAX_QM_GLOBAL_RLS]) { - u32 mask; + u32 mask = 0; /* Init AFullOprtnstcCrdMask */ - mask = (QM_OPPOR_LINE_VOQ_DEF << - QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) | - (QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) | - (pf_wfq_en << QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT) | - (vport_wfq_en << QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT) | - (pf_rl_en << QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT) | - (vport_rl_en << QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT) | - (QM_OPPOR_FW_STOP_DEF << - QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT) | - (QM_OPPOR_PQ_EMPTY_DEF << - QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ, + QM_OPPOR_LINE_VOQ_DEF); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ, pf_wfq_en); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ, vport_wfq_en); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL, pf_rl_en); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL, global_rl_en); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF); + SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY, + QM_OPPOR_PQ_EMPTY_DEF); STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask); /* Enable/disable PF RL */ @@ -726,8 +770,8 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, /* Enable/disable PF WFQ */ ecore_enable_pf_wfq(p_hwfn, pf_wfq_en); - /* Enable/disable VPORT RL */ - ecore_enable_vport_rl(p_hwfn, vport_rl_en); + /* Enable/disable global RL */ + ecore_enable_global_rl(p_hwfn, global_rl_en); /* Enable/disable VPORT WFQ */ ecore_enable_vport_wfq(p_hwfn, vport_wfq_en); @@ -740,72 +784,71 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, ecore_btb_blocks_rt_init(p_hwfn, max_ports_per_engine, max_phys_tcs_per_port, port_params); + ecore_global_rl_rt_init(p_hwfn, global_rl_params); + return 0; } int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u8 port_id, u8 pf_id, u8 max_phys_tcs_per_port, - bool is_first_pf, + bool is_pf_loading, u32 num_pf_cids, u32 num_vf_cids, u32 num_tids, u16 start_pq, u16 num_pf_pqs, u16 num_vf_pqs, - u8 start_vport, - u8 num_vports, + u16 start_vport, + u16 num_vports, u16 pf_wfq, u32 pf_rl, struct init_qm_pq_params *pq_params, struct init_qm_vport_params *vport_params) { u32 other_mem_size_4kb; - u8 tc, i; + u16 vport_id; + u8 tc; other_mem_size_4kb = QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF; /* Clear first Tx PQ ID array for each VPORT */ - for (i = 0; i < num_vports; i++) + for (vport_id = 0; vport_id < num_vports; vport_id++) for (tc = 0; tc < NUM_OF_TCS; tc++) - vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID; + vport_params[vport_id].first_tx_pq_id[tc] = + QM_INVALID_PQ_ID; /* Map Other PQs (if any) */ #if QM_OTHER_PQS_PER_PF > 0 - ecore_other_pq_map_rt_init(p_hwfn, port_id, pf_id, num_pf_cids, + ecore_other_pq_map_rt_init(p_hwfn, pf_id, is_pf_loading, num_pf_cids, num_tids, 0); #endif /* Map Tx PQs */ - ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id, - max_phys_tcs_per_port, is_first_pf, num_pf_cids, - num_vf_cids, start_pq, num_pf_pqs, num_vf_pqs, - start_vport, other_mem_size_4kb, pq_params, - vport_params); + if (ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, pf_id, max_phys_tcs_per_port, + is_pf_loading, num_pf_cids, num_vf_cids, + start_pq, num_pf_pqs, num_vf_pqs, + start_vport, other_mem_size_4kb, pq_params, + vport_params)) + return -1; /* Init PF WFQ */ if (pf_wfq) - if (ecore_pf_wfq_rt_init - (p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port, - num_pf_pqs + num_vf_pqs, pq_params)) + if (ecore_pf_wfq_rt_init(p_hwfn, pf_id, pf_wfq, + max_phys_tcs_per_port, + num_pf_pqs + num_vf_pqs, pq_params)) return -1; /* Init PF RL */ if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl)) return -1; - /* Set VPORT WFQ */ + /* Init VPORT WFQ */ if (ecore_vp_wfq_rt_init(p_hwfn, num_vports, vport_params)) return -1; - /* Set VPORT RL */ - if (ecore_vport_rl_rt_init - (p_hwfn, start_vport, num_vports, vport_params)) - return -1; - return 0; } @@ -832,7 +875,7 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn, u32 inc_val; inc_val = QM_RL_INC_VAL(pf_rl); - if (inc_val > QM_RL_MAX_INC_VAL) { + if (inc_val > QM_PF_RL_MAX_INC_VAL) { DP_NOTICE(p_hwfn, true, "Invalid PF rate limit configuration\n"); return -1; @@ -847,32 +890,56 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn, int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq) + u16 first_tx_pq_id[NUM_OF_TCS], + u16 wfq) { - u16 vport_pq_id; + u16 vp_pq_id; u32 inc_val; u8 tc; - inc_val = QM_WFQ_INC_VAL(vport_wfq); + inc_val = QM_WFQ_INC_VAL(wfq); if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) { DP_NOTICE(p_hwfn, true, "Invalid VPORT WFQ weight configuration\n"); return -1; } + /* A VPORT can have several VPORT PQ IDs for various TCs */ for (tc = 0; tc < NUM_OF_TCS; tc++) { - vport_pq_id = first_tx_pq_id[tc]; - if (vport_pq_id != QM_INVALID_PQ_ID) { + vp_pq_id = first_tx_pq_id[tc]; + if (vp_pq_id != QM_INVALID_PQ_ID) { ecore_wr(p_hwfn, p_ptt, - QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val); + QM_REG_WFQVPWEIGHT + vp_pq_id * 4, inc_val); + } + } + + return 0; } + +int ecore_init_global_rl(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u16 rl_id, + u32 rate_limit) +{ + u32 inc_val; + + inc_val = QM_RL_INC_VAL(rate_limit); + if (inc_val > QM_VP_RL_MAX_INC_VAL(rate_limit)) { + DP_NOTICE(p_hwfn, true, "Invalid rate limit configuration.\n"); + return -1; } + ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + rl_id * 4, + (u32)QM_RL_CRD_REG_SIGN_BIT); + ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val); + return 0; } int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, u8 vport_id, u32 vport_rl) + struct ecore_ptt *p_ptt, u8 vport_id, + u32 vport_rl, + u32 link_speed) { u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS; @@ -882,8 +949,8 @@ int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn, return -1; } - inc_val = QM_RL_INC_VAL(vport_rl); - if (inc_val > QM_RL_MAX_INC_VAL) { + inc_val = QM_RL_INC_VAL(vport_rl ? vport_rl : link_speed); + if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) { DP_NOTICE(p_hwfn, true, "Invalid VPORT rate-limit configuration\n"); return -1; @@ -934,6 +1001,7 @@ bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn, return true; } +#ifndef UNUSED_HSI_FUNC /* NIG: ETS configuration constants */ #define NIG_TX_ETS_CLIENT_OFFSET 4 @@ -1157,6 +1225,9 @@ void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn, } } +#endif /* UNUSED_HSI_FUNC */ + +#ifndef UNUSED_HSI_FUNC /* PRS: ETS configuration constants */ #define PRS_ETS_MIN_WFQ_BYTES 1600 @@ -1223,6 +1294,8 @@ void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn, } } +#endif /* UNUSED_HSI_FUNC */ +#ifndef UNUSED_HSI_FUNC /* BRB: RAM configuration constants */ #define BRB_TOTAL_RAM_BLOCKS_BB 4800 @@ -1335,31 +1408,79 @@ void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn, } } -/* In MF should be called once per engine to set EtherType of OuterTag */ -void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, u32 ethType) +#endif /* UNUSED_HSI_FUNC */ +#ifndef UNUSED_HSI_FUNC + +#define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \ + do { \ + u32 i; \ + for (i = 0; i < (arr_size); i++) \ + ecore_wr(dev, ptt, ((addr) + (4 * i)), \ + ((u32 *)&(arr))[i]); \ + } while (0) + +#ifndef DWORDS_TO_BYTES +#define DWORDS_TO_BYTES(dwords) ((dwords) * REG_SIZE) +#endif + + +/** + * @brief ecore_dmae_to_grc - is an internal function - writes from host to + * wide-bus registers (split registers are not supported yet) + * + * @param p_hwfn - HW device data + * @param p_ptt - ptt window used for writing the registers. + * @param pData - pointer to source data. + * @param addr - Destination register address. + * @param len_in_dwords - data length in DWARDS (u32) + */ +static int ecore_dmae_to_grc(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u32 *pData, + u32 addr, + u32 len_in_dwords) { - /* Update PRS register */ - STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType); + struct dmae_params params; + bool read_using_dmae = false; - /* Update NIG register */ - STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType); + if (!pData) + return -1; - /* Update PBF register */ - STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType); + /* Set DMAE params */ + OSAL_MEMSET(¶ms, 0, sizeof(params)); + + SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 1); + + /* Execute DMAE command */ + read_using_dmae = !ecore_dmae_host2grc(p_hwfn, p_ptt, + (u64)(osal_uintptr_t)(pData), + addr, len_in_dwords, ¶ms); + if (!read_using_dmae) + DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, + "Failed writing to chip using DMAE, using GRC instead\n"); + + /* If not read using DMAE, read using GRC */ + if (!read_using_dmae) + /* write to registers using GRC */ + ARR_REG_WR(p_hwfn, p_ptt, addr, pData, len_in_dwords); + + return len_in_dwords; } -/* In MF should be called once per port to set EtherType of OuterTag */ -void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, u32 ethType) +/* In MF, should be called once per port to set EtherType of OuterTag */ +void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType) { /* Update DORQ register */ STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType); } +#endif /* UNUSED_HSI_FUNC */ + #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \ (var = ((var) & ~(1 << (offset))) | ((enable) ? (1 << (offset)) : 0)) -#define PRS_ETH_TUNN_FIC_FORMAT -188897008 +#define PRS_ETH_TUNN_OUTPUT_FORMAT -188897008 +#define PRS_ETH_OUTPUT_FORMAT -46832 + void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 dest_port) { @@ -1384,9 +1505,14 @@ void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1416,9 +1542,14 @@ void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1466,9 +1597,14 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT, ip_geneve_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1482,12 +1618,43 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, return; /* Update DORQ registers */ - ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5, + ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2, eth_geneve_enable ? 1 : 0); - ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5, + ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2, ip_geneve_enable ? 1 : 0); } +#define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 3 +#define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -925189872 + +void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + bool enable) +{ + u32 reg_val, cfg_mask; + + /* read PRS config register */ + reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO); + + /* set VXLAN_NO_L2_ENABLE mask */ + cfg_mask = (1 << PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); + + if (enable) { + /* set VXLAN_NO_L2_ENABLE flag */ + reg_val |= cfg_mask; + + /* update PRS FIC Format register */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT); + /* clear VXLAN_NO_L2_ENABLE flag */ + reg_val &= ~cfg_mask; + } + + /* write PRS config register */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val); +} + +#ifndef UNUSED_HSI_FUNC #define T_ETH_PACKET_ACTION_GFT_EVENTID 23 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272 @@ -1497,35 +1664,26 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, #define RAM_LINE_SIZE sizeof(u64) #define REG_SIZE sizeof(u32) -void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u16 pf_id) +void ecore_gft_disable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u16 pf_id) { - union gft_cam_line_union cam_line; - struct gft_ram_line ram_line; - u32 i, *ram_line_ptr; - - ram_line_ptr = (u32 *)&ram_line; + struct regpair ram_line; + OSAL_MEMSET(&ram_line, 0, sizeof(ram_line)); - /* Stop using gft logic, disable gft search */ + /* disable gft search for PF */ ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0); - ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, 0x0); - /* Clean ram & cam for next rfs/gft session*/ + /* Clean ram & cam for next gft session*/ /* Zero camline */ - OSAL_MEMSET(&cam_line, 0, sizeof(cam_line)); - ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, - cam_line.cam_line_mapped.camline); + ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0); /* Zero ramline */ - OSAL_MEMSET(&ram_line, 0, sizeof(ram_line)); + ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line, + PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, + sizeof(ram_line) / REG_SIZE); - /* Each iteration write to reg */ - for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++) - ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + - RAM_LINE_SIZE * pf_id + - i * REG_SIZE, *(ram_line_ptr + i)); } @@ -1543,115 +1701,130 @@ void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn, ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id); } -void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn, +void ecore_gft_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 pf_id, bool tcp, bool udp, bool ipv4, - bool ipv6) + bool ipv6, + enum gft_profile_type profile_type) { - u32 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT); - union gft_cam_line_union camLine; - struct gft_ram_line ramLine; - u32 *ramLinePointer = (u32 *)&ramLine; - int i; + u32 reg_val, cam_line, search_non_ip_as_gft; + struct regpair ram_line = { 0 }; if (!ipv6 && !ipv4) - DP_NOTICE(p_hwfn, true, - "set_rfs_mode_enable: must accept at " - "least on of - ipv4 or ipv6"); - + DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - ipv4 or ipv6'\n"); if (!tcp && !udp) - DP_NOTICE(p_hwfn, true, - "set_rfs_mode_enable: must accept at " - "least on of - udp or tcp"); + DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - udp or tcp\n"); + if (profile_type >= MAX_GFT_PROFILE_TYPE) + DP_NOTICE(p_hwfn, true, "gft_config: unsupported gft_profile_type\n"); /* Set RFS event ID to be awakened i Tstorm By Prs */ - rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID << - PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT; - rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR << - PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT; - ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id); + reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID << + PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT; + reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT; + ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val); - /* Configure Registers for RFS mode */ + /* Do not load context only cid in PRS on match. */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); - /* Enable gft search */ - ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1); - ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); /* do not load - * context only cid - * in PRS on match - */ - camLine.cam_line_mapped.camline = 0; + /* Do not use tenant ID exist bit for gft search*/ + ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0); - /* Cam line is now valid!! */ - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_VALID, 1); + /* Set Cam */ + cam_line = 0; + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1); /* Filters are per PF!! */ - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_PF_ID_MASK, 1); - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_PF_ID, pf_id); + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID_MASK, + GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK); + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id); if (!(tcp && udp)) { - SET_FIELD(camLine.cam_line_mapped.camline, + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK); if (tcp) - SET_FIELD(camLine.cam_line_mapped.camline, + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, GFT_PROFILE_TCP_PROTOCOL); else - SET_FIELD(camLine.cam_line_mapped.camline, + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, GFT_PROFILE_UDP_PROTOCOL); } if (!(ipv4 && ipv6)) { - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1); + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1); if (ipv4) - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_IP_VERSION, + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION, GFT_PROFILE_IPV4); else - SET_FIELD(camLine.cam_line_mapped.camline, - GFT_CAM_LINE_MAPPED_IP_VERSION, + SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION, GFT_PROFILE_IPV6); } /* Write characteristics to cam */ ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, - camLine.cam_line_mapped.camline); - camLine.cam_line_mapped.camline = - ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id); + cam_line); + cam_line = ecore_rd(p_hwfn, p_ptt, + PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id); /* Write line to RAM - compare to filter 4 tuple */ - ramLine.lo = 0; - ramLine.hi = 0; - SET_FIELD(ramLine.hi, GFT_RAM_LINE_DST_IP, 1); - SET_FIELD(ramLine.hi, GFT_RAM_LINE_SRC_IP, 1); - SET_FIELD(ramLine.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); - SET_FIELD(ramLine.lo, GFT_RAM_LINE_ETHERTYPE, 1); - SET_FIELD(ramLine.lo, GFT_RAM_LINE_SRC_PORT, 1); - SET_FIELD(ramLine.lo, GFT_RAM_LINE_DST_PORT, 1); - - /* Each iteration write to reg */ - for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++) - ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + - RAM_LINE_SIZE * pf_id + - i * REG_SIZE, *(ramLinePointer + i)); + + /* Search no IP as GFT */ + search_non_ip_as_gft = 0; + + /* Tunnel type */ + SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1); + + if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) { + SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1); + SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1); + SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_SRC_PORT, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1); + } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) { + SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1); + } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) { + SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) { + SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1); + SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) { + SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1); + + /* Allow tunneled traffic without inner IP */ + search_non_ip_as_gft = 1; + } + + ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT, + search_non_ip_as_gft); + ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line, + PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, + sizeof(ram_line) / REG_SIZE); /* Set default profile so that no filter match will happen */ - ramLine.lo = 0xffff; - ramLine.hi = 0xffff; - for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++) - ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + - RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH + - i * REG_SIZE, *(ramLinePointer + i)); + ram_line.lo = 0xffffffff; + ram_line.hi = 0x3ff; + ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line, + PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * + PRS_GFT_CAM_LINES_NO_MATCH, + sizeof(ram_line) / REG_SIZE); + + /* Enable gft search */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1); } + +#endif /* UNUSED_HSI_FUNC */ + /* Configure VF zone size mode */ void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 mode, @@ -1722,40 +1895,26 @@ u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, return offset; } -/* Calculate CRC8 of first 4 bytes in buf */ -static u8 ecore_calc_crc8(const u8 *buf) -{ - u32 i, j, crc = 0xff << 8; - - /* CRC-8 polynomial */ - #define POLY 0x1070 - - for (j = 0; j < 4; j++, buf++) { - crc ^= (*buf << 8); - for (i = 0; i < 8; i++) { - if (crc & 0x8000) - crc ^= (POLY << 3); - - crc <<= 1; - } - } - - return (u8)(crc >> 8); -} +#ifndef LINUX_REMOVE +#define CRC8_INIT_VALUE 0xFF +#endif +static u8 cdu_crc8_table[CRC8_TABLE_SIZE]; -/* Calculate and return CDU validation byte per conneciton type / region / +/* Calculate and return CDU validation byte per connection type / region / * cid */ -static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region, - u32 cid) +static u8 ecore_calc_cdu_validation_byte(struct ecore_hwfn *p_hwfn, + u8 conn_type, u8 region, u32 cid) { - const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG; + static u8 crc8_table_valid; /*automatically initialized to 0*/ u8 crc, validation_byte = 0; u32 validation_string = 0; - const u8 *data_to_crc_rev; - u8 data_to_crc[4]; + u32 data_to_crc; - data_to_crc_rev = (const u8 *)&validation_string; + if (crc8_table_valid == 0) { + OSAL_CRC8_POPULATE(cdu_crc8_table, 0x07); + crc8_table_valid = 1; + } /* * The CRC is calculated on the String-to-compress: @@ -1763,56 +1922,71 @@ static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region, * [7:4] = Region * [3:0] = Type */ - if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1) - validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8); - - if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1) - validation_string |= ((region & 0xF) << 4); - - if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1) - validation_string |= (conn_type & 0xF); - - /* Convert to big-endian (ntoh())*/ - data_to_crc[0] = data_to_crc_rev[3]; - data_to_crc[1] = data_to_crc_rev[2]; - data_to_crc[2] = data_to_crc_rev[1]; - data_to_crc[3] = data_to_crc_rev[0]; +#if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \ + CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1) + validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8); +#endif - crc = ecore_calc_crc8(data_to_crc); +#if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \ + CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1) + validation_string |= ((region & 0xF) << 4); +#endif - validation_byte |= ((validation_cfg >> +#if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \ + CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1) + validation_string |= (conn_type & 0xF); +#endif + /* Convert to big-endian and calculate CRC8*/ + data_to_crc = OSAL_BE32_TO_CPU(validation_string); + + crc = OSAL_CRC8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc), + CRC8_INIT_VALUE); + + /* The validation byte [7:0] is composed: + * for type A validation + * [7] = active configuration bit + * [6:0] = crc[6:0] + * + * for type B validation + * [7] = active configuration bit + * [6:3] = connection_type[3:0] + * [2:0] = crc[2:0] + */ + validation_byte |= ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7; - if ((validation_cfg >> - CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1) - validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7); - else - validation_byte |= crc & 0x7F; - +#if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \ + CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1) + validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7); +#else + validation_byte |= crc & 0x7F; +#endif return validation_byte; } /* Calcualte and set validation bytes for session context */ -void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, +void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn, + void *p_ctx_mem, u16 ctx_size, u8 ctx_type, u32 cid) { u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx; p_ctx = (u8 *)p_ctx_mem; + x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]]; t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]]; u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]]; OSAL_MEMSET(p_ctx, 0, ctx_size); - *x_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 3, cid); - *t_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 4, cid); - *u_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 5, cid); + *x_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 3, cid); + *t_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 4, cid); + *u_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 5, cid); } /* Calcualte and set validation bytes for task context */ -void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, - u8 ctx_type, u32 tid) +void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn, void *p_ctx_mem, + u16 ctx_size, u8 ctx_type, u32 tid) { u8 *p_ctx, *region1_val_ptr; @@ -1821,16 +1995,19 @@ void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, OSAL_MEMSET(p_ctx, 0, ctx_size); - *region1_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 1, tid); + *region1_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 1, + tid); } /* Memset session context to 0 while preserving validation bytes */ -void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) +void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn, void *p_ctx_mem, + u32 ctx_size, u8 ctx_type) { u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx; u8 x_val, t_val, u_val; p_ctx = (u8 *)p_ctx_mem; + x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]]; t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]]; u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]]; @@ -1847,8 +2024,8 @@ void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) } /* Memset task context to 0 while preserving validation bytes */ -void ecore_memset_task_ctx(void *p_ctx_mem, const u32 ctx_size, - const u8 ctx_type) +void ecore_memset_task_ctx(struct ecore_hwfn *p_hwfn, void *p_ctx_mem, + u32 ctx_size, u8 ctx_type) { u8 *p_ctx, *region1_val_ptr; u8 region1_val; @@ -1869,15 +2046,15 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, { u32 ctx_validation; - /* Enable validation for connection region 3 - bits [31:24] */ - ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24; + /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */ + ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 24; ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation); - /* Enable validation for connection region 5 - bits [15: 8] */ - ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8; + /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */ + ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 8; ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation); - /* Enable validation for connection region 1 - bits [15: 8] */ - ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8; + /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */ + ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 8; ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation); }