X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fecore_init_ops.c;h=b7636f365982b5414a2e083f722847e637f48d8f;hb=cbc2359676a03cdad97f6d5cac8c0026834164c1;hp=c76cc0720af4d3b3ce6b285628f06fbaafe93d25;hpb=739a5b2f2b49c15df759f0774d812ebf93d85b2a;p=dpdk.git diff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c index c76cc0720a..b7636f3659 100644 --- a/drivers/net/qede/base/ecore_init_ops.c +++ b/drivers/net/qede/base/ecore_init_ops.c @@ -1,9 +1,7 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ /* include the precompiled configuration values - only once */ @@ -176,8 +174,7 @@ static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn, static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u32 addr, u32 fill, - u32 fill_count) + u32 addr, u32 fill_count) { static u32 zero_buffer[DMAE_MAX_RW_SIZE]; @@ -309,7 +306,7 @@ static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn, case INIT_SRC_ZEROS: data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count); if (b_must_dmae || (b_can_dmae && (data >= 64))) - rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data); + rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, data); else ecore_init_fill(p_hwfn, p_ptt, addr, 0, data); break; @@ -318,10 +315,10 @@ static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn, b_must_dmae, b_can_dmae); break; case INIT_SRC_RUNTIME: - ecore_init_rt(p_hwfn, p_ptt, addr, - OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset), - OSAL_LE16_TO_CPU(p_cmd->args.runtime.size), - b_must_dmae); + rc = ecore_init_rt(p_hwfn, p_ptt, addr, + OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset), + OSAL_LE16_TO_CPU(p_cmd->args.runtime.size), + b_must_dmae); break; } @@ -390,20 +387,29 @@ static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn, } if (i == ECORE_INIT_MAX_POLL_COUNT) - DP_ERR(p_hwfn, - "Timeout when polling reg: 0x%08x [ Waiting-for: %08x" - " Got: %08x (comparsion %08x)]\n", + DP_ERR(p_hwfn, "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparison %08x)]\n", addr, OSAL_LE32_TO_CPU(cmd->expected_val), val, OSAL_LE32_TO_CPU(cmd->op_data)); } /* init_ops callbacks entry point */ -static void ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct init_callback_op *p_cmd) +static enum _ecore_status_t ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct init_callback_op *p_cmd) { - DP_NOTICE(p_hwfn, true, - "Currently init values have no need of callbacks\n"); + enum _ecore_status_t rc; + + switch (p_cmd->callback_id) { + case DMAE_READY_CB: + rc = ecore_dmae_sanity(p_hwfn, p_ptt, "engine_phase"); + break; + default: + DP_NOTICE(p_hwfn, false, "Unexpected init op callback ID %d\n", + p_cmd->callback_id); + return ECORE_INVAL; + } + + return rc; } static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn, @@ -444,17 +450,16 @@ static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn, INIT_IF_MODE_OP_CMD_OFFSET); } -static u32 ecore_init_cmd_phase(struct ecore_hwfn *p_hwfn, - struct init_if_phase_op *p_cmd, +static u32 ecore_init_cmd_phase(struct init_if_phase_op *p_cmd, u32 phase, u32 phase_id) { u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data); + u32 op_data = OSAL_LE32_TO_CPU(p_cmd->op_data); if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase && (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID || GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id))) - return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data), - INIT_IF_PHASE_OP_CMD_OFFSET); + return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET); else return 0; } @@ -500,8 +505,8 @@ enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn, modes); break; case INIT_OP_IF_PHASE: - cmd_num += ecore_init_cmd_phase(p_hwfn, &cmd->if_phase, - phase, phase_id); + cmd_num += ecore_init_cmd_phase(&cmd->if_phase, phase, + phase_id); b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE); break; case INIT_OP_DELAY: @@ -512,7 +517,7 @@ enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn, break; case INIT_OP_CALLBACK: - ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback); + rc = ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback); break; } @@ -573,7 +578,11 @@ void ecore_gtt_init(struct ecore_hwfn *p_hwfn, } enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev, - const u8 *data) +#ifdef CONFIG_ECORE_BINARY_FW + const u8 *fw_data) +#else + const u8 OSAL_UNUSED * fw_data) +#endif { struct ecore_fw_data *fw = p_dev->fw_data; @@ -581,24 +590,24 @@ enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev, struct bin_buffer_hdr *buf_hdr; u32 offset, len; - if (!data) { + if (!fw_data) { DP_NOTICE(p_dev, true, "Invalid fw data\n"); return ECORE_INVAL; } - buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data; + buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)fw_data; offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset; - fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset)); + fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(fw_data + offset)); offset = buf_hdr[BIN_BUF_INIT_CMD].offset; - fw->init_ops = (union init_op *)((uintptr_t)(data + offset)); + fw->init_ops = (union init_op *)((uintptr_t)(fw_data + offset)); offset = buf_hdr[BIN_BUF_INIT_VAL].offset; - fw->arr_data = (u32 *)((uintptr_t)(data + offset)); + fw->arr_data = (u32 *)((uintptr_t)(fw_data + offset)); offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset; - fw->modes_tree_buf = (u8 *)((uintptr_t)(data + offset)); + fw->modes_tree_buf = (u8 *)((uintptr_t)(fw_data + offset)); len = buf_hdr[BIN_BUF_INIT_CMD].length; fw->init_ops_size = len / sizeof(struct init_raw_op); #else