X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fecore_init_ops.h;h=de7846d4654bc3fa0c69b5eae1d8580bea92b463;hb=4182ee7f0239563916b1f730d5a58f534769ee5e;hp=8a6fce417b2343f49644d81336cf36b5f7393747;hpb=ec94dbc573625119a9ef101a07cd3773c32d8d96;p=dpdk.git

diff --git a/drivers/net/qede/base/ecore_init_ops.h b/drivers/net/qede/base/ecore_init_ops.h
index 8a6fce417b..de7846d465 100644
--- a/drivers/net/qede/base/ecore_init_ops.h
+++ b/drivers/net/qede/base/ecore_init_ops.h
@@ -1,9 +1,7 @@
-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 #ifndef __ECORE_INIT_OPS__
@@ -32,7 +30,9 @@ void ecore_init_iro_array(struct ecore_dev *p_dev);
  */
 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
 				    struct ecore_ptt *p_ptt,
-				    int phase, int phase_id, int modes);
+				    int               phase,
+				    int               phase_id,
+				    int               modes);
 
 /**
  * @brief ecore_init_hwfn_allocate - Allocate RT array, Store 'values' ptrs.
@@ -52,6 +52,7 @@ enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn);
  */
 void ecore_init_free(struct ecore_hwfn *p_hwfn);
 
+
 /**
  * @brief ecore_init_clear_rt_data - Clears the runtime init array.
  *
@@ -68,7 +69,9 @@ void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn);
  * @param rt_offset
  * @param val
  */
-void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val);
+void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn,
+			     u32               rt_offset,
+			     u32               val);
 
 #define STORE_RT_REG(hwfn, offset, val)				\
 	ecore_init_store_rt_reg(hwfn, offset, val)
@@ -87,11 +90,14 @@ void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val);
 */
 
 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
-			     u32 rt_offset, u32 *val, osal_size_t size);
+			     u32               rt_offset,
+			     u32               *val,
+			     osal_size_t       size);
 
 #define STORE_RT_REG_AGG(hwfn, offset, val)			\
 	ecore_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val))
 
+
 /**
  * @brief
  *      Initialize GTT global windows and set admin window
@@ -99,5 +105,6 @@ void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
  *
  * @param p_hwfn
  */
-void ecore_gtt_init(struct ecore_hwfn *p_hwfn);
+void ecore_gtt_init(struct ecore_hwfn *p_hwfn,
+		    struct ecore_ptt *p_ptt);
 #endif /* __ECORE_INIT_OPS__ */