X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fecore_l2.c;h=8b9817eb2879089ee685a2bbc1c0af7a062861ce;hb=45a49cc7e7a589d268e362ee275c399a6640708a;hp=d71f4616c3388f1acbd41fd179e7a71294b75414;hpb=3126df2237c2ef0e934d4b691ccaddb3ebebf575;p=dpdk.git diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index d71f4616c3..8b9817eb28 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -608,6 +608,9 @@ ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn, SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, !!(accept_filter & ECORE_ACCEPT_BCAST)); + SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI, + !!(accept_filter & ECORE_ACCEPT_ANY_VNI)); + p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state); DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n", @@ -783,6 +786,11 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn, return rc; } + if (p_params->update_ctl_frame_check) { + p_cmn->ctl_frame_mac_check_en = p_params->mac_chk_en; + p_cmn->ctl_frame_ethtype_check_en = p_params->ethtype_chk_en; + } + /* Update mcast bins for VFs, PF doesn't use this functionality */ ecore_sp_update_mcast_bin(p_ramrod, p_params); @@ -2084,6 +2092,24 @@ void ecore_reset_vport_stats(struct ecore_dev *p_dev) } } +static enum gft_profile_type +ecore_arfs_mode_to_hsi(enum ecore_filter_config_mode mode) +{ + if (mode == ECORE_FILTER_CONFIG_MODE_5_TUPLE) + return GFT_PROFILE_TYPE_4_TUPLE; + + if (mode == ECORE_FILTER_CONFIG_MODE_IP_DEST) + return GFT_PROFILE_TYPE_IP_DST_ADDR; + + if (mode == ECORE_FILTER_CONFIG_MODE_TUNN_TYPE) + return GFT_PROFILE_TYPE_TUNNEL_TYPE; + + if (mode == ECORE_FILTER_CONFIG_MODE_IP_SRC) + return GFT_PROFILE_TYPE_IP_SRC_ADDR; + + return GFT_PROFILE_TYPE_L4_DST_PORT; +} + void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct ecore_arfs_config_params *p_cfg_params) @@ -2091,13 +2117,13 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn, if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits)) return; - if (p_cfg_params->arfs_enable) { + if (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) { ecore_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_cfg_params->tcp, p_cfg_params->udp, p_cfg_params->ipv4, p_cfg_params->ipv6, - GFT_PROFILE_TYPE_4_TUPLE); + ecore_arfs_mode_to_hsi(p_cfg_params->mode)); DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n", p_cfg_params->tcp ? "Enable" : "Disable", @@ -2107,8 +2133,8 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn, } else { ecore_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); } - DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n", - p_cfg_params->arfs_enable ? "Enable" : "Disable"); + DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %d\n", + (int)p_cfg_params->mode); } enum _ecore_status_t @@ -2179,10 +2205,10 @@ ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn, return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); } -int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct ecore_queue_cid *p_cid, - u16 *p_rx_coal) +enum _ecore_status_t ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct ecore_queue_cid *p_cid, + u16 *p_rx_coal) { u32 coalesce, address, is_valid; struct cau_sb_entry sb_entry; @@ -2191,7 +2217,8 @@ int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn, rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + p_cid->sb_igu_id * sizeof(u64), - (u64)(osal_uintptr_t)&sb_entry, 2, 0); + (u64)(osal_uintptr_t)&sb_entry, 2, + OSAL_NULL /* default parameters */); if (rc != ECORE_SUCCESS) { DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); return rc; @@ -2213,10 +2240,10 @@ int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; } -int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct ecore_queue_cid *p_cid, - u16 *p_tx_coal) +enum _ecore_status_t ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct ecore_queue_cid *p_cid, + u16 *p_tx_coal) { u32 coalesce, address, is_valid; struct cau_sb_entry sb_entry; @@ -2225,7 +2252,8 @@ int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn, rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + p_cid->sb_igu_id * sizeof(u64), - (u64)(osal_uintptr_t)&sb_entry, 2, 0); + (u64)(osal_uintptr_t)&sb_entry, 2, + OSAL_NULL /* default parameters */); if (rc != ECORE_SUCCESS) { DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); return rc; @@ -2302,3 +2330,55 @@ ecore_eth_tx_queue_maxrate(struct ecore_hwfn *p_hwfn, return ecore_init_vport_rl(p_hwfn, p_ptt, vport, rate, p_link->speed); } + +#define RSS_TSTORM_UPDATE_STATUS_MAX_POLL_COUNT 100 +#define RSS_TSTORM_UPDATE_STATUS_POLL_PERIOD_US 1 + +enum _ecore_status_t +ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn, + u8 vport_id, + u8 ind_table_index, + u16 ind_table_value) +{ + struct eth_tstorm_rss_update_data update_data = { 0 }; + void OSAL_IOMEM *addr = OSAL_NULL; + enum _ecore_status_t rc; + u8 abs_vport_id; + u32 cnt = 0; + + OSAL_BUILD_BUG_ON(sizeof(update_data) != sizeof(u64)); + + rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id); + if (rc != ECORE_SUCCESS) + return rc; + + addr = (u8 OSAL_IOMEM *)p_hwfn->regview + + GTT_BAR0_MAP_REG_TSDM_RAM + + TSTORM_ETH_RSS_UPDATE_OFFSET(p_hwfn->rel_pf_id); + + *(u64 *)(&update_data) = DIRECT_REG_RD64(p_hwfn, addr); + + for (cnt = 0; update_data.valid && + cnt < RSS_TSTORM_UPDATE_STATUS_MAX_POLL_COUNT; cnt++) { + OSAL_UDELAY(RSS_TSTORM_UPDATE_STATUS_POLL_PERIOD_US); + *(u64 *)(&update_data) = DIRECT_REG_RD64(p_hwfn, addr); + } + + if (update_data.valid) { + DP_NOTICE(p_hwfn, true, + "rss update valid status is not clear! valid=0x%x vport id=%d ind_Table_idx=%d ind_table_value=%d.\n", + update_data.valid, vport_id, ind_table_index, + ind_table_value); + + return ECORE_AGAIN; + } + + update_data.valid = 1; + update_data.ind_table_index = ind_table_index; + update_data.ind_table_value = ind_table_value; + update_data.vport_id = abs_vport_id; + + DIRECT_REG_WR64(p_hwfn, addr, *(u64 *)(&update_data)); + + return ECORE_SUCCESS; +}