X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Freg_addr.h;h=91d889dc86d89246d730d7b7ebe0359d4ab58efd;hb=1e8d75d8059701fd15876416be06064735ec5e87;hp=60286545be9d83df1d635518a23ea55abf7b7405;hpb=2e2f392b249a81303c99584082a067a86591c3da;p=dpdk.git diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index 60286545be..91d889dc86 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -1,30 +1,20 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. - */ - -/* - * Copyright (c) 2016 QLogic Corporation. - * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 0 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ - 0xfff << 0) + 0xfffUL << 0) #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 12 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ - 0xfff << 12) + 0xfffUL << 12) #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 24 @@ -144,7 +134,7 @@ 0x009060UL #define MISCS_REG_CLK_100G_MODE \ 0x009070UL -#define MISCS_REG_RESET_PL_HV_2 \ +#define MISCS_REG_RESET_PL_HV_2_K2 \ 0x009150UL #define MSDM_REG_ENABLE_IN1 \ 0xfc0004UL @@ -332,6 +322,21 @@ 0x180820UL #define IGU_REG_ATTN_MSG_ADDR_H \ 0x180824UL +#define IGU_REG_LEADING_EDGE_LATCH \ + 0x18082cUL +#define IGU_REG_TRAILING_EDGE_LATCH \ + 0x180830UL +#define IGU_REG_ATTENTION_ACK_BITS \ + 0x180838UL +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \ + 0x181210UL +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \ + 0x18042cUL +#define IGU_REG_PBA_STS_PF_SIZE 5 +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL #define MISC_REG_AEU_GENERAL_ATTN_0 \ 0x008400UL #define CAU_REG_SB_ADDR_MEMORY \ @@ -361,9 +366,9 @@ #define IGU_REG_COMMAND_REG_CTRL \ 0x180848UL #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ - 0x1 << 1) + 0x1UL << 1) #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ - 0x1 << 0) + 0x1UL << 0) #define IGU_REG_MAPPING_MEMORY \ 0x184000UL #define MISCS_REG_GENERIC_POR_0 \ @@ -371,7 +376,7 @@ #define MCP_REG_NVM_CFG4 \ 0xe0642cUL #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ - 0x7 << 0) + 0x7UL << 0) #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 0 #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL @@ -404,7 +409,7 @@ #define XMAC_REG_TX_CTRL_LO 0x210020UL #define XMAC_REG_CTRL 0x210000UL #define XMAC_REG_RX_CTRL 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12) #define MISC_REG_CLK_100G_MODE 0x008c10UL #define MISC_REG_OPTE_MODE 0x008c0cUL #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL @@ -434,16 +439,16 @@ #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL -#define XMAC_REG_CTRL_TX_EN (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN (0x1UL << 1) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16 -#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0 -#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0 #define PSWRQ2_REG_ILT_MEMORY 0x260000UL #define QM_REG_WFQPFWEIGHT 0x2f4e80UL @@ -531,7 +536,7 @@ #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL #define MCP_REG_CPU_STATE 0xe05004UL #define MCP_REG_CPU_MODE 0xe05000UL -#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10) +#define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10) #define MCP_REG_CPU_EVENT_MASK 0xe05008UL #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL @@ -560,15 +565,15 @@ #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL #define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL -#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10) +#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10) #define DORQ_REG_DB_DROP_REASON 0x100a2cUL #define DORQ_REG_DB_DROP_DETAILS 0x100a24UL #define TM_REG_INT_STS_1 0x2c0190UL -#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6) -#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5) +#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6) +#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5) #define TM_REG_INT_MASK_1 0x2c0194UL -#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5) -#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6) +#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5) +#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6) #define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL #define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL @@ -1104,7 +1109,7 @@ #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL #define MISCS_REG_FUNCTION_HIDE 0x0096f0UL #define PCIE_REG_PRTY_MASK 0x0547b4UL -#define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL +#define PGLUE_B_REG_VF_BAR0_SIZE_K2 0x2aaeb4UL #define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL #define SEM_FAST_REG_INT_RAM_SIZE 20480 #define MCP_REG_SCRATCH_SIZE 57344 @@ -1131,12 +1136,12 @@ #define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL #define PRS_REG_SEARCH_FCOE 0x1f0408UL -#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL +#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL #define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL -#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL -#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL +#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL +#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL #define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL -#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL +#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL #define IGU_REG_WRITE_DONE_PENDING 0x180900UL #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL #define PRS_REG_MSG_INFO 0x1f0a1cUL @@ -1152,52 +1157,47 @@ #define CDU_REG_CCFC_CTX_VALID1 0x580404UL #define CDU_REG_TCFC_CTX_VALID0 0x580408UL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL -#define MISCS_REG_RESET_PL_HV_2_K2_E5 0x009150UL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL #define CNIG_REG_NW_PORT_MODE_BB 0x218200UL #define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL #define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL #define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL -#define NWM_REG_MAC0_K2_E5 0x800400UL -#define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0 -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1 -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3 -#define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL -#define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0 -#define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL -#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0 -#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL -#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0 -#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL -#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0 -#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL -#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16 -#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0 -#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL +#define NWM_REG_MAC0_K2 0x800400UL + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT 0 + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT 1 + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT 3 +#define ETH_MAC_REG_XIF_MODE_K2 0x000080UL + #define ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT 0 +#define ETH_MAC_REG_FRM_LENGTH_K2 0x000014UL + #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT 0 +#define ETH_MAC_REG_TX_IPG_LENGTH_K2 0x000044UL + #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT 0 +#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2 0x00001cUL + #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT 0 +#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2 0x000020UL + #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT 16 + #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT 0 + #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2 (0x1 << 6) + #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_SHIFT 6 +#define ETH_MAC_REG_COMMAND_CONFIG_K2 0x000008UL #define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL #define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL #define XMAC_REG_MODE_BB 0x210008UL #define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL #define XMAC_REG_TX_CTRL_LO_BB 0x210020UL #define XMAC_REG_CTRL_BB 0x210000UL -#define XMAC_REG_CTRL_TX_EN_BB (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN_BB (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1) #define XMAC_REG_RX_CTRL_BB 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12) -#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL -#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL -#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5 0x2aafa0UL -#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5 0x2aafa4UL #define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL #define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL #define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL #define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL -#define PCIE_REG_PRTY_MASK_K2_E5 0x0547b4UL -#define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL +#define PCIE_REG_PRTY_MASK_K2 0x0547b4UL #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL @@ -1205,3 +1205,43 @@ #define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL #define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL + +#define PSWRQ2_REG_WR_MBS0 0x240400UL +#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL +#define DORQ_REG_PF_USAGE_CNT 0x1009c0UL +#define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL +#define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL +#define DORQ_REG_INT_STS 0x100180UL + #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1) + #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2) + #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3) +#define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL +#define DORQ_REG_INT_STS_WR 0x100188UL +#define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL +#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL + #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) +#define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL +#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL + +#define RSS_REG_RSS_RAM_MASK 0x238c10UL + +#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL +#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL +#define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL +#define DORQ_REG_PF_PCP 0x1008c4UL +#define DORQ_REG_PF_EXT_VID 0x1008c8UL +#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL +#define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL +#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL +#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL 0x501b40UL + +#define MCP_REG_CACHE_PAGING_ENABLE 0xe06304UL +#define PSWRQ2_REG_RESET_STT 0x240008UL +#define PSWRQ2_REG_PRTY_STS_WR_H_0 0x240208UL +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 +#define PGLUE_B_REG_MASTER_DISCARD_NBLOCK 0x2aa58cUL +#define PGLUE_B_REG_PRTY_STS_WR_H_0 0x2a8208UL +#define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL +#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL +#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL