X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Freg_addr.h;h=91d889dc86d89246d730d7b7ebe0359d4ab58efd;hb=f159c61c35ebc6ff18d2c6c2cb07c177935a96e3;hp=be59f7738c0fc6be429e4f3d897bec2a825fc991;hpb=9aea0e7daffd26888252cbf77287def3a907e7af;p=dpdk.git diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index be59f7738c..91d889dc86 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -134,7 +134,7 @@ 0x009060UL #define MISCS_REG_CLK_100G_MODE \ 0x009070UL -#define MISCS_REG_RESET_PL_HV_2 \ +#define MISCS_REG_RESET_PL_HV_2_K2 \ 0x009150UL #define MSDM_REG_ENABLE_IN1 \ 0xfc0004UL @@ -1109,7 +1109,7 @@ #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL #define MISCS_REG_FUNCTION_HIDE 0x0096f0UL #define PCIE_REG_PRTY_MASK 0x0547b4UL -#define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL +#define PGLUE_B_REG_VF_BAR0_SIZE_K2 0x2aaeb4UL #define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL #define SEM_FAST_REG_INT_RAM_SIZE 20480 #define MCP_REG_SCRATCH_SIZE 57344 @@ -1136,12 +1136,12 @@ #define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL #define PRS_REG_SEARCH_FCOE 0x1f0408UL -#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL +#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL #define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL -#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL -#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL +#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL +#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL #define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL -#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL +#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL #define IGU_REG_WRITE_DONE_PENDING 0x180900UL #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL #define PRS_REG_MSG_INFO 0x1f0a1cUL @@ -1157,30 +1157,30 @@ #define CDU_REG_CCFC_CTX_VALID1 0x580404UL #define CDU_REG_TCFC_CTX_VALID0 0x580408UL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL -#define MISCS_REG_RESET_PL_HV_2_K2_E5 0x009150UL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL #define CNIG_REG_NW_PORT_MODE_BB 0x218200UL #define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL #define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL #define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL -#define NWM_REG_MAC0_K2_E5 0x800400UL -#define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0 -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1 -#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3 -#define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL -#define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0 -#define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL -#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0 -#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL -#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0 -#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL -#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0 -#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL -#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16 -#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0 -#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL +#define NWM_REG_MAC0_K2 0x800400UL + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT 0 + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT 1 + #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT 3 +#define ETH_MAC_REG_XIF_MODE_K2 0x000080UL + #define ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT 0 +#define ETH_MAC_REG_FRM_LENGTH_K2 0x000014UL + #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT 0 +#define ETH_MAC_REG_TX_IPG_LENGTH_K2 0x000044UL + #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT 0 +#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2 0x00001cUL + #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT 0 +#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2 0x000020UL + #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT 16 + #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT 0 + #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2 (0x1 << 6) + #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_SHIFT 6 +#define ETH_MAC_REG_COMMAND_CONFIG_K2 0x000008UL #define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL #define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL #define XMAC_REG_MODE_BB 0x210008UL @@ -1192,17 +1192,12 @@ #define XMAC_REG_RX_CTRL_BB 0x210030UL #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12) -#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL -#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL -#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5 0x2aafa0UL -#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5 0x2aafa4UL #define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL #define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL #define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL #define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL -#define PCIE_REG_PRTY_MASK_K2_E5 0x0547b4UL -#define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL +#define PCIE_REG_PRTY_MASK_K2 0x0547b4UL #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL @@ -1233,10 +1228,20 @@ #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL -#define DORQ_REG_PF_PCP_BB_K2 0x1008c4UL -#define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL +#define DORQ_REG_PF_PCP 0x1008c4UL +#define DORQ_REG_PF_EXT_VID 0x1008c8UL #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL #define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL 0x501b40UL + +#define MCP_REG_CACHE_PAGING_ENABLE 0xe06304UL +#define PSWRQ2_REG_RESET_STT 0x240008UL +#define PSWRQ2_REG_PRTY_STS_WR_H_0 0x240208UL +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 +#define PGLUE_B_REG_MASTER_DISCARD_NBLOCK 0x2aa58cUL +#define PGLUE_B_REG_PRTY_STS_WR_H_0 0x2a8208UL +#define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL +#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL +#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL