X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fqede_ethdev.c;h=fbad2a6e5f05cd085d48e337b787653e214c2c2c;hb=bed3b24c87cb7fb63d24d16d65b911fe14525d82;hp=f5309c5629f5230a2e855601fe36532be29b1e61;hpb=52d94b57e1c7d3859a4d6f318381983272df097a;p=dpdk.git diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index f5309c5629..fbad2a6e5f 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -279,14 +279,14 @@ static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) } static void -qede_interrupt_handler(struct rte_intr_handle *handle, void *param) +qede_interrupt_handler(void *param) { struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; struct qede_dev *qdev = eth_dev->data->dev_private; struct ecore_dev *edev = &qdev->edev; qede_interrupt_action(ECORE_LEADING_HWFN(edev)); - if (rte_intr_enable(handle)) + if (rte_intr_enable(eth_dev->intr_handle)) DP_ERR(edev, "rte_intr_enable failed\n"); } @@ -335,15 +335,15 @@ static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) /* ucast->assert_on_error = true; - For debug */ } -static void qede_set_cmn_tunn_param(struct ecore_tunn_update_params *params, - uint8_t clss, uint64_t mode, uint64_t mask) +static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn, + uint8_t clss, bool mode, bool mask) { - memset(params, 0, sizeof(struct ecore_tunn_update_params)); - params->tunn_mode = mode; - params->tunn_mode_update_mask = mask; - params->update_tx_pf_clss = 1; - params->update_rx_pf_clss = 1; - params->tunn_clss_vxlan = clss; + memset(p_tunn, 0, sizeof(struct ecore_tunnel_info)); + p_tunn->vxlan.b_update_mode = mode; + p_tunn->vxlan.b_mode_enabled = mask; + p_tunn->b_update_rx_cls = true; + p_tunn->b_update_tx_cls = true; + p_tunn->vxlan.tun_cls = clss; } static int @@ -485,7 +485,8 @@ qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, } } else { /* Unicast */ if (add) { - if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) { + if (qdev->num_uc_addr >= + qdev->dev_info.num_mac_filters) { DP_ERR(edev, "Ucast filter table limit exceeded," " Please enable promisc mode\n"); @@ -528,9 +529,9 @@ qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) PMD_INIT_FUNC_TRACE(edev); - if (index >= qdev->dev_info.num_mac_addrs) { + if (index >= qdev->dev_info.num_mac_filters) { DP_ERR(edev, "Index %u is above MAC filter limit %u\n", - index, qdev->dev_info.num_mac_addrs); + index, qdev->dev_info.num_mac_filters); return; } @@ -650,7 +651,7 @@ static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) qede_vlan_filter_set(eth_dev, 0, 1); } else { if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ - DP_NOTICE(edev, false, + DP_ERR(edev, " Please remove existing VLAN filters" " before disabling VLAN filtering\n"); /* Signal app that VLAN filtering is still @@ -684,7 +685,7 @@ static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, if (on) { if (qdev->configured_vlans == dev_info->num_vlan_filters) { - DP_INFO(edev, "Reached max VLAN filter limit" + DP_ERR(edev, "Reached max VLAN filter limit" " enabling accept_any_vlan\n"); qede_config_accept_any_vlan(qdev, true); return 0; @@ -768,7 +769,7 @@ static int qede_init_vport(struct qede_dev *qdev) int rc; start.remove_inner_vlan = 1; - start.gro_enable = 0; + start.enable_lro = qdev->enable_lro; start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD; start.vport_id = 0; start.drop_ttl0 = false; @@ -788,6 +789,54 @@ static int qede_init_vport(struct qede_dev *qdev) return 0; } +static void qede_prandom_bytes(uint32_t *buff) +{ + uint8_t i; + + srand((unsigned int)time(NULL)); + for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) + buff[i] = rand(); +} + +int qede_config_rss(struct rte_eth_dev *eth_dev) +{ + struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); + struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); + uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; + struct rte_eth_rss_reta_entry64 reta_conf[2]; + struct rte_eth_rss_conf rss_conf; + uint32_t i, id, pos, q; + + rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; + if (!rss_conf.rss_key) { + DP_INFO(edev, "Applying driver default key\n"); + rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); + qede_prandom_bytes(&def_rss_key[0]); + rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; + } + + /* Configure RSS hash */ + if (qede_rss_hash_update(eth_dev, &rss_conf)) + return -EINVAL; + + /* Configure default RETA */ + memset(reta_conf, 0, sizeof(reta_conf)); + for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) + reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; + + for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { + id = i / RTE_RETA_GROUP_SIZE; + pos = i % RTE_RETA_GROUP_SIZE; + q = i % QEDE_RSS_COUNT(qdev); + reta_conf[id].reta[pos] = q; + } + if (qede_rss_reta_update(eth_dev, &reta_conf[0], + ECORE_RSS_IND_TABLE_SIZE)) + return -EINVAL; + + return 0; +} + static int qede_dev_configure(struct rte_eth_dev *eth_dev) { struct qede_dev *qdev = eth_dev->data->dev_private; @@ -801,14 +850,13 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) if (edev->num_hwfns > 1) { if (eth_dev->data->nb_rx_queues < 2 || eth_dev->data->nb_tx_queues < 2) { - DP_NOTICE(edev, false, - "100G mode needs min. 2 RX/TX queues\n"); + DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); return -EINVAL; } if ((eth_dev->data->nb_rx_queues % 2 != 0) || (eth_dev->data->nb_tx_queues % 2 != 0)) { - DP_NOTICE(edev, false, + DP_ERR(edev, "100G mode needs even no. of RX/TX queues\n"); return -EINVAL; } @@ -818,11 +866,6 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) if (rxmode->enable_scatter == 1) eth_dev->data->scattered_rx = 1; - if (rxmode->enable_lro == 1) { - DP_INFO(edev, "LRO is not supported\n"); - return -EINVAL; - } - if (!rxmode->hw_strip_crc) DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); @@ -830,6 +873,13 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " "in hw\n"); + if (rxmode->enable_lro) { + qdev->enable_lro = true; + /* Enable scatter mode for LRO */ + if (!rxmode->enable_scatter) + eth_dev->data->scattered_rx = 1; + } + /* Check for the port restart case */ if (qdev->state != QEDE_DEV_INIT) { rc = qdev->ops->vport_stop(edev, 0); @@ -856,6 +906,23 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) if (rc != 0) return rc; + if (!(rxmode->mq_mode == ETH_MQ_RX_RSS || + rxmode->mq_mode == ETH_MQ_RX_NONE)) { + DP_ERR(edev, "Unsupported RSS mode\n"); + qdev->ops->vport_stop(edev, 0); + qede_dealloc_fp_resc(eth_dev); + return -EINVAL; + } + + /* Flow director mode check */ + rc = qede_check_fdir_support(eth_dev); + if (rc) { + qdev->ops->vport_stop(edev, 0); + qede_dealloc_fp_resc(eth_dev); + return -EINVAL; + } + SLIST_INIT(&qdev->fdir_info.fdir_list_head); + SLIST_INIT(&qdev->vlan_list_head); /* Add primary mac for PF */ @@ -880,13 +947,15 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev) static const struct rte_eth_desc_lim qede_rx_desc_lim = { .nb_max = NUM_RX_BDS_MAX, .nb_min = 128, - .nb_align = 128 /* lowest common multiple */ + .nb_align = 128 /* lowest common multiple */ }; static const struct rte_eth_desc_lim qede_tx_desc_lim = { .nb_max = NUM_TX_BDS_MAX, .nb_min = 256, - .nb_align = 256 + .nb_align = 256, + .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, + .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET }; static void @@ -901,33 +970,43 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev, PMD_INIT_FUNC_TRACE(edev); dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device); - dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU + - QEDE_ETH_OVERHEAD); + dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; dev_info->rx_desc_lim = qede_rx_desc_lim; dev_info->tx_desc_lim = qede_tx_desc_lim; - dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev); - dev_info->max_tx_queues = dev_info->max_rx_queues; - dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs; - if (IS_VF(edev)) - dev_info->max_vfs = 0; + + if (IS_PF(edev)) + dev_info->max_rx_queues = (uint16_t)RTE_MIN( + QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); else - dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev); + dev_info->max_rx_queues = (uint16_t)RTE_MIN( + QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); + dev_info->max_tx_queues = dev_info->max_rx_queues; + + dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; + dev_info->max_vfs = 0; dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; + dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; dev_info->default_txconf = (struct rte_eth_txconf) { .txq_flags = QEDE_TXQ_FLAGS, }; - dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | - DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM); - dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM); + dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | + DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_RX_OFFLOAD_TCP_LRO); + + dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | + DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM | + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_TX_OFFLOAD_TCP_TSO | + DEV_TX_OFFLOAD_VXLAN_TNL_TSO); memset(&link, 0, sizeof(struct qed_link_output)); qdev->ops->common->get_link(edev, &link); @@ -1050,6 +1129,8 @@ static void qede_dev_close(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(edev); + qede_fdir_dealloc_resc(eth_dev); + /* dev_stop() shall cleanup fp resources in hw but without releasing * dma memories and sw structures so that dev_start() can be called * by the app without reconfiguration. However, in dev_close() we @@ -1088,6 +1169,7 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) struct ecore_dev *edev = &qdev->edev; struct ecore_eth_stats stats; unsigned int i = 0, j = 0, qid; + unsigned int rxq_stat_cntrs, txq_stat_cntrs; struct qede_tx_queue *txq; qdev->ops->get_vport_stats(edev, &stats); @@ -1121,6 +1203,17 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) eth_stats->oerrors = stats.tx_err_drop_pkts; /* Queue stats */ + rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), + RTE_ETHDEV_QUEUE_STAT_CNTRS); + txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), + RTE_ETHDEV_QUEUE_STAT_CNTRS); + if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) || + (txq_stat_cntrs != QEDE_TSS_COUNT(qdev))) + DP_VERBOSE(edev, ECORE_MSG_DEBUG, + "Not all the queue stats will be displayed. Set" + " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" + " appropriately and retry.\n"); + for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { eth_stats->q_ipackets[i] = @@ -1139,7 +1232,11 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) rx_alloc_errors)); i++; } + if (i == rxq_stat_cntrs) + break; + } + for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) { txq = qdev->fp_array[(qid)].txqs[0]; eth_stats->q_opackets[j] = @@ -1149,13 +1246,17 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) xmit_pkts))); j++; } + if (j == txq_stat_cntrs) + break; } } static unsigned qede_get_xstats_count(struct qede_dev *qdev) { return RTE_DIM(qede_xstats_strings) + - (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev)); + (RTE_DIM(qede_rxq_xstats_strings) * + RTE_MIN(QEDE_RSS_COUNT(qdev), + RTE_ETHDEV_QUEUE_STAT_CNTRS)); } static int @@ -1165,6 +1266,7 @@ qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, struct qede_dev *qdev = dev->data->dev_private; const unsigned int stat_cnt = qede_get_xstats_count(qdev); unsigned int i, qid, stat_idx = 0; + unsigned int rxq_stat_cntrs; if (xstats_names != NULL) { for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { @@ -1175,7 +1277,9 @@ qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, stat_idx++; } - for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) { + rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), + RTE_ETHDEV_QUEUE_STAT_CNTRS); + for (qid = 0; qid < rxq_stat_cntrs; qid++) { for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { snprintf(xstats_names[stat_idx].name, sizeof(xstats_names[stat_idx].name), @@ -1199,6 +1303,7 @@ qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, struct ecore_eth_stats stats; const unsigned int num = qede_get_xstats_count(qdev); unsigned int i, qid, stat_idx = 0; + unsigned int rxq_stat_cntrs; if (n < num) return num; @@ -1212,7 +1317,9 @@ qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, stat_idx++; } - for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { + rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), + RTE_ETHDEV_QUEUE_STAT_CNTRS); + for (qid = 0; qid < rxq_stat_cntrs; qid++) { if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { xstats[stat_idx].value = *(uint64_t *)( @@ -1369,7 +1476,7 @@ qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) return NULL; } -void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) +static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) { *rss_caps = 0; *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; @@ -1378,76 +1485,112 @@ void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; + *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; + *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; } static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, struct rte_eth_rss_conf *rss_conf) { - struct qed_update_vport_params vport_update_params; - struct qede_dev *qdev = eth_dev->data->dev_private; - struct ecore_dev *edev = &qdev->edev; + struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); + struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); + struct ecore_sp_vport_update_params vport_update_params; + struct ecore_rss_params rss_params; + struct ecore_hwfn *p_hwfn; uint32_t *key = (uint32_t *)rss_conf->rss_key; uint64_t hf = rss_conf->rss_hf; - int i; + uint8_t len = rss_conf->rss_key_len; + uint8_t idx; + uint8_t i; + int rc; memset(&vport_update_params, 0, sizeof(vport_update_params)); + memset(&rss_params, 0, sizeof(rss_params)); + + DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", + (unsigned long)hf, len, key); if (hf != 0) { - /* Enable RSS */ - qede_init_rss_caps(&qdev->rss_params.rss_caps, hf); - memcpy(&vport_update_params.rss_params, &qdev->rss_params, - sizeof(vport_update_params.rss_params)); - if (key) - memcpy(qdev->rss_params.rss_key, rss_conf->rss_key, - rss_conf->rss_key_len); - vport_update_params.update_rss_flg = 1; - qdev->rss_enabled = 1; - } else { - /* Disable RSS */ - qdev->rss_enabled = 0; + /* Enabling RSS */ + DP_INFO(edev, "Enabling rss\n"); + + /* RSS caps */ + qede_init_rss_caps(&rss_params.rss_caps, hf); + rss_params.update_rss_capabilities = 1; + + /* RSS hash key */ + if (key) { + if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { + DP_ERR(edev, "RSS key length exceeds limit\n"); + return -EINVAL; + } + DP_INFO(edev, "Applying user supplied hash key\n"); + rss_params.update_rss_key = 1; + memcpy(&rss_params.rss_key, key, len); + } + rss_params.rss_enable = 1; } - /* If the mapping doesn't fit any supported, return */ - if (qdev->rss_params.rss_caps == 0 && hf != 0) - return -EINVAL; - - DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ? - "Enabling RSS" : "Disabling RSS"); - + rss_params.update_rss_config = 1; + /* tbl_size has to be set with capabilities */ + rss_params.rss_table_size_log = 7; vport_update_params.vport_id = 0; + /* pass the L2 handles instead of qids */ + for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { + idx = qdev->rss_ind_table[i]; + rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; + } + vport_update_params.rss_params = &rss_params; + + for_each_hwfn(edev, i) { + p_hwfn = &edev->hwfns[i]; + vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; + rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, + ECORE_SPQ_MODE_EBLOCK, NULL); + if (rc) { + DP_ERR(edev, "vport-update for RSS failed\n"); + return rc; + } + } + qdev->rss_enable = rss_params.rss_enable; + + /* Update local structure for hash query */ + qdev->rss_conf.rss_hf = hf; + qdev->rss_conf.rss_key_len = len; + if (qdev->rss_enable) { + if (qdev->rss_conf.rss_key == NULL) { + qdev->rss_conf.rss_key = (uint8_t *)malloc(len); + if (qdev->rss_conf.rss_key == NULL) { + DP_ERR(edev, "No memory to store RSS key\n"); + return -ENOMEM; + } + } + if (key && len) { + DP_INFO(edev, "Storing RSS key\n"); + memcpy(qdev->rss_conf.rss_key, key, len); + } + } else if (!qdev->rss_enable && len == 0) { + if (qdev->rss_conf.rss_key) { + free(qdev->rss_conf.rss_key); + qdev->rss_conf.rss_key = NULL; + DP_INFO(edev, "Free RSS key\n"); + } + } - return qdev->ops->vport_update(edev, &vport_update_params); + return 0; } -int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, +static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, struct rte_eth_rss_conf *rss_conf) { - struct qede_dev *qdev = eth_dev->data->dev_private; - uint64_t hf; - - if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key)) - return -EINVAL; + struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); - if (rss_conf->rss_key) - memcpy(rss_conf->rss_key, qdev->rss_params.rss_key, - sizeof(qdev->rss_params.rss_key)); - - hf = 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4) ? - ETH_RSS_IPV4 : 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? - ETH_RSS_IPV6 : 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? - ETH_RSS_IPV6_EX : 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ? - ETH_RSS_NONFRAG_IPV4_TCP : 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? - ETH_RSS_NONFRAG_IPV6_TCP : 0; - hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? - ETH_RSS_IPV6_TCP_EX : 0; - - rss_conf->rss_hf = hf; + rss_conf->rss_hf = qdev->rss_conf.rss_hf; + rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; + if (rss_conf->rss_key && qdev->rss_conf.rss_key) + memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, + rss_conf->rss_key_len); return 0; } @@ -1455,10 +1598,14 @@ static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) { - struct qed_update_vport_params vport_update_params; - struct qede_dev *qdev = eth_dev->data->dev_private; - struct ecore_dev *edev = &qdev->edev; + struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); + struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); + struct ecore_sp_vport_update_params vport_update_params; + struct ecore_rss_params params; + struct ecore_hwfn *p_hwfn; uint16_t i, idx, shift; + uint8_t entry; + int rc; if (reta_size > ETH_RSS_RETA_SIZE_128) { DP_ERR(edev, "reta_size %d is not supported by hardware\n", @@ -1467,42 +1614,67 @@ static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, } memset(&vport_update_params, 0, sizeof(vport_update_params)); - memcpy(&vport_update_params.rss_params, &qdev->rss_params, - sizeof(vport_update_params.rss_params)); + memset(¶ms, 0, sizeof(params)); for (i = 0; i < reta_size; i++) { idx = i / RTE_RETA_GROUP_SIZE; shift = i % RTE_RETA_GROUP_SIZE; if (reta_conf[idx].mask & (1ULL << shift)) { - uint8_t entry = reta_conf[idx].reta[shift]; - qdev->rss_params.rss_ind_table[i] = entry; + entry = reta_conf[idx].reta[shift]; + /* Pass rxq handles to ecore */ + params.rss_ind_table[i] = + qdev->fp_array[entry].rxq->handle; + /* Update the local copy for RETA query command */ + qdev->rss_ind_table[i] = entry; } } - vport_update_params.update_rss_flg = 1; + /* Fix up RETA for CMT mode device */ + if (edev->num_hwfns > 1) + qdev->rss_enable = qed_update_rss_parm_cmt(edev, + params.rss_ind_table[0]); + params.update_rss_ind_table = 1; + params.rss_table_size_log = 7; + params.update_rss_config = 1; vport_update_params.vport_id = 0; + /* Use the current value of rss_enable */ + params.rss_enable = qdev->rss_enable; + vport_update_params.rss_params = ¶ms; + + for_each_hwfn(edev, i) { + p_hwfn = &edev->hwfns[i]; + vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; + rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, + ECORE_SPQ_MODE_EBLOCK, NULL); + if (rc) { + DP_ERR(edev, "vport-update for RSS failed\n"); + return rc; + } + } - return qdev->ops->vport_update(edev, &vport_update_params); + return 0; } -int qede_rss_reta_query(struct rte_eth_dev *eth_dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size) +static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) { struct qede_dev *qdev = eth_dev->data->dev_private; + struct ecore_dev *edev = &qdev->edev; uint16_t i, idx, shift; + uint8_t entry; if (reta_size > ETH_RSS_RETA_SIZE_128) { - struct ecore_dev *edev = &qdev->edev; DP_ERR(edev, "reta_size %d is not supported\n", reta_size); + return -EINVAL; } for (i = 0; i < reta_size; i++) { idx = i / RTE_RETA_GROUP_SIZE; shift = i % RTE_RETA_GROUP_SIZE; if (reta_conf[idx].mask & (1ULL << shift)) { - uint8_t entry = qdev->rss_params.rss_ind_table[i]; + entry = qdev->rss_ind_table[i]; reta_conf[idx].reta[shift] = entry; } } @@ -1512,32 +1684,61 @@ int qede_rss_reta_query(struct rte_eth_dev *eth_dev, int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) { - uint32_t frame_size; - struct qede_dev *qdev = dev->data->dev_private; + struct qede_dev *qdev = QEDE_INIT_QDEV(dev); + struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); struct rte_eth_dev_info dev_info = {0}; + struct qede_fastpath *fp; + uint32_t frame_size; + uint16_t rx_buf_size; + uint16_t bufsz; + int i; + PMD_INIT_FUNC_TRACE(edev); qede_dev_info_get(dev, &dev_info); - - /* VLAN_TAG = 4 */ - frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4; - - if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) + frame_size = mtu + QEDE_ETH_OVERHEAD; + if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { + DP_ERR(edev, "MTU %u out of range\n", mtu); return -EINVAL; - + } if (!dev->data->scattered_rx && - frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) + frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { + DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", + dev->data->min_rx_buf_size); return -EINVAL; - + } + /* Temporarily replace I/O functions with dummy ones. It cannot + * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. + */ + dev->rx_pkt_burst = qede_rxtx_pkts_dummy; + dev->tx_pkt_burst = qede_rxtx_pkts_dummy; + qede_dev_stop(dev); + rte_delay_ms(1000); + qdev->mtu = mtu; + /* Fix up RX buf size for all queues of the port */ + for_each_queue(i) { + fp = &qdev->fp_array[i]; + if (fp->type & QEDE_FASTPATH_RX) { + bufsz = (uint16_t)rte_pktmbuf_data_room_size( + fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; + if (dev->data->scattered_rx) + rx_buf_size = bufsz + QEDE_ETH_OVERHEAD; + else + rx_buf_size = mtu + QEDE_ETH_OVERHEAD; + rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); + fp->rxq->rx_buf_size = rx_buf_size; + DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size); + } + } + qede_dev_start(dev); if (frame_size > ETHER_MAX_LEN) dev->data->dev_conf.rxmode.jumbo_frame = 1; else dev->data->dev_conf.rxmode.jumbo_frame = 0; - /* update max frame size */ dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; - qdev->mtu = mtu; - qede_dev_stop(dev); - qede_dev_start(dev); + /* Reassign back */ + dev->rx_pkt_burst = qede_recv_pkts; + dev->tx_pkt_burst = qede_xmit_pkts; return 0; } @@ -1549,24 +1750,24 @@ qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev, { struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); - struct ecore_tunn_update_params params; + struct ecore_tunnel_info tunn; /* @DPDK */ struct ecore_hwfn *p_hwfn; int rc, i; PMD_INIT_FUNC_TRACE(edev); - memset(¶ms, 0, sizeof(params)); + memset(&tunn, 0, sizeof(tunn)); if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) { - params.update_vxlan_udp_port = 1; - params.vxlan_udp_port = (add) ? tunnel_udp->udp_port : - QEDE_VXLAN_DEF_PORT; + tunn.vxlan_port.b_update_port = true; + tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port : + QEDE_VXLAN_DEF_PORT; for_each_hwfn(edev, i) { p_hwfn = &edev->hwfns[i]; - rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, ¶ms, + rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, ECORE_SPQ_MODE_CB, NULL); if (rc != ECORE_SUCCESS) { DP_ERR(edev, "Unable to config UDP port %u\n", - params.vxlan_udp_port); + tunn.vxlan_port.port); return rc; } } @@ -1659,7 +1860,7 @@ static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, { struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); - struct ecore_tunn_update_params params; + struct ecore_tunnel_info tunn; struct ecore_hwfn *p_hwfn; enum ecore_filter_ucast_type type; enum ecore_tunn_clss clss; @@ -1708,16 +1909,14 @@ static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, qdev->vxlan_filter_type = filter_type; DP_INFO(edev, "Enabling VXLAN tunneling\n"); - qede_set_cmn_tunn_param(¶ms, clss, - (1 << ECORE_MODE_VXLAN_TUNN), - (1 << ECORE_MODE_VXLAN_TUNN)); + qede_set_cmn_tunn_param(&tunn, clss, true, true); for_each_hwfn(edev, i) { p_hwfn = &edev->hwfns[i]; rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, - ¶ms, ECORE_SPQ_MODE_CB, NULL); + &tunn, ECORE_SPQ_MODE_CB, NULL); if (rc != ECORE_SUCCESS) { DP_ERR(edev, "Failed to update tunn_clss %u\n", - params.tunn_clss_vxlan); + tunn.vxlan.tun_cls); } } qdev->num_tunn_filters++; /* Filter added successfully */ @@ -1744,16 +1943,15 @@ static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, DP_INFO(edev, "Disabling VXLAN tunneling\n"); /* Use 0 as tunnel mode */ - qede_set_cmn_tunn_param(¶ms, clss, 0, - (1 << ECORE_MODE_VXLAN_TUNN)); + qede_set_cmn_tunn_param(&tunn, clss, false, true); for_each_hwfn(edev, i) { p_hwfn = &edev->hwfns[i]; - rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, - ¶ms, ECORE_SPQ_MODE_CB, NULL); + rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, + ECORE_SPQ_MODE_CB, NULL); if (rc != ECORE_SUCCESS) { DP_ERR(edev, "Failed to update tunn_clss %u\n", - params.tunn_clss_vxlan); + tunn.vxlan.tun_cls); break; } } @@ -1802,11 +2000,13 @@ int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, } break; case RTE_ETH_FILTER_FDIR: + return qede_fdir_filter_conf(eth_dev, filter_op, arg); + case RTE_ETH_FILTER_NTUPLE: + return qede_ntuple_filter_conf(eth_dev, filter_op, arg); case RTE_ETH_FILTER_MACVLAN: case RTE_ETH_FILTER_ETHERTYPE: case RTE_ETH_FILTER_FLEXIBLE: case RTE_ETH_FILTER_SYN: - case RTE_ETH_FILTER_NTUPLE: case RTE_ETH_FILTER_HASH: case RTE_ETH_FILTER_L2_TUNNEL: case RTE_ETH_FILTER_MAX: @@ -1894,9 +2094,10 @@ static const struct eth_dev_ops qede_eth_vf_dev_ops = { static void qede_update_pf_params(struct ecore_dev *edev) { struct ecore_pf_params pf_params; - /* 32 rx + 32 tx */ + memset(&pf_params, 0, sizeof(struct ecore_pf_params)); - pf_params.eth_pf_params.num_cons = 64; + pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; + pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; qed_ops->common->update_pf_params(edev, &pf_params); } @@ -1933,6 +2134,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) eth_dev->rx_pkt_burst = qede_recv_pkts; eth_dev->tx_pkt_burst = qede_xmit_pkts; + eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; if (rte_eal_process_type() != RTE_PROC_PRIMARY) { DP_NOTICE(edev, false, @@ -1942,6 +2144,10 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) rte_eth_copy_pci_info(eth_dev, pci_dev); + /* @DPDK */ + edev->vendor_id = pci_dev->id.vendor_id; + edev->device_id = pci_dev->id.device_id; + qed_ops = qed_get_eth_ops(); if (!qed_ops) { DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); @@ -2013,20 +2219,20 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) qede_alloc_etherdev(adapter, &dev_info); - adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION); + adapter->ops->common->set_name(edev, edev->name); if (!is_vf) - adapter->dev_info.num_mac_addrs = + adapter->dev_info.num_mac_filters = (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), ECORE_MAC); else ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), - &adapter->dev_info.num_mac_addrs); + (uint32_t *)&adapter->dev_info.num_mac_filters); /* Allocate memory for storing MAC addr */ eth_dev->data->mac_addrs = rte_zmalloc(edev->name, (ETHER_ADDR_LEN * - adapter->dev_info.num_mac_addrs), + adapter->dev_info.num_mac_filters), RTE_CACHE_LINE_SIZE); if (eth_dev->data->mac_addrs == NULL) { @@ -2127,66 +2333,96 @@ static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) return qede_dev_common_uninit(eth_dev); } -static struct rte_pci_id pci_id_qedevf_map[] = { +static const struct rte_pci_id pci_id_qedevf_map[] = { #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) { - QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF) + QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) }, { - QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV) + QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) + }, + { + QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) }, {.vendor_id = 0,} }; -static struct rte_pci_id pci_id_qede_map[] = { +static const struct rte_pci_id pci_id_qede_map[] = { #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) { - QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E) + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) }, { - QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S) + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) }, { - QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40) + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) }, { - QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25) + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) }, { - QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100) + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) + }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) + }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) + }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) + }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) + }, + { + QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) }, {.vendor_id = 0,} }; -static struct eth_driver rte_qedevf_pmd = { - .pci_drv = { - .id_table = pci_id_qedevf_map, - .drv_flags = - RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, - .probe = rte_eth_dev_pci_probe, - .remove = rte_eth_dev_pci_remove, - }, - .eth_dev_init = qedevf_eth_dev_init, - .eth_dev_uninit = qedevf_eth_dev_uninit, - .dev_private_size = sizeof(struct qede_dev), +static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct qede_dev), qedevf_eth_dev_init); +} + +static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); +} + +static struct rte_pci_driver rte_qedevf_pmd = { + .id_table = pci_id_qedevf_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = qedevf_eth_dev_pci_probe, + .remove = qedevf_eth_dev_pci_remove, }; -static struct eth_driver rte_qede_pmd = { - .pci_drv = { - .id_table = pci_id_qede_map, - .drv_flags = - RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, - .probe = rte_eth_dev_pci_probe, - .remove = rte_eth_dev_pci_remove, - }, - .eth_dev_init = qede_eth_dev_init, - .eth_dev_uninit = qede_eth_dev_uninit, - .dev_private_size = sizeof(struct qede_dev), +static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct qede_dev), qede_eth_dev_init); +} + +static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); +} + +static struct rte_pci_driver rte_qede_pmd = { + .id_table = pci_id_qede_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = qede_eth_dev_pci_probe, + .remove = qede_eth_dev_pci_remove, }; -RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv); +RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio"); -RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv); +RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");