X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fqede_if.h;h=405c525ec14102168a39a80f76019e4a513f1996;hb=2f6fec53909b90fa653b5d6ace0c4aeb4cce25b7;hp=2d38b1bf59b5973117accbe1bd4765071bbd7a39;hpb=7eca78cefde830270e18d47abe0cd52f7afff9a4;p=dpdk.git diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h index 2d38b1bf59..405c525ec1 100644 --- a/drivers/net/qede/qede_if.h +++ b/drivers/net/qede/qede_if.h @@ -30,11 +30,24 @@ struct qed_dev_info { /* MFW version */ uint32_t mfw_rev; +#define QED_MFW_VERSION_0_MASK 0x000000FF +#define QED_MFW_VERSION_0_OFFSET 0 +#define QED_MFW_VERSION_1_MASK 0x0000FF00 +#define QED_MFW_VERSION_1_OFFSET 8 +#define QED_MFW_VERSION_2_MASK 0x00FF0000 +#define QED_MFW_VERSION_2_OFFSET 16 +#define QED_MFW_VERSION_3_MASK 0xFF000000 +#define QED_MFW_VERSION_3_OFFSET 24 uint32_t flash_size; uint8_t mf_mode; bool tx_switching; - /* To be added... */ + u16 mtu; + + /* Out param for qede */ + bool vxlan_enable; + bool gre_enable; + bool geneve_enable; }; enum qed_sb_type { @@ -70,6 +83,7 @@ struct qed_link_output { uint32_t advertised_caps; /* In ADVERTISED defs */ uint32_t lp_caps; /* In ADVERTISED defs */ uint32_t speed; /* In Mb/s */ + uint32_t adv_speed; /* Speed mask */ uint8_t duplex; /* In DUPLEX defs */ uint8_t port; /* In PORT defs */ bool autoneg; @@ -87,8 +101,45 @@ struct qed_slowpath_params { #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ +struct qed_eth_tlvs { + u16 feat_flags; + u8 mac[3][ETH_ALEN]; + u16 lso_maxoff; + u16 lso_minseg; + bool prom_mode; + u16 num_txqs; + u16 num_rxqs; + u16 num_netqs; + u16 flex_vlan; + u32 tcp4_offloads; + u32 tcp6_offloads; + u16 tx_avg_qdepth; + u16 rx_avg_qdepth; + u8 txqs_empty; + u8 rxqs_empty; + u8 num_txqs_full; + u8 num_rxqs_full; +}; + +struct qed_tunn_update_params { + unsigned long tunn_mode_update_mask; + unsigned long tunn_mode; + u16 vxlan_udp_port; + u16 geneve_udp_port; + u8 update_rx_pf_clss; + u8 update_tx_pf_clss; + u8 update_vxlan_udp_port; + u8 update_geneve_udp_port; + u8 tunn_clss_vxlan; + u8 tunn_clss_l2geneve; + u8 tunn_clss_ipgeneve; + u8 tunn_clss_l2gre; + u8 tunn_clss_ipgre; +}; + struct qed_common_cb_ops { void (*link_update)(void *dev, struct qed_link_output *link); + void (*get_tlv_data)(void *dev, struct qed_eth_tlvs *data); }; struct qed_selftest_ops { @@ -107,16 +158,17 @@ struct qed_common_ops { struct rte_pci_device *pci_dev, enum qed_protocol protocol, uint32_t dp_module, uint8_t dp_level, bool is_vf); - void (*set_id)(struct ecore_dev *edev, - char name[], const char ver_str[]); - enum _ecore_status_t (*chain_alloc)(struct ecore_dev *edev, - enum ecore_chain_use_mode - intended_use, - enum ecore_chain_mode mode, - enum ecore_chain_cnt_type cnt_type, - uint32_t num_elems, - osal_size_t elem_size, - struct ecore_chain *p_chain); + void (*set_name)(struct ecore_dev *edev, char name[]); + enum _ecore_status_t + (*chain_alloc)(struct ecore_dev *edev, + enum ecore_chain_use_mode + intended_use, + enum ecore_chain_mode mode, + enum ecore_chain_cnt_type cnt_type, + uint32_t num_elems, + osal_size_t elem_size, + struct ecore_chain *p_chain, + struct ecore_chain_ext_pbl *ext_pbl); void (*chain_free)(struct ecore_dev *edev, struct ecore_chain *p_chain); @@ -146,9 +198,16 @@ struct qed_common_ops { dma_addr_t sb_phy_addr, uint16_t sb_id, enum qed_sb_type type); + int (*get_sb_info)(struct ecore_dev *edev, + struct ecore_sb_info *sb, u16 qid, + struct ecore_sb_info_dbg *sb_dbg); + bool (*can_link_change)(struct ecore_dev *edev); + void (*update_msglvl)(struct ecore_dev *edev, uint32_t dp_module, uint8_t dp_level); + + int (*send_drv_state)(struct ecore_dev *edev, bool active); }; #endif /* _QEDE_IF_H */