X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fqede_main.c;h=caa9d1d4f6155c5348d5d3b896f3a9e93d14b37f;hb=9d2cca549474061620a291aaf67ca87e43f26140;hp=c9caec64508560973f0ca291f258f19f184a637e;hpb=3b307c55f2ac7f3f4146bd0dc9b474e1f3076f97;p=dpdk.git diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index c9caec6450..caa9d1d4f6 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -5,11 +5,12 @@ */ #include -#include #include #include #include "qede_ethdev.h" +/* ######### DEBUG ###########*/ +#include "qede_debug.h" /* Alarm timeout. */ #define QEDE_ALARM_TIMEOUT_US 100000 @@ -18,7 +19,7 @@ char qede_fw_file[PATH_MAX]; static const char * const QEDE_DEFAULT_FIRMWARE = - "/lib/firmware/qed/qed_init_values-8.40.25.0.bin"; + "/lib/firmware/qed/qed_init_values-8.40.33.0.bin"; static void qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params) @@ -36,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev) edev->regview = pci_dev->mem_resource[0].addr; edev->doorbells = pci_dev->mem_resource[2].addr; edev->db_size = pci_dev->mem_resource[2].len; + edev->pci_dev = pci_dev; } static int @@ -56,13 +58,17 @@ qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev, qed_init_pci(edev, pci_dev); memset(&hw_prepare_params, 0, sizeof(hw_prepare_params)); + + if (is_vf) + hw_prepare_params.acquire_retry_cnt = ECORE_VF_ACQUIRE_THRESH; + hw_prepare_params.personality = ECORE_PCI_ETH; hw_prepare_params.drv_resc_alloc = false; hw_prepare_params.chk_reg_fifo = false; hw_prepare_params.initiate_pf_flr = true; hw_prepare_params.allow_mdump = false; hw_prepare_params.b_en_pacing = false; - hw_prepare_params.epoch = (u32)time(NULL); + hw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev)); rc = ecore_hw_prepare(edev, &hw_prepare_params); if (rc) { DP_ERR(edev, "hw prepare failed\n"); @@ -215,7 +221,9 @@ static void qed_stop_iov_task(struct ecore_dev *edev) for_each_hwfn(edev, i) { p_hwfn = &edev->hwfns[i]; - if (!IS_PF(edev)) + if (IS_PF(edev)) + rte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn); + else rte_eal_alarm_cancel(qede_vf_task, p_hwfn); } } @@ -273,10 +281,15 @@ static int qed_slowpath_start(struct ecore_dev *edev, qed_start_iov_task(edev); #ifdef CONFIG_ECORE_BINARY_FW - if (IS_PF(edev)) + if (IS_PF(edev)) { data = (const uint8_t *)edev->firmware + sizeof(u32); + + /* ############### DEBUG ################## */ + qed_dbg_pf_init(edev); + } #endif + /* Start the slowpath */ memset(&hw_init_params, 0, sizeof(hw_init_params)); hw_init_params.b_hw_start = true; @@ -378,8 +391,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info) if (IS_PF(edev)) { dev_info->b_inter_pf_switch = - OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits); - if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits)) + OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits); + if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits)) dev_info->b_arfs_capable = true; dev_info->tx_switching = false; @@ -390,6 +403,9 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info) ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt, &dev_info->mfw_rev, NULL); + ecore_mcp_get_mbi_ver(ECORE_LEADING_HWFN(edev), ptt, + &dev_info->mbi_version); + ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt, &dev_info->flash_size); @@ -571,13 +587,12 @@ qed_get_current_link(struct ecore_dev *edev, struct qed_link_output *if_link) hwfn = &edev->hwfns[0]; if (IS_PF(edev)) { ptt = ecore_ptt_acquire(hwfn); - if (!ptt) - DP_NOTICE(hwfn, true, "Failed to fill link; No PTT\n"); - + if (ptt) { qed_fill_link(hwfn, ptt, if_link); - - if (ptt) ecore_ptt_release(hwfn, ptt); + } else { + DP_NOTICE(hwfn, true, "Failed to fill link; No PTT\n"); + } } else { qed_fill_link(hwfn, NULL, if_link); } @@ -635,10 +650,13 @@ void qed_link_update(struct ecore_hwfn *hwfn) struct ecore_dev *edev = hwfn->p_dev; struct qede_dev *qdev = (struct qede_dev *)edev; struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev; + int rc; + + rc = qede_link_update(dev, 0); + qed_inform_vf_link_state(hwfn); - if (!qede_link_update(dev, 0)) - _rte_eth_dev_callback_process(dev, - RTE_ETH_EVENT_INTR_LSC, NULL); + if (!rc) + rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); } static int qed_drain(struct ecore_dev *edev) @@ -773,11 +791,42 @@ const struct qed_common_ops qed_common_ops_pass = { INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop), INIT_STRUCT_FIELD(remove, &qed_remove), INIT_STRUCT_FIELD(send_drv_state, &qed_send_drv_state), + /* ############### DEBUG ####################*/ + + INIT_STRUCT_FIELD(dbg_get_debug_engine, &qed_get_debug_engine), + INIT_STRUCT_FIELD(dbg_set_debug_engine, &qed_set_debug_engine), + + INIT_STRUCT_FIELD(dbg_protection_override, + &qed_dbg_protection_override), + INIT_STRUCT_FIELD(dbg_protection_override_size, + &qed_dbg_protection_override_size), + + INIT_STRUCT_FIELD(dbg_grc, &qed_dbg_grc), + INIT_STRUCT_FIELD(dbg_grc_size, &qed_dbg_grc_size), + + INIT_STRUCT_FIELD(dbg_idle_chk, &qed_dbg_idle_chk), + INIT_STRUCT_FIELD(dbg_idle_chk_size, &qed_dbg_idle_chk_size), + + INIT_STRUCT_FIELD(dbg_mcp_trace, &qed_dbg_mcp_trace), + INIT_STRUCT_FIELD(dbg_mcp_trace_size, &qed_dbg_mcp_trace_size), + + INIT_STRUCT_FIELD(dbg_fw_asserts, &qed_dbg_fw_asserts), + INIT_STRUCT_FIELD(dbg_fw_asserts_size, &qed_dbg_fw_asserts_size), + + INIT_STRUCT_FIELD(dbg_ilt, &qed_dbg_ilt), + INIT_STRUCT_FIELD(dbg_ilt_size, &qed_dbg_ilt_size), + + INIT_STRUCT_FIELD(dbg_reg_fifo_size, &qed_dbg_reg_fifo_size), + INIT_STRUCT_FIELD(dbg_reg_fifo, &qed_dbg_reg_fifo), + + INIT_STRUCT_FIELD(dbg_igu_fifo_size, &qed_dbg_igu_fifo_size), + INIT_STRUCT_FIELD(dbg_igu_fifo, &qed_dbg_igu_fifo), }; const struct qed_eth_ops qed_eth_ops_pass = { INIT_STRUCT_FIELD(common, &qed_common_ops_pass), INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info), + INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure), }; const struct qed_eth_ops *qed_get_eth_ops(void)