X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fqede_rxtx.c;h=184f0e13f2d30d453ef101e8543d98fceb1af9a2;hb=ecad87d22383e4cfe4b6838342c2de6e18b05c28;hp=665a07b8bbea03f0b06c92a71c645d01edcfea92;hpb=a39001d90dbd212e178619276183dc02b936c70c;p=dpdk.git diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c index 665a07b8bb..184f0e13f2 100644 --- a/drivers/net/qede/qede_rxtx.c +++ b/drivers/net/qede/qede_rxtx.c @@ -28,7 +28,7 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq) } rxq->sw_rx_ring[idx].mbuf = new_mb; rxq->sw_rx_ring[idx].page_offset = 0; - mapping = rte_mbuf_data_dma_addr_default(new_mb); + mapping = rte_mbuf_data_iova_default(new_mb); /* Advance PROD and get BD pointer */ rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring); rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping)); @@ -82,6 +82,7 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, rxq->nb_rx_desc = nb_desc; rxq->queue_id = queue_idx; rxq->port_id = dev->data->port_id; + max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len; qdev->mtu = max_rx_pkt_len; @@ -94,6 +95,7 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, dev->data->scattered_rx = 1; } } + if (dev->data->scattered_rx) rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD; else @@ -109,9 +111,8 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size, RTE_CACHE_LINE_SIZE, socket_id); if (!rxq->sw_rx_ring) { - DP_NOTICE(edev, false, - "Unable to alloc memory for sw_rx_ring on socket %u\n", - socket_id); + DP_ERR(edev, "Memory allocation fails for sw_rx_ring on" + " socket %u\n", socket_id); rte_free(rxq); return -ENOMEM; } @@ -127,9 +128,8 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, NULL); if (rc != ECORE_SUCCESS) { - DP_NOTICE(edev, false, - "Unable to alloc memory for rxbd ring on socket %u\n", - socket_id); + DP_ERR(edev, "Memory allocation fails for RX BD ring" + " on socket %u\n", socket_id); rte_free(rxq->sw_rx_ring); rte_free(rxq); return -ENOMEM; @@ -146,9 +146,8 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, NULL); if (rc != ECORE_SUCCESS) { - DP_NOTICE(edev, false, - "Unable to alloc memory for cqe ring on socket %u\n", - socket_id); + DP_ERR(edev, "Memory allocation fails for RX CQE ring" + " on socket %u\n", socket_id); qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring); rte_free(rxq->sw_rx_ring); rte_free(rxq); @@ -365,12 +364,12 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info, uint16_t sb_id) { struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); - struct status_block *sb_virt; + struct status_block_e4 *sb_virt; dma_addr_t sb_phys; int rc; sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, - sizeof(struct status_block)); + sizeof(struct status_block_e4)); if (!sb_virt) { DP_ERR(edev, "Status block allocation failed\n"); return -ENOMEM; @@ -380,7 +379,7 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info, if (rc) { DP_ERR(edev, "Status block initialization failed\n"); OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys, - sizeof(struct status_block)); + sizeof(struct status_block_e4)); return rc; } @@ -454,7 +453,7 @@ void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev) if (fp->sb_info) { OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt, fp->sb_info->sb_phys, - sizeof(struct status_block)); + sizeof(struct status_block_e4)); rte_free(fp->sb_info); fp->sb_info = NULL; } @@ -553,9 +552,10 @@ qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0); /* Prepare ramrod */ memset(¶ms, 0, sizeof(params)); - params.queue_id = rx_queue_id; + params.queue_id = rx_queue_id / edev->num_hwfns; params.vport_id = 0; - params.sb = fp->sb_info->igu_sb_id; + params.stats_id = params.vport_id; + params.p_sb = fp->sb_info; DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n", fp->rxq->queue_id, fp->sb_info->igu_sb_id); params.sb_idx = RX_PI; @@ -611,9 +611,10 @@ qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) txq = eth_dev->data->tx_queues[tx_queue_id]; fp = &qdev->fp_array[tx_queue_id]; memset(¶ms, 0, sizeof(params)); - params.queue_id = tx_queue_id; + params.queue_id = tx_queue_id / edev->num_hwfns; params.vport_id = 0; - params.sb = fp->sb_info->igu_sb_id; + params.stats_id = params.vport_id; + params.p_sb = fp->sb_info; DP_INFO(edev, "txq %u igu_sb_id 0x%x\n", fp->txq->queue_id, fp->sb_info->igu_sb_id); params.sb_idx = TX_PI(0); /* tc = 0 */ @@ -704,7 +705,6 @@ qede_process_tx_compl(__rte_unused struct ecore_dev *edev, qede_free_tx_pkt(txq); } - static int qede_drain_txq(struct qede_dev *qdev, struct qede_tx_queue *txq, bool allow_drain) { @@ -740,7 +740,6 @@ static int qede_drain_txq(struct qede_dev *qdev, return 0; } - /* Stops a given TX queue in the HW */ static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) { @@ -781,7 +780,7 @@ int qede_start_queues(struct rte_eth_dev *eth_dev) { struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); uint8_t id; - int rc; + int rc = -1; for_each_rss(id) { rc = qede_rx_queue_start(eth_dev, id); @@ -845,6 +844,109 @@ static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag) return 0; } +/* Returns outer L3 and L4 packet_type for tunneled packets */ +static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m) +{ + uint32_t packet_type = RTE_PTYPE_UNKNOWN; + struct ether_hdr *eth_hdr; + struct ipv4_hdr *ipv4_hdr; + struct ipv6_hdr *ipv6_hdr; + + eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *); + if (eth_hdr->ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv4)) { + packet_type |= RTE_PTYPE_L3_IPV4; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, + sizeof(struct ether_hdr)); + if (ipv4_hdr->next_proto_id == IPPROTO_TCP) + packet_type |= RTE_PTYPE_L4_TCP; + else if (ipv4_hdr->next_proto_id == IPPROTO_UDP) + packet_type |= RTE_PTYPE_L4_UDP; + } else if (eth_hdr->ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv6)) { + packet_type |= RTE_PTYPE_L3_IPV6; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, + sizeof(struct ether_hdr)); + if (ipv6_hdr->proto == IPPROTO_TCP) + packet_type |= RTE_PTYPE_L4_TCP; + else if (ipv6_hdr->proto == IPPROTO_UDP) + packet_type |= RTE_PTYPE_L4_UDP; + } + + return packet_type; +} + +static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags) +{ + uint16_t val; + + /* Lookup table */ + static const uint32_t + ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = { + [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_TCP | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_TCP | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_UDP | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_UDP | + RTE_PTYPE_INNER_L2_ETHER, + /* Frags with no VLAN */ + [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_FRAG | + RTE_PTYPE_INNER_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_FRAG | + RTE_PTYPE_INNER_L2_ETHER, + /* VLANs */ + [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_TCP | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_TCP | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_UDP | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_UDP | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + /* Frags with VLAN */ + [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 | + RTE_PTYPE_INNER_L4_FRAG | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 | + RTE_PTYPE_INNER_L4_FRAG | + RTE_PTYPE_INNER_L2_ETHER_VLAN, + }; + + /* Bits (0..3) provides L3/L4 protocol type */ + /* Bits (4,5) provides frag and VLAN info */ + val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK << + PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) | + (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK << + PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) | + (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK << + PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) | + (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK << + PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags; + + if (val < QEDE_PKT_TYPE_MAX) + return ptype_lkup_tbl[val]; + + return RTE_PTYPE_UNKNOWN; +} + static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags) { uint16_t val; @@ -852,24 +954,68 @@ static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags) /* Lookup table */ static const uint32_t ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = { - [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4, - [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6, - [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP, - [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP, - [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP, - [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP, + [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_TCP | + RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_TCP | + RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_UDP | + RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_UDP | + RTE_PTYPE_L2_ETHER, + /* Frags with no VLAN */ + [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_FRAG | + RTE_PTYPE_L2_ETHER, + [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_FRAG | + RTE_PTYPE_L2_ETHER, + /* VLANs */ + [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_TCP | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_TCP | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_UDP | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_UDP | + RTE_PTYPE_L2_ETHER_VLAN, + /* Frags with VLAN */ + [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_FRAG | + RTE_PTYPE_L2_ETHER_VLAN, + [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_FRAG | + RTE_PTYPE_L2_ETHER_VLAN, }; /* Bits (0..3) provides L3/L4 protocol type */ + /* Bits (4,5) provides frag and VLAN info */ val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK << PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) | (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK << - PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags; + PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) | + (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK << + PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) | + (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK << + PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags; if (val < QEDE_PKT_TYPE_MAX) - return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER; - else - return RTE_PTYPE_UNKNOWN; + return ptype_lkup_tbl[val]; + + return RTE_PTYPE_UNKNOWN; } static inline uint8_t @@ -918,7 +1064,7 @@ qede_reuse_page(__rte_unused struct qede_dev *qdev, curr_prod = &rxq->sw_rx_ring[idx]; *curr_prod = *curr_cons; - new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) + + new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) + curr_prod->page_offset; rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping)); @@ -1083,7 +1229,7 @@ qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb, pkt_len; if (unlikely(!cur_size)) { PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs" - " left for mapping jumbo", num_segs); + " left for mapping jumbo\n", num_segs); qede_recycle_rx_bd_ring(rxq, qdev, num_segs); return -EINVAL; } @@ -1101,6 +1247,27 @@ qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb, return 0; } +#ifdef RTE_LIBRTE_QEDE_DEBUG_RX +static inline void +print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq, + uint8_t bitfield) +{ + PMD_RX_LOG(INFO, rxq, + "len 0x%x bf 0x%x hash_val 0x%x" + " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s" + " inner_l2=%s inner_l3=%s inner_l4=%s\n", + m->data_len, bitfield, m->hash.rss, + (unsigned long)m->ol_flags, + rte_get_ptype_l2_name(m->packet_type), + rte_get_ptype_l3_name(m->packet_type), + rte_get_ptype_l4_name(m->packet_type), + rte_get_ptype_tunnel_name(m->packet_type), + rte_get_ptype_inner_l2_name(m->packet_type), + rte_get_ptype_inner_l3_name(m->packet_type), + rte_get_ptype_inner_l4_name(m->packet_type)); +} +#endif + uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) { @@ -1121,7 +1288,6 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) uint16_t parse_flag; #ifdef RTE_LIBRTE_QEDE_DEBUG_RX uint8_t bitfield_val; - enum rss_hash_type htype; #endif uint8_t tunn_parse_flag; uint8_t j; @@ -1215,8 +1381,6 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash); #ifdef RTE_LIBRTE_QEDE_DEBUG_RX bitfield_val = fp_cqe->bitfields; - htype = (uint8_t)GET_FIELD(bitfield_val, - ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE); #endif } else { parse_flag = @@ -1227,8 +1391,6 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag); #ifdef RTE_LIBRTE_QEDE_DEBUG_RX bitfield_val = cqe_start_tpa->bitfields; - htype = (uint8_t)GET_FIELD(bitfield_val, - ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE); #endif rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash); } @@ -1248,8 +1410,17 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) else flags = fp_cqe->tunnel_pars_flags.flags; tunn_parse_flag = flags; + /* Tunnel_type */ packet_type = qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag); + + /* Inner header */ + packet_type |= + qede_rx_cqe_to_pkt_type_inner(parse_flag); + + /* Outer L3/L4 types is not available in CQE */ + packet_type |= + qede_rx_cqe_to_pkt_type_outer(rx_mb); } } else { PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n"); @@ -1276,21 +1447,16 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) } } - if (CQE_HAS_VLAN(parse_flag)) { - ol_flags |= PKT_RX_VLAN_PKT; + if (CQE_HAS_VLAN(parse_flag) || + CQE_HAS_OUTER_VLAN(parse_flag)) { + /* Note: FW doesn't indicate Q-in-Q packet */ + ol_flags |= PKT_RX_VLAN; if (qdev->vlan_strip_flg) { ol_flags |= PKT_RX_VLAN_STRIPPED; rx_mb->vlan_tci = vlan_tci; } } - if (CQE_HAS_OUTER_VLAN(parse_flag)) { - ol_flags |= PKT_RX_QINQ_PKT; - if (qdev->vlan_strip_flg) { - rx_mb->vlan_tci = vlan_tci; - ol_flags |= PKT_RX_QINQ_STRIPPED; - } - rx_mb->vlan_tci_outer = 0; - } + /* RSS Hash */ if (qdev->rss_enable) { ol_flags |= PKT_RX_RSS_HASH; @@ -1342,11 +1508,9 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) rx_mb->ol_flags = ol_flags; rx_mb->data_len = len; rx_mb->packet_type = packet_type; - PMD_RX_LOG(INFO, rxq, - "pkt_type 0x%04x len %u hash_type %d hash_val 0x%x" - " ol_flags 0x%04lx\n", - packet_type, len, htype, rx_mb->hash.rss, - (unsigned long)ol_flags); +#ifdef RTE_LIBRTE_QEDE_DEBUG_RX + print_rx_bd_info(rx_mb, rxq, bitfield_val); +#endif if (!tpa_start_flg) { rx_mb->nb_segs = fp_cqe->bd_num; rx_mb->pkt_len = pkt_len; @@ -1383,14 +1547,14 @@ next_cqe: /* Populate scatter gather buffer descriptor fields */ -static inline uint8_t +static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg, struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3) { struct qede_tx_queue *txq = p_txq; struct eth_tx_bd *tx_bd = NULL; dma_addr_t mapping; - uint8_t nb_segs = 0; + uint16_t nb_segs = 0; /* Check for scattered buffers */ while (m_seg) { @@ -1401,7 +1565,7 @@ qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg, memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd)); nb_segs++; } - mapping = rte_mbuf_data_dma_addr(m_seg); + mapping = rte_mbuf_data_iova(m_seg); QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len); PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len); } else if (nb_segs == 1) { @@ -1411,7 +1575,7 @@ qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg, memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd)); nb_segs++; } - mapping = rte_mbuf_data_dma_addr(m_seg); + mapping = rte_mbuf_data_iova(m_seg); QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len); PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len); } else { @@ -1419,7 +1583,7 @@ qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg, ecore_chain_produce(&txq->tx_pbl); memset(tx_bd, 0, sizeof(*tx_bd)); nb_segs++; - mapping = rte_mbuf_data_dma_addr(m_seg); + mapping = rte_mbuf_data_iova(m_seg); QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len); PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len); } @@ -1628,7 +1792,9 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) == PKT_TX_TUNNEL_VXLAN) || ((tx_ol_flags & PKT_TX_TUNNEL_MASK) == - PKT_TX_TUNNEL_MPLSINUDP)) { + PKT_TX_TUNNEL_MPLSINUDP) || + ((tx_ol_flags & PKT_TX_TUNNEL_MASK) == + PKT_TX_TUNNEL_GENEVE)) { /* Check against max which is Tunnel IPv6 + ext */ if (unlikely(txq->nb_tx_avail < ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT)) @@ -1682,12 +1848,6 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) inner_l4_hdr_offset = (mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2; - /* TODO: There's no DPDK flag to request outer - * L4 checksum offload, so we don't do it. - * bd1_bd_flags_bf |= - * ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK << - * ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT; - */ /* Inner L2 size and address type */ bd2_bf1 |= (inner_l2_hdr_size & ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) << @@ -1766,15 +1926,36 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) } /* Offload the IP checksum in the hardware */ - if (tx_ol_flags & PKT_TX_IP_CKSUM) + if (tx_ol_flags & PKT_TX_IP_CKSUM) { bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT; + /* There's no DPDK flag to request outer-L4 csum + * offload. But in the case of tunnel if inner L3 or L4 + * csum offload is requested then we need to force + * recalculation of L4 tunnel header csum also. + */ + if (tunn_flg) { + bd1_bd_flags_bf |= + ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK << + ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT; + } + } /* L4 checksum offload (tcp or udp) */ if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) && (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) { bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT; + /* There's no DPDK flag to request outer-L4 csum + * offload. But in the case of tunnel if inner L3 or L4 + * csum offload is requested then we need to force + * recalculation of L4 tunnel header csum also. + */ + if (tunn_flg) { + bd1_bd_flags_bf |= + ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK << + ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT; + } } /* Fill the entry in the SW ring and the BDs in the FW ring */ @@ -1787,7 +1968,7 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) nbds++; /* Map MBUF linear data for DMA and set in the BD1 */ - QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf), + QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf), mbuf->data_len); bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf); bd1->data.bd_flags.bitfields = bd1_bd_flags_bf; @@ -1800,11 +1981,11 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) nbds++; /* BD1 */ - QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf), + QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf), hdr_size); /* BD2 */ QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size + - rte_mbuf_data_dma_addr(mbuf)), + rte_mbuf_data_iova(mbuf)), mbuf->data_len - hdr_size); bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1); if (mplsoudp_flg) {